JPH058571B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS field effect transistor suitable for ultra-highly integrated circuits.

Traditionally, it was used as a basic component of semiconductor integrated circuits.
Field effect transistors having a MOS (metal-oxide-semiconductor) structure have been used. This feature allows for easy high-density integration and the ability to manufacture high-density ICs in large quantities at low cost.

Generally, MOS type field effect transistor (hereinafter referred to as
The switching speed of a MOS transistor (MOS transistor) increases as the mutual conductance (hereinafter referred to as g _n ) increases, so it is desirable that g _n be large.

By the way, g _n is g _n = (W/L) μ _o C _i V _D (unsaturated region) g _n = (W/L) μ _o C _i (V _G −V _T ′) (saturated region) L is Channel length, W is channel width, C _i is input capacitance, V _D is drain voltage, V _G is gate voltage, V _T ′
is expressed by the equation of threshold voltage.

According to the above formula, it can be understood that in order to increase g _n , it is better to shorten the channel length L.

However, in the structure of a normal MOS transistor, when the channel length L is shortened, the so-called punch-through phenomenon tends to occur, and the withstand voltage between the source and drain decreases.

Therefore, conventional methods have been used to shorten the channel length L without reducing the withstand voltage between the source and drain.
Attempts have been made to increase g _n . FIG. 1 is a process explanatory diagram of a manufacturing method for explaining an example thereof.

Note that in the following description, a depletion region means a region of the opposite conductivity type to the substrate, and an enhancement region means a region of the same conductivity type as the substrate. For example, since there are many holes in a P substrate,
A region of the same conductivity type as the substrate is called an enhancement region, and a region of the opposite conductivity type as the substrate is called a depletion region because the number of holes is small.

In FIG. 1, 1 is a silicon substrate, 2 is a source region, 3 is a drain region, 4 is a silicon dioxide insulating film, and 5 is a silicon dioxide gate insulating film.

On the lower surface side of this gate insulating film 5, depletion regions 6 and 7 are formed adjacent to the source region 2 and drain region 3, respectively.
Furthermore, a gate electrode 8 is formed on the gate insulating film 5 .

A source electrode 9 is connected to the source region 2, and a drain electrode 10 is connected to the drain region 3.

In this structure, depletion regions 6 and 7 are formed by ion implantation using a self-alignment method using gate electrode 8 as a mask.

The aim of the MOS transistor shown in FIG. 1 is that the channel length L is
The length of the enhancement region between the source regions 2 and 2 can be very short, while the length of the
The distance L' between the drain region 3 and the drain region 3 can be made sufficiently longer than the channel length L.

As a result, g _n is large and the source region 2
The main idea is that the breakdown voltage between the drain region 3 and the drain region 3 can also be increased.

However, in the structure shown in FIG. 1, since the gate electrode 8 does not exist above the depletion regions 6 and 7, in order to operate this MOS transistor stably, the depletion regions 6 and 7 are not provided.
The impurity concentration must be considerably high. Therefore, depletion regions 6 and 7 may become extensions of source region 2 and drain region 3. Therefore, there is a drawback that it is difficult to increase the source-drain breakdown voltage.

Furthermore, the source/drain contact holes in conventional silicon gate field effect transistors are self-aligned with respect to the gate.
The following methods are used to form the structure.

In FIG. 1, after forming polysilicon for a gate electrode 8, the gate insulating film 5 underneath is etched using the polysilicon as a mask to form a source and
The Si in the region corresponding to the drain is exposed, and then the silicon substrate 1 is oxidized.

At this time, since the polysilicon in the gate electrode 8 portion contains a high concentration of phosphorus as an impurity, it is oxidized faster (and thicker) than the Si on the surface of the regions 2 and 3 corresponding to the source and drain (11 in Fig. 1). ).

Next, by etching the silicon dioxide film over the entire surface, the regions corresponding to the source and drain are etched.
A state can be realized in which the SiO ₂ film is etched first and the oxide film on the gate polysilicon remains.
As a result, source/drain contact holes can be formed in self-alignment with respect to the gate.

However, with this method, it is difficult to form a sufficiently thick oxide film above the gate polysilicon film. That is, if the oxide film is formed thickly, it may cause misalignment between the source and the drain. Therefore, there is a drawback that the withstand voltage between the source/drain and the gate is lowered.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology.It has a short channel length and high g _n , but has a large source-drain breakdown voltage, and a source-drain-gate breakdown voltage. An object of the present invention is to provide a method for manufacturing a MOS field effect transistor that can be made larger.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2k are process explanatory diagrams of one embodiment. FIG. 2 shows the case of an N-channel MOS transistor.

First, as shown in FIG. 2a, a P-type silicon substrate 41 with a surface direction of 100 mm and a specific resistance of 5 to 20 Ω-cm is coated with a silicon dioxide film (approximately 300 Å thick) 42 and a silicon nitride film 43 (approximately 1500 Å thick). ), a resist pattern 41 is formed on the element forming portion of this silicon nitride film 43 by photolithography.
11 is formed.

Next, using this resist pattern 4111 as a mask, the silicon nitride film 43 is selectively etched by reactive plasma using CF ₄ , and then, using the resist pattern 4111 and the insulating film (silicon nitride film 43) directly below it as a mask, Boron ions are implanted at a dose of 5×10 ¹³ ions/cm ² to form a P ⁺ inversion layer 413.

Next, after removing the resist pattern 4111, the substrate is left in a high temperature oxidation atmosphere (1000°C to 1200°C in WetO ₂ gas), and as shown in FIG.
11 is formed.

Next, a silicon dioxide film 42 is formed as an insulating film.
After removing the silicon nitride film 43, the substrate is left in an oxidizing atmosphere again to form a silicon dioxide film 412 (gate insulating film) with a thickness of about 500 Å.

After that, a thermosetting resin film solution, typically a polyimide resin, is applied to the substrate and cured by heating in air or in an inert gas at a temperature of 100 to 400°C to form a polyimide resin film with a thickness of 1. Form ~5 μm.

Thereafter, a resist mask pattern, an oxide film pattern, an aluminum pattern, or other mask pattern that allows selective etching of the polyimide film, such as a resist mask pattern, an oxide film pattern, or an aluminum pattern, is formed on the gate portion of the polyimide resin film using well-known photolithography technology, and then parallel etching is performed. A vertical profile polyimide film pattern 44 is formed using a flat plate type reactive etching device or an ion etching device.

Next, ion implantation is performed as indicated by the arrows.
For ion implantation, in the case of an N channel, donors of 1×10 ¹³ or less/cm ² are used. Since a polyimide film pattern 44 is provided on the gate insulating film 412, donor ions are implanted into the silicon substrate 41 in areas other than directly under the polyimide film pattern 44 to form depletion regions 45 and 46.

Next, as shown in FIG. 2c, a polysilicon film 47 is deposited on the entire surface of the substrate. As a method for forming the polysilicon film 47, a silicon deposition method using plasma (PRDCVD method) is suitable for this invention.

This is because the heat resistance of the polyimide film pattern 44 is about 500°C, so it is desirable to form the polysilicon film at a temperature of 500°C or lower.
According to the PRDCVD method, a silicon film can be formed at a temperature of 300 to 400°C.

Thereafter, the substrate is etched using a dry etching device having directional etching characteristics, such as a reactive ion etching device using _CF4 gas, or
The entire surface is etched using an Ar ion etching device.

At this time, since the polysilicon film 47 is deposited as thick as the polyimide film thickness on the side wall portion of the polyimide film pattern 44, even when the substrate surface is exposed and etching is completed,
The polysilicon film 47 on the sidewalls of the polyimide film pattern 44 remains as shown in FIG. 2d.

Furthermore, the polyimide film pattern 44 also maintains its structure. Thereafter, phosphorus ions as donors are implanted onto the substrate as shown by the arrows in FIG. 2d, thereby forming an N ⁺ source region 48 and an N ⁺ drain region 49.

Thereafter, as shown in FIG. 2e, a silicon nitride film 50 is formed on the entire surface of the substrate. silicon nitride film 50
In the present invention, it is preferable to form a silicon nitride film using plasma for the same reasons as in the formation of the polysilicon film 47.
In the PRDCVD method, a silicon nitride film is formed at a temperature of approximately 300 to 400°C.

After forming the silicon nitride film 50, the entire surface of the silicon nitride film 50 is etched using a parallel plate type reactive etching device or an ion etching device having directionality.

As for the device profile after this etching, the silicon nitride film 50 on the side wall of the polysilicon film 47 remains unetched, similar to the etched film of the polysilicon film 47 (FIG. 2f).

Next, the polyimide film pattern 44 is removed using a hydrazine etching solution. The device profile at this time is shown in FIG. 2g.

Next, as shown in FIG. 2h, a doped polysilicon film 51 containing phosphorus at a high concentration (5×10 ²³ /cm ² ) is deposited over the entire surface of the substrate. Thereafter, a photoresist is applied, and a resist pattern 52 is formed on the gate portion by a predetermined photolithography.

Next, the entire surface of the substrate is etched using a parallel plate type reactive sputter etching device or an ion etching device, which is the directional etching method described above. Its profile is shown in Figure 2i.

Thereafter, after removing the resist pattern 52, the substrate is left in an oxidizing high temperature atmosphere to convert the surface of the polysilicon film 51 into an oxidized polysilicon film 53 as shown in FIG. 2J.

Next, after openings are formed on the source region 48, drain region 49, and gate region (polysilicon film 51), a metal film 54 is deposited, and a metal wiring pattern is formed by predetermined photolithography. Through the above steps, the MOS transistor is completed.

The thickness of the polysilicon film 47 in the embodiment of the present invention described above can be formed to a thickness of several hundred Å to several μm, and the thickness of the polysilicon film 47 that has been deposited can be
As shown in FIG. 2d, due to the film thickness of
The difference between L' and L' between depletion regions 46, ie (L-L'), can be determined.

Furthermore, as shown in Figures 2i and 2j, phosphorus (or arsenic) is added to a high concentration (approximately 5x
In the step of oxidizing polysilicon containing 10 ²³ pieces/cm ² ), the silicon nitride film 50 prevents oxidation of the polysilicon inside the silicon nitride film, and even in excessive oxidation, the depletion regions 45 and 46
In addition, the polysilicon films 47 and 51 on the enhancement regions are not oxidized, and gate polysilicon is accurately provided on the depletion regions 45 and 46 and the enhancement regions.

Therefore, the thickness of the oxide film on the polysilicon film 51 is
It is easy to obtain a thickness of 5000Å or more, and the subsequent reactive ion etching method (gas is CF _c type)
By etching the entire surface of the substrate using
The Si surface above the source region 48 and drain region 49 is exposed, and a contact hole is formed.

At this time, since the oxide film on the polysilicon films 47 and 51 has a thickness of 5000 Å or more, at least 3500 Å thick is formed on the polysilicon films 47 and 51.
An oxide film thickness of Å or more remains.

Further, the oxide film on the gate sidewall remains as thick as it was before etching.

As a result, the polysilicon film 4 which becomes the gate region
An increase in the mirror effect between 7 and 51 and the drain electrode can be prevented.

In this way, source/drain contact holes can be formed in self-alignment with respect to the gate.

As described above in detail, according to the present invention, the gate electrode can be formed on the relatively low concentration diffusion region corresponding to the depletion region of the embodiment, so the diffusion region does not have to be highly concentrated.
MOS transistors now operate stably,
Since the diffusion region can be maintained at a low concentration (1×10 ¹³ atoms/cm ² or less), a high source-drain breakdown voltage can be achieved. In addition, the oxidation prevention film (silicon nitride film) prevents the polysilicon on the inside from being oxidized, so even if excessive oxidation is performed, the gate polysilicon can be accurately formed over the diffusion region and channel region. can be formed. In addition, since excessive oxidation is possible and a thick oxide film can be formed on the gate polysilicon, it becomes possible to leave a thick oxide film on the gate polysilicon even if the source/drain contacts are opened by self-alignment. Therefore, the breakdown voltage between the source/drain and gate can also be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a method for manufacturing a field effect transistor using a conventional MOS structure, and FIGS. 2a to 2k illustrate an embodiment of a method for manufacturing a MOS type field effect transistor according to the present invention. FIG. 41... Silicon substrate, 412... Silicon dioxide film, 44... Polyimide film pattern, 45, 46...
depletion region, 47, 51... polysilicon film, 48... source region, 49... drain region,
50...Silicon nitride film, 53...Polysilicon oxide film, 54...Metal film.

Claims (1)

[Claims] 1. A step of forming a gate insulating film on the surface of the semiconductor substrate, a step of forming a thermosetting resin mask on the gate insulating film, and then applying the mask to the semiconductor substrate as a blocker. a step of forming a relatively low concentration diffusion region in the semiconductor substrate other than the mask forming region by introducing ions as a first polysilicon layer; and a step of forming a first polysilicon only on the side surfaces of the mask; By introducing ions into the semiconductor substrate using the first polysilicon and the mask as a blocking body, a relatively high concentration source/drain diffusion region is formed in the semiconductor substrate other than the first polysilicon and the mask forming region. forming a silicon nitride film only on the side surfaces of the first polysilicon, and then removing the mask and forming a silicon nitride film to completely cover the first polysilicon and the silicon nitride film. forming a photoresist pattern on the second polysilicon so as to completely cover the silicon nitride film but not completely covering the source/drain diffusion region; etching the second polysilicon using the resist pattern as a mask; and etching the second polysilicon using the silicon nitride film as a stopper.
oxidizing the polysilicon of the first polysilicon, except for the second polysilicon that is surrounded by the first polysilicon and serves as a gate electrode; . A method for manufacturing a MOS field effect transistor, comprising the following steps: forming an electrode electrically connected to the source/drain diffusion region.