JPH058652U - Memory device having error detection and correction circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the reliability of a memory device. [Structure] Since the memory is provided with an error flag section (2c) and an error flag can be added to each address (that is, data) of the memory, statistical processing of errors (recognition of the number of error occurrences and error-prone ICs) (Identification, etc.) can be performed easily.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory device having a function of detecting and correcting an error using the SECDED code. SECDED (Single bit Error Correct Double bit Error Detect) code is an error correction code with a Hamming distance of at least 4 bits for correcting 1-bit error and detecting 2-bit error.

[0002]

[Prior Art]

 The structure of a conventional memory device using SECDED code is shown in FIG. The operation of this memory device is as follows.

During the write cycle to the memory (2), the error correction (EDC) unit (1) receives the data input, generates a SECDED code, and transfers the data via the data bus (MData). Write to the data section (2a) and write the SECDED code to the check code section (2b) via the bus (CB).

On the other hand, during a read cycle from the memory (2), the read data and SECDED code are input to the EDC unit (1), and this EDC unit (1) generates a SECDED code from the data and Perform error checking by comparing the generated code with the read SECDED code. If there is a 1-bit error, correct the error and output the correct data to the master (for example, CPU5) via the bus (Data) and generate the 1-bit error signal (ERR). When there is a 2-bit error, the data cannot be corrected and only an error signal (multi-bit error signal) is generated.

As described above, in this conventional example, even if a 1-bit error occurs in the data in the memory, the EDC unit (1) automatically corrects the error, and the master (5) does not know anything. You don't have to.

[0006]

[Problems to be solved by the device]

 Although it can be seen that a 1-bit error has occurred in the conventional memory device described above, the past error history of the address in which the error occurred is not changed.

Therefore, for example, even if the error is an unrecoverable error due to a hardware failure, such a judgment cannot be made and an appropriate response process cannot be performed. ..

The present invention has been made in view of such a problem, and an object thereof is to identify an error occurrence address and accumulate the history thereof as information to improve the reliability of the memory device. It is in.

[0009]

[Means for Solving the Problems]

 The present invention is a memory device having an error detection / correction circuit having a function of generating a SECDED code and performing an error check of data using this code, in addition to a data storage unit and a SECDED code storage unit, The error flag in the memory is provided with a memory provided with an error flag storage section and a control circuit having a function of controlling the operation of the memory and the error detection / correction circuit and generating and checking an error flag. The address of the storage section corresponds to each address of the data storage section, so that the error flag can be set corresponding to each address of the data storage section. When an error is detected, the control circuit checks whether or not there is an error flag read from the error flag storage section. In the previous cycle, determine whether an error has occurred at the same address and, if it has occurred, record the fact, and if not, generate a new error flag and write it to the error flag storage section. It is characterized by.

[0010]

In the present invention, since the error flag is added to each address (that is, each data) of the memory, statistical processing of the error (for example, the number of times an error occurs, the soft error / hardware based on the number of times the error occurs). It is possible to easily determine the error, identify the place where the error frequently occurs, etc., and thereby improve the reliability of the device.

[0011]

【Example】

 Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

The main difference of this embodiment from the conventional example of FIG. 5 is that an error flag part (2 c) is added to the memory (2) and a counter (4) is provided. The control circuit (3) is provided, and the content of the counter (4) can be checked by the CPU (5) as the master.

Next, the operation will be described. In the write cycle, the EDC unit (1) receives data from the CPU (5) and generates a SECDED code, writes the data to the data section (2a) via the bus (MDATA), and writes the SECDED code to the bus (CB). Write to the check code part (2b) via. Further, the control circuit (3) clears the error flag part (2c) in the memory (2) by the control signal (MCTL).

Since a characteristic operation is performed during the read cycle, description will be made with reference to FIGS. 2A and 2B. Figure 2 (a) shows the operation of the EDC unit (1) and control circuit (3) when a 1-bit error occurred at the same address in the previous cycle, and (b) shows the 1-bit error detected for the first time. The operation when it is performed is shown.

When the control circuit (3) receives the error signal (ERR) from the EDC unit (1) and knows that a 1-bit error has occurred, the control circuit (3) sends a control signal ECTL to the EDC unit (1). The correct data corrected by 1) is sent to the CPU (5) via the bus (Data), and the correct data is also sent to the data section (2a) of the memory (2) via the bus (MData). Let me write. The SECDED code is also written in the check code section (2b) via the bus (CB).

The control circuit (3) reads the error flag (EF) from the error flag unit (2c) in synchronization with the data reading, and determines whether or not the error occurred even when the previous access was made. When the error flag (EF) is set and it is determined that the error is continuous, the control signal (CNT) increments the counter (4). Therefore, the value of the counter (4) represents the number of times that the 1-bit error occurs twice or more at the same address (data). At the same address, there is a very small probability that a soft error (an error in which α-ray data is inverted and data can be corrected by rewriting data) will occur twice within a short time. The value of 4) can be considered as the number of occurrences of 1-bit error due to hardware failure.

On the other hand, as a result of checking the error flag, if the 1-bit error has not occurred in the previous cycle and this is the first time, the EDC unit (1) rewrites the correction data and SECDED code. I do. The control circuit (3) also generates an error flag and writes it in the error flag section (2c) of the memory (2). The counter is not incremented.

The above operation is summarized as shown in FIG. That is, if there is a 1-bit error (step 10), the presence or absence of the previous error is confirmed (step 20). If there is no error, the correction data and code are written, and an error flag is generated and written (step 30). ), If yes, write the correction data and code and increment the counter (step 40).

An example of the operation of the CPU (5) that is the master is shown in FIG. That is, the counter value is periodically measured (step 50), and when it is equal to or higher than a predetermined threshold value (step 60), an alarm (predetermined display, etc.) indicating the occurrence of a hardware failure is generated (step 50). Step 70).

The present invention is not limited to this embodiment and can be modified and applied. For example, the data of the data part (2a) and the flag data of the error flag part (2c) are multiplexed, and the CPU (5) outputs the error flag together with the data via the EDC unit (1). If the data can be read, all the addresses (data) that caused the 1-bit error can be known, and the defective memory cell can be identified reliably and quickly. In addition, the SECDED code for 32-bit data is 7 bits, and when using a memory IC of × 8 bits or × 4 bits, 1 bit is left over. Therefore, if this extra bit is used for an error flag, it is wasted. It does not occur and is efficient.

[0021]

[Effect of the device]

 As described above, the present invention has a configuration in which an error flag can be added to each address (that is, data) of the memory, and therefore statistical processing of errors (such as grasping the number of error occurrences and identification of error-prone ICs) is performed. There is an effect that can be easily done. This has the effect of improving the reliability of the memory device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 (a) shows that the same address is set to 1 in the previous cycle.
The operation of the EDC unit (1) and the control circuit (3) when a bit error has occurred is shown, and (b) shows the operation when a 1-bit error is detected for the first time.

FIG. 3 is a flowchart showing operations of an EDC unit (1) and a control circuit (3).

FIG. 4 is a flowchart showing an operation of a CPU (5).

FIG. 5 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

1 EDC (Error Detection and Correction) unit 2 Memory 3 Control circuit 4 Counter 5 CPU

Claims (1)

[Claims for utility model registration] [Claim 1] An error detection and correction circuit (1) having a function of generating a SECDED (single bit error correction double bit error detection) code and performing an error check of data using this code A memory device comprising: a data storage section (2a), a SECDED code storage section (2b),
Memory (2) with error flag storage (2c)
And this memory (2) and the error detection and correction circuit (1)
And a control circuit (3) having a function of generating and checking an error flag and controlling the operation of the error flag storage unit (2c) in the memory (2). ) Corresponds to each address of the data storage section (2a), and the error flag can be set corresponding to each address of the data storage section (2a). Then, the control circuit (3) checks the presence or absence of the error flag read from the error flag storage section (2c) to determine whether or not an error has occurred at the same address in the previous cycle. If so, the fact is recorded, and if not, an error flag is newly generated and written in the error flag storage section (2c). Memory device having a circuit.