JPH05868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a silicon (Si) gate MOS type integrated circuit.

A conventional Si gate MOS type integrated circuit and its manufacturing method will be explained with reference to FIG. 1st
In the figure, 1 is a silicon Si substrate, 3 is a Si substrate 1
Gate polysilicon 4 and 5 are formed on the silicon substrate 1 with a gate oxide film 2 interposed therebetween, and are source and drain diffusion layers formed on the Si substrate 1 on both sides of the gate portion.

In the Si gate MOS type integrated circuit as described above, the source/drain diffusion layers 4 and 5 are formed on the Si substrate 1 by a self-alignment method using the gate polysilicon as a mask for diffusion.

However, in the Si gate MOS type integrated circuit shown in FIG. This causes a so-called short channel effect, which slows down the operating speed due to parasitic capacitance between the gate and the drain or source, and becomes a factor that makes the transistor characteristics unstable.

This invention was made in view of the above-mentioned circumstances, and by forming an insulating film on the side surfaces of the gate polysilicon and suppressing the spread of the source/drain diffusion layer below the gate, the operation speed is high and the transistor An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can obtain a Si gate MOS type integrated circuit with good characteristics.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 4.

First, as shown in FIG. 2, after gate oxidation on a wafer, which is a Si substrate 11, impurity-doped polysilicon is deposited on the entire surface, followed by photolithography and patterning.
Gate oxide film 12 and gate polysilicon 13 on top
A gate portion is formed. Next, reduced pressure CVD
A phosphosilicate glass (PSG) film 18 is formed on the entire surface of the Si substrate 11 by a method. The formation of this PSG film 18 is carried out at a reaction pressure of 1 atm or less, preferably about 1 to 1 atm.
It is formed by reacting SiH ₄ , O ₂ and PH ₃ gas at 10 ^-2 Torr and a reaction temperature of about 400°C. Next, this is immersed in a dilute HF solution such as a 1% HF solution, and as shown in FIG. 3, light etching is performed to the extent that only the side surfaces of the gate polysilicon 13 are exposed and the other parts remain unetched. Do this. Growth temperature mentioned above
When the PSG film 18 formed by SiH ₄ -O ₂ -based low pressure CVD method at about 400°C has a stepped portion on the base,
The film quality on the side surface is poorer than on other parts, and the etching rate with the HF solution is much faster than on other parts, so that the structure shown in FIG. 3 is obtained. Next, thermal oxidation is performed to form an insulating film 19 made of SiO ₂ film only on the side surfaces of the gate polysilicon 13.
is formed, and then the PSG film 18 is removed using an HF-based liquid. In this case, since the etching rate of the insulating film 19 is much slower than that of the PSG film 18, it remains unetched, resulting in the structure shown in FIG. 4. Furthermore, after that, the gate polysilicon 13
The source/drain diffusion layers 14 and 15 are formed using the normal self-alignment method using the insulating film 19 as a diffusion mask.
form. In this case, as shown in Figure 4,
Since lateral diffusion starts from points S and D at the outer edge of the insulating film 19, the overlapping portion 1 between the polysilicon 13 under the gate and the source/drain diffusion layers 14 and 15
6 and 17 can be made smaller.

In addition, by the reduced pressure CVD method of the above-mentioned example
Instead of the PSG film 18, this ^invention
50KHz to SiH ₄ −N ₂ O gas under Torr pressure
The same process can be performed using a SiO ₂ film formed by plasma CVD by applying a high frequency voltage of 13.56 MHz.

As explained above, according to the present invention, an insulating film for suppressing the spread of the diffusion layer below the gate is formed on the side surface of the gate polysilicon. The overlap between the layers can be made smaller compared to conventional ones, the so-called short channel effect is reduced, transistor characteristics are stabilized, parasitic capacitance is reduced, and operation speed is improved. This has the effect of preventing insulation deterioration of the oxide film. Furthermore, according to the present invention, an insulating film is formed on the side surface of the gate polysilicon by thermal oxidation while the substrate surface in the region where the source/drain is to be formed is covered with a mask layer of phosphosilicate glass film or silicon oxide film. When this insulating film is formed, the regions where the source and drain are to be formed are hardly oxidized, which prevents the harmful effects of unnecessary oxide film formation, such as the generation of crystal defects and the intrusion of metal contamination into the substrate. There is an effect that it can be done. Furthermore, in a method in which the side surfaces of the gate are thermally oxidized after forming the source/drain diffusion layer and there is no mask on the source/drain diffusion layer, the high concentration impurity region on the surface of the source/drain diffusion layer is oxidized during the thermal oxidation. However, in this invention, the source/drain diffusion layer is formed after thermally oxidizing the side surface of the gate polysilicon. According to this method, the impurity concentration of the source/drain diffusion layer is not affected by thermal oxidation of the gate side surface, and the impurity concentration of the source/drain diffusion layer can be set freely, and the source/drain diffusion layer has sufficiently low resistance. It has the effect of forming

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the gate part and its vicinity of a conventional Si gate MOS integrated circuit, Figures 2 and 3 are
Fig. 4 shows a Si gate according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a gate portion and its vicinity, showing a method for manufacturing a MOS integrated circuit in the order of steps. 11...Si substrate, 12...gate oxide film, 13
... Gate polysilicon, 14, 15 ... Source/drain diffusion layer, 16, 17 ... Overlapping portion, 18 ... PSG film, 19 ... Insulating film.

Claims (1)

[Claims] 1. In manufacturing a silicon gate MOS type integrated circuit, there is a step of forming gate polysilicon on a silicon substrate, and forming a phosphosilicate glass film or a silicon oxide film on the silicon substrate and the gate polysilicon. a step of performing selective etching to expose the side surfaces of the gate polysilicon and leaving a mask layer made of the phosphosilicate glass film or the silicon oxide film on the silicon substrate and the gate polysilicon; forming a source/drain diffusion layer on the silicon substrate on both sides of the insulating film using the gate polysilicon and the insulating film as a mask; A method for manufacturing a semiconductor integrated circuit, comprising sequentially performing the following steps.