JPH0590159A - Production of polycrystalline semiconductor film - Google Patents
Production of polycrystalline semiconductor filmInfo
- Publication number
- JPH0590159A JPH0590159A JP3278705A JP27870591A JPH0590159A JP H0590159 A JPH0590159 A JP H0590159A JP 3278705 A JP3278705 A JP 3278705A JP 27870591 A JP27870591 A JP 27870591A JP H0590159 A JPH0590159 A JP H0590159A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor film
- recesses
- silicon
- board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000843 powder Substances 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 16
- 239000011863 silicon-based powder Substances 0.000 claims description 12
- 238000005245 sintering Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 239000011521 glass Substances 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 14
- 239000003960 organic solvent Substances 0.000 abstract description 3
- 239000011159 matrix material Substances 0.000 abstract description 2
- 239000002904 solvent Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 40
- 239000013078 crystal Substances 0.000 description 39
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000012298 atmosphere Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000007790 solid phase Substances 0.000 description 5
- 239000012808 vapor phase Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、結晶粒径を制御したか
たちで生成させ、しかも結晶粒径がそろった多結晶半導
体膜の作製方法に関するものである。変換装置、薄膜ト
ランジスタ等の半導体装置に用いることができるもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a polycrystalline semiconductor film having a uniform crystal grain size, which is produced in a controlled crystal grain size. It can be used for a semiconductor device such as a conversion device and a thin film transistor.
【0002】[0002]
【0003】従来、多結晶半導体膜を作製する方法とし
ては、例えば珪素の場合、溶融した珪素中から多結晶珪
素の芯を用いて液相成長によってバルク状の多結晶珪素
半導体を得る方法や、気相化学反応法等によって成膜さ
れた非晶質珪素半導体膜を加熱することによって固相成
長させ多結晶珪素半導体を得る方法、さらにはガラス基
板上等に成膜された非晶質珪素半導体膜に対してレーザ
ー照射を行うことによって多結晶珪素半導体膜を得る方
法等が知られている。Conventionally, as a method of producing a polycrystalline semiconductor film, for example, in the case of silicon, a method of obtaining a bulk polycrystalline silicon semiconductor by liquid phase growth from a molten silicon core using polycrystalline silicon, A method for obtaining a polycrystalline silicon semiconductor by solid-phase growth by heating an amorphous silicon semiconductor film formed by a vapor phase chemical reaction method or the like, and further an amorphous silicon semiconductor formed on a glass substrate or the like. A method of obtaining a polycrystalline silicon semiconductor film by performing laser irradiation on the film is known.
【0004】特に、ガラス基板上等に気相化学反応法で
非晶質半導体膜を成膜し、この非晶質半導体膜を加熱す
ることによって結晶化させる方法(固相成長法と呼ばれ
る)は、低コストであり、大面積化が可能であるという
点で、太陽電池、TFT(薄膜トランジスタ)等に応用
することがさかんに研究されている。In particular, a method of forming an amorphous semiconductor film on a glass substrate or the like by a vapor phase chemical reaction method and crystallizing the amorphous semiconductor film by heating (called a solid phase growth method) is In view of low cost and large area, application to solar cells, TFTs (thin film transistors), etc. has been vigorously studied.
【0005】[0005]
【発明が解決しようとする課題】しかしながら上記従来
の固相成長によって得られる多結晶珪素半導体膜は、そ
の核発生数や結晶粒径を制御すことが困難であるという
問題があった。特に、不均一な粒径に起因する欠損の存
在や不純物の存在が問題とされていた。However, the polycrystalline silicon semiconductor film obtained by the conventional solid phase growth has a problem that it is difficult to control the number of nuclei generated and the crystal grain size. In particular, the presence of defects and the presence of impurities due to the nonuniform particle size have been problems.
【0006】[0006]
【課題を解決するための手段】本発明は、結晶核の発生
数と結晶粒径を制御するために珪素の微粉末をこの珪素
の微粉末と概略同じ大きさを有した凹部を設けた基板上
に塗布する工程と、この基板上に塗布された珪素の微粉
末を焼結する工程と、該工程の後非晶質珪素半導体膜を
製膜する工程と、該工程の後加熱することによって前記
非晶質珪素半導体膜を結晶化させる工程とを有すること
を特徴とする多結晶半導体膜作製方法である。According to the present invention, in order to control the number of crystal nuclei generated and the crystal grain size, a fine silicon powder is provided on a substrate provided with recesses having substantially the same size as the fine silicon powder. A step of applying the above, a step of sintering the fine powder of silicon applied on the substrate, a step of forming an amorphous silicon semiconductor film after the step, and a heating after the step. And a step of crystallizing the amorphous silicon semiconductor film.
【0007】上記本発明の構成において、基板として
は、ガラス基板、単結晶または多結晶のシリコンウェ
ハ、さらには絶縁体または半導体の基板を用いることが
できる。In the above structure of the present invention, as the substrate, a glass substrate, a monocrystalline or polycrystalline silicon wafer, and an insulating or semiconductor substrate can be used.
【0008】珪素の微粉末と概略同じ大きさの凹部を基
板上に設けるというのは、凹部の窪みの部分の大きさを
珪素の微粉末の大きさ(微粉末の直径)と概略合わせる
ということである。Providing a recess having substantially the same size as the fine silicon powder on the substrate means that the size of the recessed portion of the recess is approximately matched with the size of the fine silicon powder (diameter of the fine powder). Is.
【0009】本発明は、珪素の微粉末を結晶核として珪
素の結晶粒を成長させることによって多結晶珪素膜を形
成することを目的とするものである。そこで、本発明の
構成においては、結晶核となる珪素の微粉末を基板上に
定着させた後に非晶質珪素半導体膜を気相化学反応法等
で成膜し、550度〜800度程度の温度で加熱するこ
とによって結晶化させるのである。An object of the present invention is to form a polycrystalline silicon film by growing crystal grains of silicon using fine powder of silicon as a crystal nucleus. Therefore, in the structure of the present invention, fine silicon powder serving as crystal nuclei is fixed on the substrate, and then an amorphous silicon semiconductor film is formed by a vapor phase chemical reaction method or the like, and the amorphous silicon semiconductor film is formed at about 550 to 800 degrees. It is crystallized by heating at temperature.
【0010】作製される結晶粒径の大きさを制御するに
は、基板上に設けられる凹部の大きさと間隔、さらには
珪素の微粉末の大きさを制御することによって行うこと
ができる。もちろんこの場合、珪素の微粉末に結晶性を
有しているもの(好ましくは単結晶のもの)を用いるこ
とが重要である。なぜならば、この微粉末を結晶核とし
て結晶が成長するからである。The size of the crystal grain size to be produced can be controlled by controlling the size and interval of the recesses provided on the substrate and the size of the fine silicon powder. In this case, of course, it is important to use fine silicon powder having crystallinity (preferably single crystal). This is because crystals grow using this fine powder as crystal nuclei.
【0011】本明細書中における結晶の粒径とは、基板
の上面方向からみた結晶の大きさを示すものである。本
発明の構成のように基板上に形成される薄膜状の多結晶
珪素半導体膜は、柱状に成長することが知られており、
本明細書中においてはこの柱状の結晶の柱の直径に相当
する部分を粒径と定義する。また、珪素の微粉末の大き
さは、この微粉末の直径と定義する。The grain size of the crystal in this specification indicates the size of the crystal seen from the upper surface direction of the substrate. It is known that the thin film-like polycrystalline silicon semiconductor film formed on the substrate as in the structure of the present invention grows in a column shape,
In this specification, the portion corresponding to the diameter of the column of the columnar crystal is defined as the grain size. The size of the fine powder of silicon is defined as the diameter of the fine powder.
【0012】具体的に結晶粒径を制御する方法として
は、基板表面上に設けられる凹部の大きさを変化させる
ことで、その大きさに従った結晶粒を得ることができ
る。もちろんこの場合、凹部の大きさよりも結晶核とな
る凹部の大きさが小さいことが条件である。また、結晶
核となる珪素の微粉末の大きさを変化させることによっ
て結晶粒径の大きさを変化させることがでる。Specifically, as a method of controlling the crystal grain size, the size of the concave portion provided on the surface of the substrate is changed to obtain crystal grains according to the size. In this case, of course, the condition is that the size of the recess that becomes the crystal nucleus is smaller than the size of the recess. Further, the size of the crystal grain size can be changed by changing the size of the fine powder of silicon that becomes the crystal nuclei.
【0013】また、結晶核となる珪素の微粉末同士が結
合して多結晶珪素半導体膜になる場合もあり、この場合
は微粉末の大きさと、結晶粒径の大きさはほとんど同じ
になる。もちろん、結晶は粒状に成長していくのである
から珪素の微粉末を結晶核として成長することに変わり
はない。In addition, there are cases where fine silicon powders serving as crystal nuclei are bonded to each other to form a polycrystalline silicon semiconductor film. In this case, the size of the fine powders and the size of the crystal grain size are almost the same. Of course, since the crystal grows in a granular form, it is still the case that the fine powder of silicon grows as a crystal nucleus.
【0014】結晶粒がそろった状態で多結晶珪素半導体
膜を得ることは、均一な膜質を大面積にわたって必要と
する太陽電池にとっては重要なことである。大粒径の結
晶をそろえることで最良の電気特性を有した多結晶珪素
半導体膜を得ることができる。これは、結晶の粒界すな
わち結晶粒と結晶粒の境に格子欠陥や半導体の電気的特
性に悪影響を与える不純物が存在しており、これら格子
欠陥や不純物の影響を最小限に抑えるために均質に大粒
径の結晶をそろえて設けることによってこの粒界の面積
の割合を最小限にすることができるからである。Obtaining a polycrystalline silicon semiconductor film in a state where crystal grains are uniform is important for a solar cell which requires uniform film quality over a large area. By arranging crystals of large grain size, a polycrystalline silicon semiconductor film having the best electric characteristics can be obtained. This is because there are lattice defects and impurities that adversely affect the electrical characteristics of the semiconductor at the grain boundaries of the crystal, that is, the boundaries between the crystal grains, and they are homogeneous to minimize the effects of these lattice defects and impurities. This is because the ratio of the area of this grain boundary can be minimized by arranging the crystals of large grain size.
【0015】[0015]
【実施例】〔実施例1〕本実施例は、図1に示すように
10μm間隔で設けた凹部、別な見方をするならば10
μm間隔で設けられた10μmの幅を有する凸部を基板
上に設けたものである。また、基板上に10μm間隔で
凹凸を付けたものであるということもできる。以下その
作製工程を説明する。[Embodiment 1] In this embodiment, as shown in FIG. 1, recesses provided at intervals of 10 .mu.m.
The convex portions having a width of 10 μm and provided at intervals of μm are provided on the substrate. It can also be said that unevenness is provided on the substrate at intervals of 10 μm. The manufacturing process will be described below.
【0016】本実施例においては、基板としてコーニン
グ7059ガラス基板(以下ガラス基板と記載する)を
用いた。In this example, a Corning 7059 glass substrate (hereinafter referred to as a glass substrate) was used as the substrate.
【0017】まずガラス基板1上にレジスト2(ポジ型
でもネガ型でもよい)を塗布し、公知のフォトリソグラ
フィー工程を経ることによって図1に示すようなパター
ンをガラス基板上を形成する。そして、化学的にガラス
基板をエッチングすることによってガラス基板1を0.
1μm〜2μm本実施例においては約0.3μmの深さ
にエッチングする。そしてレジストを除去することによ
って凹部を形成する。First, a resist 2 (which may be a positive type or a negative type) is applied on the glass substrate 1 and a known photolithography process is performed to form a pattern as shown in FIG. 1 on the glass substrate. Then, the glass substrate 1 is removed by chemically etching it.
1 μm to 2 μm In this embodiment, etching is performed to a depth of about 0.3 μm. Then, the resist is removed to form a recess.
【0018】図1には基板を断面方向から見た断面図が
示されているが、この断面から角度にして90°異なる
方向から見た断面図も図1と同様である。すなわち、こ
の凹部は碁盤の目のように設けられているのであり、1
0mμ間隔に凹部がマトリックス状に設けられているの
である。FIG. 1 shows a cross-sectional view of the substrate viewed from the cross-sectional direction, but the cross-sectional view viewed from a direction different from this cross-section by 90 ° is also the same as FIG. In other words, this concave portion is provided like a grid pattern.
The recesses are provided in a matrix at intervals of 0 mμ.
【0019】前記工程において形成した深さ約0.3μ
mの凹部を有するガラス基板上に大きさが約10μmの
珪素の微粉末を有機溶剤に溶かして塗布した。そして3
00度で1時間の時間をかけ有機溶剤を飛ばすことによ
って、珪素の微粉末をガラス基板上に固着(定着)させ
た。このようにして珪素の微粉末をガラス基板上に設け
た凹部に配置させることができた。The depth formed in the above process is about 0.3 μm.
On a glass substrate having m recesses, fine powder of silicon having a size of about 10 μm was dissolved in an organic solvent and applied. And 3
The fine powder of silicon was fixed (fixed) on the glass substrate by blowing off the organic solvent at 00 ° C. for 1 hour. In this way, the fine silicon powder could be placed in the recesses provided on the glass substrate.
【0020】つぎに、前記工程において凹部に珪素の微
粉末が配置させられたガラス基板上にプラズマ気相反応
方法によって非晶質珪素半導体膜を10μmの厚さに形
成した。成膜条件は、 雰囲気 SiH4 (流量10〜100sccm) 基板温度 100〜400度 成膜圧力 0.01〜1.00Torr 高周波電力(13.56MHz) 10〜80W である。Next, an amorphous silicon semiconductor film having a thickness of 10 μm was formed on the glass substrate, in which fine silicon powder was placed in the recesses in the above step, by the plasma vapor phase reaction method. The film forming conditions are atmosphere SiH 4 (flow rate 10 to 100 sccm) substrate temperature 100 to 400 degrees, film forming pressure 0.01 to 1.00 Torr high frequency power (13.56 MHz) 10 to 80 W.
【0021】前記工程によって成膜した非晶質珪素半導
体膜を600度の温度で24時間加熱することによって
結晶を固相成長させ、多結晶珪素半導体膜をガラス基板
上形成した。この固相成長すなわち非晶質珪素を結晶化
させるための加熱工程は、550度から800度の温度
範囲において可能であり、その加熱時間も膜厚等の成膜
条件の違いによって2時間〜96時間程度の範囲で可能
である。The amorphous silicon semiconductor film formed by the above process was heated at a temperature of 600 ° C. for 24 hours to cause solid phase growth of crystals to form a polycrystalline silicon semiconductor film on a glass substrate. This solid-phase growth, that is, the heating process for crystallizing amorphous silicon can be performed in the temperature range of 550 to 800 ° C., and the heating time is 2 hours to 96 hours depending on the film forming conditions such as film thickness. It is possible within a time range.
【0022】本実施例において作製した多結晶珪素半導
体膜を断面SEM写真によって観察を行ったところ、結
晶の粒径が約10μmであり、結晶粒のそろった多結晶
珪素半導体膜を得ることができた。When the polycrystalline silicon semiconductor film produced in this example was observed by a cross-sectional SEM photograph, the grain size of the crystal was about 10 μm, and a polycrystalline silicon semiconductor film with uniform crystal grains could be obtained. It was
【0023】〔実施例2〕本実施例は、実施例1と同様
な結晶成長方法を用いることによって、基板側からPI
N構造を有する光電変換装置すなわち太陽電池を作製し
たものである。[Embodiment 2] In this embodiment, the same crystal growth method as in Embodiment 1 is used, and the PI is applied from the substrate side.
A photoelectric conversion device having an N structure, that is, a solar cell is manufactured.
【0024】本実施例には、コーニング7059ガラス
基板上に高濃度にN型の導電型を付与する不純物を添加
した裏面電極となる非晶質半導体、その上にN型の導電
型を有する非単結晶半導体膜、さらにI型となる真性ま
たは実質的に真性(不純物を人為的に添加していないと
いう意味)の非晶質珪素半導体膜、さらにP型の導電型
を有する非晶質半導体膜を積層し、600度,24時間
の温度で加熱することによって、多結晶化したものであ
る。In this embodiment, an amorphous semiconductor serving as a back electrode is prepared by adding an impurity imparting N-type conductivity to a Corning 7059 glass substrate at a high concentration, and a non-type semiconductor having N-type conductivity is formed thereon. A single crystal semiconductor film, an i-type intrinsic or substantially intrinsic (meaning that no impurities are artificially added) amorphous silicon semiconductor film, and an amorphous semiconductor film having a p-type conductivity type Are laminated and heated at a temperature of 600 ° C. for 24 hours to be polycrystallized.
【0025】本発明の構成のようにガラス基板表面から
結晶核を成長させる場合、前述のように結晶は柱状に成
長するので、上記のようにNIPと異なる導電型を有す
る半導体層を積層しても、層全体を結晶化させることが
できる。すなわち基板とN層との界面で珪素の微粉末を
結晶核として発生した結晶は、I層そしてP層と連続的
に柱状に成長していくのである。When crystal nuclei are grown from the glass substrate surface as in the structure of the present invention, the crystals grow in a columnar shape as described above. Therefore, as described above, semiconductor layers having a conductivity type different from NIP are laminated. Also, the entire layer can be crystallized. That is, the crystal generated from the fine powder of silicon as crystal nuclei at the interface between the substrate and the N layer grows in columnar shape continuously with the I layer and the P layer.
【0026】以下本実施における裏面電極並びにNIP
各層の非晶質珪素半導体の作製条件を示す。電極となる
N+ 層の成膜条件は、 雰囲気 SiH4 (流量50sccm)(P
H3 1000ppm添加) 基板温度 100〜400度 成膜圧力 0.01〜1.00Torr 高周波電力 10〜80W(13.56MHz) であり、7000Åの厚さに成膜した。The back electrode and NIP in this embodiment will be described below.
The manufacturing conditions of the amorphous silicon semiconductor of each layer are shown below. The conditions for forming the N + layer to be the electrode are as follows: atmosphere SiH 4 (flow rate 50 sccm) (P
H 3 1000 ppm added) substrate temperature 100 to 400 degrees deposition pressure 0.01~1.00Torr frequency power 10~80W (13.56MHz), was deposited to a thickness of 7000 Å.
【0027】N層の成膜条件は、 雰囲気 SiH4 (50sccm)(PH3
10ppm添加) 基板温度 100〜400度 成膜圧力 0.01〜1.00Torr 高周波電力 10〜80W(13.56MHz) であり、500Åの厚さに成膜した。The N layer is formed under the following conditions: atmosphere SiH 4 (50 sccm) (PH 3
Addition of 10 ppm) Substrate temperature 100 to 400 degrees Film forming pressure 0.01 to 1.00 Torr High frequency power 10 to 80 W (13.56 MHz), and a film having a thickness of 500 Å was formed.
【0028】I層の成膜条件は、 雰囲気 SiH4 (10〜100sccm) 基板温度 100〜400度 成膜圧力 0.01〜1.00Torr 高周波電力 10〜80W(13.56MHz) であり、10μmの厚さに成膜した。The film forming conditions for the I layer are as follows: atmosphere SiH 4 (10 to 100 sccm) substrate temperature 100 to 400 ° C. film forming pressure 0.01 to 1.00 Torr high frequency power 10 to 80 W (13.56 MHz) at 10 μm. The film was formed to a thickness.
【0029】P層の成膜条件は、 雰囲気 SiH4 (50sccm)(B2H
6 10ppm添加) 基板温度 100〜400度 成膜圧力 0.01〜1.00Torr 高周波電力 10〜80W(13.56MHz) であり、500Åの厚さに成膜した。The P layer is formed under the following conditions: atmosphere SiH 4 (50 sccm) (B 2 H
6 10 ppm added) Substrate temperature 100 to 400 degrees Film forming pressure 0.01 to 1.00 Torr High frequency power 10 to 80 W (13.56 MHz), and film was formed to a thickness of 500 Å.
【0030】その後、N2 雰囲気中において600度の
温度で24時間加熱し、結晶化を行った。この結晶化の
ための加熱は450度〜800度好ましくは550度か
ら700度の温度で可能である。After that, crystallization was performed by heating in an N 2 atmosphere at a temperature of 600 ° C. for 24 hours. The heating for this crystallization can be carried out at a temperature of 450 to 800 degrees, preferably 550 to 700 degrees.
【0031】本実施例のような構成をとることによっ
て、結晶粒径のそろった多結晶半導体膜を用いた太陽電
池を得ることができた。By adopting the structure as in this example, a solar cell using a polycrystalline semiconductor film having a uniform crystal grain size could be obtained.
【0032】[0032]
【発明の効果】本発明の構成のように基板に凹部を周期
的に設け、その凹部に珪素の微粉末を固着させ、その上
に非晶質珪素を成膜し、加熱結晶化させることで、結晶
粒径のそろった多結晶珪素半導体膜を得ることができ
た。そして、本発明の構成をとることによって得られる
多結晶珪素半導体膜は、太陽電池,薄膜トランジスタの
チャネル形成領域やソース,ドレイン領域の半導体層,
他の半導体装置に応用することができる。According to the structure of the present invention, concave portions are periodically provided in the substrate, fine silicon powder is fixed to the concave portions, and amorphous silicon is deposited on the fine particles and crystallized by heating. A polycrystalline silicon semiconductor film having a uniform crystal grain size could be obtained. The polycrystalline silicon semiconductor film obtained by adopting the structure of the present invention is a semiconductor layer of a solar cell, a channel forming region of a thin film transistor, a source and a drain region,
It can be applied to other semiconductor devices.
【0033】以上の説明においては、珪素を例として説
明を行ってきたが、珪素以外の半導体を用いることも可
能である。そして、非晶質半導体の成膜方法もプラズマ
CVD法に限定されず、他のCVD法やスパッタ法等を
用いてもよい。In the above description, silicon has been described as an example, but a semiconductor other than silicon can be used. The method for depositing the amorphous semiconductor is not limited to the plasma CVD method, and other CVD method, sputtering method, or the like may be used.
【図1】 本発明の構成を用いた実施例1における基板
の加工工程を示すものである。FIG. 1 shows a substrate processing step in a first embodiment using the configuration of the present invention.
1 ガラス基板 2 レジスト 1 glass substrate 2 resist
Claims (1)
結する工程と、該工程の後非晶質半導体膜を成膜する工
程と、該工程の後前記非晶質半導体膜を多結晶化させる
ための加熱をする工程とを有することを特徴とする多結
晶半導体膜作製方法であって、 前記基板には、前記珪素の微粉末と概略同一の大きさを
有する凹部が形成されていることを特徴とする多結晶半
導体膜作製方法。1. A step of coating fine silicon powder on a substrate and then sintering, a step of forming an amorphous semiconductor film after the step, and a step of forming the amorphous semiconductor film after the step. And a step of heating for polycrystallization, wherein a recess having a size substantially the same as that of the fine powder of silicon is formed in the substrate. And a method for manufacturing a polycrystalline semiconductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03278705A JP3105310B2 (en) | 1991-09-30 | 1991-09-30 | Polycrystalline semiconductor film and thin film transistor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03278705A JP3105310B2 (en) | 1991-09-30 | 1991-09-30 | Polycrystalline semiconductor film and thin film transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0590159A true JPH0590159A (en) | 1993-04-09 |
| JP3105310B2 JP3105310B2 (en) | 2000-10-30 |
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ID=17601045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03278705A Expired - Fee Related JP3105310B2 (en) | 1991-09-30 | 1991-09-30 | Polycrystalline semiconductor film and thin film transistor manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6424008B1 (en) | 1992-10-30 | 2002-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Memory device having a floating gate |
| US7750347B2 (en) | 1997-08-19 | 2010-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and semiconductor display device |
-
1991
- 1991-09-30 JP JP03278705A patent/JP3105310B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6424008B1 (en) | 1992-10-30 | 2002-07-23 | Semiconductor Energy Laboratory Co., Ltd. | Memory device having a floating gate |
| US7622343B2 (en) | 1992-10-30 | 2009-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Laser processing method, method for forming a flash memory, insulated gate semiconductor device and method for forming the same |
| US7750347B2 (en) | 1997-08-19 | 2010-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and semiconductor display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3105310B2 (en) | 2000-10-30 |
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