JPH0591319A - Black level adjustment circuit - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To obtain a black level adjustment circuit that can automatically and easily and accurately adjust the black level. A digital image signal output from an A / D converter is compared with a dark signal comparison value in a dark signal determination means 21 to output a dark signal level determination signal. next,
The dark signal adjusting means 22 generates a level adjustment signal from the dark signal level determination signal and feeds it back to the A / D converter to automatically adjust the black level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a black level adjusting circuit for adjusting a dark signal in analog image information, and for example, a black level adjusting circuit for image information read by an image scanner which is an image reading device. It is about.

[0002]

2. Description of the Related Art When a CCD image sensor is used as an image scanner, the output of the CCD image sensor is output from the dark output voltage portion, and this output is obtained as analog image information. Therefore, black level adjustment is performed as signal processing. Is what you need. As an example of this black level adjustment, the one shown in FIG. 5 is conventionally known. In FIG. 5, reference numeral 1 denotes an image sensor such as a CCD image sensor, which converts the image information of the document illuminated by the reading light source into an electric signal and outputs it as analog image information. 2 is an all-pixel sample / hold circuit that receives analog image information from the image sensor and samples / holds a signal for every pixel of the analog image information. 3 receives analog image information from the image sensor 1. A dark signal sample / hold for sampling / holding a dark signal of analog image information.

Reference numeral 4 designates all of these pixels and dark signal samples /
A differential amplifier that receives the sample / hold potentials from the holds 2 and 3 and amplifies the potential difference between the sample / hold potentials is for correcting the black level. 5 is a variable resistor for adjusting the offset of this differential amplifier,
6 receives the output from the differential amplifier 4 and outputs analog /
An A / D converter for digital conversion, in which a white reference voltage is input as a reference high level voltage and a ground voltage is input as a reference low level voltage. The circuit composed of all the pixels and the dark signal sample / hold circuits 2 and 3 and the differential amplifier 4 is described in "Toshiba integrated circuit technical data CCD image sensor (linear sensor)" (published by Toshiba Corporation. It is shown as an instantaneous output compensation circuit in FIGS. 6-18 on page 54 of the publication year: 1989).

Next, the operation of the circuit thus configured will be described. First, the image information written or displayed on the document illuminated by the reading light source by the image sensor 1 is converted into an electric signal. The read signal in the analog image information converted into an electric signal by the image sensor 1 is sampled / held for all pixels by the all-pixel sample / hold circuit 2, and the dark signal in the analog image information is a dark signal sample. / Hold circuit 3 samples / holds.

The potentials sampled / held in all the pixels and the dark signal sample / hold circuits 2 and 3 are
By being differentially amplified by the differential amplifier 4, the black level of the analog image information is corrected and output. That is, the black level adjustment of the analog image information from the image sensor 1 is performed by correcting the dark signal of the analog image information. The analog information from the differential amplifier 4 whose black level has been adjusted in this way is digitally converted by the A / D converter 6 and output as digital image information whose black level has been adjusted. is there.

On the other hand, an error may occur in the digital image information from the A / D converter 6 due to a sample / hold error in all pixels and dark signal sample / holds 2 and 3 and an offset error in the differential amplifier 4. In order to eliminate this error, the variable resistor 5 is manually adjusted. That is, the black level is adjusted by manually adjusting the variable resistor 5.

As a level adjusting method of the A / D converter, for example, in Japanese Patent Laid-Open No. 1-298871, a new reference high level is generated by an overflow signal generated when the input signal level becomes higher than the reference high level voltage. A voltage is created, a new reference low level voltage is created based on this new reference high level voltage, and these new reference high level voltage and reference low level voltage are A / D.
What feeds the converter is shown.

[0008]

However, in the conventional example shown in FIG. 5, the variable resistor 5 is manually operated.
The black level is adjusted by changing the offset value of the differential amplifier 4 by adjusting the resistance value of 1., which is difficult and troublesome.
There is a problem in that the cost at the time of adjustment is increased, which in turn increases the cost of the device.

The present invention has been made in view of the above points, and an object of the present invention is to obtain a black level adjusting circuit capable of automatically and easily and accurately adjusting a black level.

[0010]

A black level adjusting circuit according to the present invention receives digital information from an A / D converter for analog / digital converting analog image information,
The dark signal determining means for comparing the input digital information with the dark signal comparison value and outputting the dark signal level determining signal, and the dark signal level determining signal from the dark signal determining means are input. , And a dark signal adjusting means for outputting a level adjustment signal for adjusting the level of the dark signal in the A / D converter.

[0011]

In the present invention, the dark signal determining means is A
The digital information from the A / D converter is compared with the dark signal comparison value, and the dark signal level determination signal is output to the dark signal adjusting means so that the dark signal adjusting means outputs the dark signal in the A / D converter. Adjust the level for.

[0012]

EXAMPLES Example 1. A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing an image reading apparatus including a black level adjusting circuit. In FIG. 1, 11 is an image sensor including, for example, a CCD image sensor or the like, and an image signal of an original document illuminated by a reading light source is converted into an electric signal. And output as analog image information. Reference numeral 12 is an A / D converter to which analog image information from this image sensor is input and which converts the input analog image information into analog / digital and outputs as digital image information, which is a reference high-level voltage terminal R (+). DC power supply 1 is a constant voltage that becomes the white reference voltage
4 and has a reference low level voltage terminal R (-), and outputs 8-bit digital image information in the first embodiment.

An input terminal 13a is connected to an output terminal O of this A / D converter 13, and an output terminal 13b is connected to the A / D converter.
A black level adjusting circuit connected to the reference low level voltage terminal R (-) of the D converter 12 compares the digital information from the A / D converter 12 with a dark signal comparison value to obtain a dark signal level. A dark signal determination means 21 for outputting a determination signal, and a dark signal level determination signal from the dark signal determination means 21 are input to adjust the level of the dark signal in the A / D converter 12. And a dark signal adjusting means for outputting a signal to the A / D converter 12.

FIG. 2 is a block diagram of the black level adjusting circuit 13. In FIG. 2, 210a indicates a signal input terminal P connected to the input terminal 13a and a black level which is a comparison value for dark signal. It has a comparison value input end Q _{m to} which the minimum value Q _m is input and an output end α to output the comparison result, and the digital information input to the signal input end P is the minimum input to the comparison value input end Q _m. When the value is smaller than the value Q _m , it is a minimum value side comparing means for outputting a pulse that becomes “1” at the output terminal α. In the first embodiment, an 8-bit comparator is used, and the minimum value is Q _{m is} also a digital signal composed of 8 bits.

[0015] 210b outputs a comparison result with the comparison value input Q _M to the maximum value Q _M of the black level is a signal input terminal P and the dark signal for comparison value which is connected to the input terminal 13a is input output And a maximum value for outputting a pulse of "1" to the output terminal β when the digital information input to the signal input terminal P is larger than the maximum value Q _M input to the comparison value input terminal Q _M. In the side comparing means of the first embodiment, an 8-bit comparator is used, and the maximum value Q _M is also a digital signal consisting of 8 bits. Reference numeral 211 denotes these minimum value side and maximum value side comparing means 21.
The first logic means is composed of an OR gate to which the outputs from 0a and 210b are inputted, and when either one of the outputs from the minimum value side and maximum value side comparison means 210a and 210b is "1", "" 1 "is output.

Reference numeral 212 is a second logic means composed of an AND gate to which the output from the first logic means and the black correction timing signal BR are inputted, and the black correction timing signal BR.
Is a signal corresponding to the output from the first logic means 211, that is, a dark signal level determination signal when the black correction timing signal BR is "0". Outputs "0" regardless of the output from the first logic means 211. And
These minimum value side and maximum value side comparing means 210a and 21
0b and the first and second logic means 211 and 212 constitute the dark-time signal determination means 21.

Reference numeral 221 denotes a count enable terminal EN to which the output from the second logic means 212 is input, a count direction control terminal U / D to which an output from the maximum value side comparison means 210b is input, and a clock signal. Counter means having a clock input terminal CK to which CK is input and a count output terminal OUT for outputting a count output. In the first embodiment, the minimum value side comparing means 210a outputs "1". It is an 8-bit up / down counter that functions as a down counter when "" is output, and as an up counter when "1" is output from the maximum value comparing means 210b.

The output from the counter means is input to 222, which converts the output into an analog signal and gives it as a level adjustment signal to the reference low level voltage terminal R (-) of the A / D converter 12 which is a digital / analog. It is a converter. The counter means 221 and the digital / analog converter 222 constitute the dark time signal adjusting means 22.

Next, the operation of the circuit thus constructed will be described mainly based on the timing chart shown in FIG. First, the image information written or displayed on the document illuminated by the reading light source by the image sensor 1 is converted into an electric signal. The analog image information converted into an electric signal by the image sensor 1 is shown in FIG.
As V _A. This analog image information V _A is A
The / D converter 12 quantizes, that is, performs analog / digital conversion, and outputs digital information V _IN shown in FIG. 3B. This digital information V _IN is used as the dark signal determining means 2
It is input to 1 and compared with the dark signal comparison value. The dark signal comparison value has a minimum value Q _m and a maximum value Q _M set so that the reference low-level voltage value of the A / D converter 12 is optimal.

The digital information V _IN is compared with the minimum value Q _m and the maximum value Q _M by the minimum value side and maximum value side comparing means 210a and 210b, respectively. In the reading cycle T ₁ in FIG. 3, when the digital information V _IN becomes the minimum value Q _m or less as shown in FIG.
, The minimum value side comparison means 2
A pulse that becomes "1" is output to the output terminal α of 10a as shown in FIG. At this time, since the digital information V _IN is less than or equal to the maximum value Q _M , no pulse is output from the maximum value comparison means 210b as shown in (e) of FIG.
The output is "0".

At timing I of the reading cycle T ₁ , when the minimum value side comparing means 210a outputs a pulse of "1", the first logic means 211 outputs "1". Now, in the black level adjustment period, and the black correction timing signal BR is "1" as shown in FIG. 3A, the second logic means 212 also outputs a pulse of "1". It The counter means 221 functions as a down counter because the pulse "1" is not output from the maximum value side comparison means 210b, and the second logic means 212.
Is activated by the pulse from 1 to “1”, and the count output is counted down based on the input clock signal CK.

The D / A converter 222 receiving the count output from the counter means 221 converts this count output into an analog signal, and the reference low level voltage terminal R (-) of the A / D converter 12 receives the reference low level voltage. Figure 3 shows the level voltage value V _REF
Adjust by lowering as shown in (c). Also, at the timing II of the reading cycle T _1, the pulse "1" is output from the minimum value side comparing means 210a as in the timing I described above, and thus the same operation is performed and the reference of the A / D converter 12 is obtained. The low level voltage terminal R (-) is adjusted by lowering the reference low level voltage value V _REF as shown in FIG. 3 (c).

Next, at the timing III of the reading cycle T ₂ , although the pulse "1" was output from the minimum value side comparing means 210a at the timing I of the reading cycle T ₁ , the reference low level voltage terminal R Since the reference low level voltage value V _REF in (-) is adjusted, the minimum value side comparison means 210a does not output a pulse of "1", and the reference low level voltage value V _REF is not adjusted. Further, at the timing IV of the reading cycle T _2, a pulse "1" is output from the minimum value side comparing means 210a as in the timing II described above, and therefore the same operation as described in the timing I above is performed. The reference low level voltage value V is applied to the reference low level voltage terminal R (-) of the / D converter 12.
Adjust _REF so that it is lowered as shown in FIG.

Then, after the reading cycle T ₃ ,
Since the reference low-level voltage value V _REF is adjusted to an appropriate value, the digital information V _IN will no longer be less than or equal to the minimum value Q _m, so the minimum value side comparison means 210a outputs a pulse of “1”. Therefore, the counter means 221 does not operate and the reference low level voltage value V _REF is not adjusted.

On the other hand, in the above description of the operation, the digital information V _IN
Has been described as being equal to or smaller than the minimum value Q _m , but when the digital information V _IN is equal to or larger than the maximum value Q _M , the maximum value comparing means 210b outputs a pulse of "1". At this time, since the digital information V _IN is the minimum value Q _m or more,
No pulse is output from the minimum value side comparison means 210a,
The output is "0". Maximum value side comparing means 210b
When a pulse of "1" is output from the first logic unit 211, "1" is output. Now, since it is a black level adjustment engine and the black correction timing signal BR is "1", the second logic means 212 also outputs a pulse of "1". The counter means 221 functions as an up counter because the maximum value side comparing means 210b outputs a pulse of "1", and is activated by the pulse of "1" from the second logic means 212, and the input clock signal CK. Based on this, the count output that has been counted up is output.

The D / A converter 222 receiving the count output from the counter means 221 converts this count output into an analog signal, and the reference low level voltage terminal R (-) of the A / D converter 12 receives the reference low level voltage. Adjustment is performed by increasing the level voltage value V _REF . As a result, the reference low level voltage value V _REF is adjusted to an appropriate value so that the digital information V _IN does not exceed the maximum value Q _M. As described above, in the first embodiment, A
The digital image information V _IN from the A / D converter 12 that is out of the range of the minimum value Q _m and the maximum value Q _M set so that the reference low-level voltage value of the / D converter 12 is optimum is The A / D converter 12 is used as the optimum reference low level voltage value V _REF.
The black level is automatically adjusted by being fed back to.

Example 2. FIG. 4 shows a second embodiment of the present invention. In the figure, 210a and 210b are the minimum value side and maximum value side comparing means similar to those in the first embodiment.
Reference numeral 13a is a minimum value side analog switch which receives the output from the minimum value side comparison means 210a and is made conductive when this output is "1", and one electrode is grounded.
Reference numeral 213b is a maximum value side analog switch which receives the output from the maximum value side comparing means 210b and is made conductive when this output is "1", and one electrode is connected to the power supply terminal. Further, the minimum value side and maximum value side comparing means 210a and 210b and the minimum value side and maximum value analog switches 213a and 213b constitute a dark time signal determining means.

Reference numeral 223 denotes a resistor whose one end is connected to the other electrode of the minimum value side and maximum value analog switches 213a and 213b, and 224 is a capacitor which is connected between the other end of this resistor and the ground. The change is the resistance 22
It is adjusted by 3. A buffer 225 is composed of an operational amplifier in which a capacitor is connected to the non-inverting input terminal and an inverting input terminal is connected to the output terminal. The resistor 223, the capacitor 224, and the buffer 225 constitute the dark signal adjusting means 22.

Next, the operation of the circuit thus constructed will be described. First, the image information written or displayed on the document illuminated by the reading light source by the image sensor 1 is converted into an electric signal. The analog image information V _A converted into an electric signal by the image sensor 1 is A / D.
The converter 12 quantizes, that is, performs analog / digital conversion, and outputs digital information V _IN . This digital information V _IN is compared with the minimum value Q _m and the maximum value Q _M by the minimum value side and maximum value side comparing means 210a and 210b, respectively.

When the digital information V _IN may fall below the minimum value Q _m , a pulse of "1" is output to the output terminal α of the minimum value side comparing means 210a. At this time, since the digital information V _IN is below the maximum value Q _M , the maximum value comparing means 2
No pulse is output from 10b, which is an output of "0". When the minimum value side comparing means 210a outputs a pulse of "1", the minimum value side analog switch 213a in the pulse period of "1" becomes conductive,
The electric charge accumulated in the capacitor 224 is discharged through the resistor 223 and the analog switch 213a, and the potential of the capacitor 224 drops. When the potential of the capacitor 224 is lowered, the output of the buffer 225 is lowered and the A / D
The reference low level voltage terminal R (-) of the converter 12 is adjusted by lowering the reference low level voltage value V _REF .

Then, each time the minimum value side comparing means 210a outputs a pulse of "1", the above operation is repeated and the reference low level voltage value V _REF is adjusted until it becomes an appropriate value. When the reference low level voltage value V _REF becomes an appropriate value, the digital information V _IN is no longer the minimum value Q _m.
Since it does not become the following, the minimum value side comparison means 210a
Does not output a pulse of "1", the analog switch 213a on the minimum value side is not turned on, and the capacitor 22
The potential of 4 no longer drops, and the reference low level voltage value V
_REF is not adjusted.

On the other hand, the digital information V _IN has the maximum value Q _M.
In the case of the above, the maximum value comparing means 210b outputs a pulse of "1". At this time, since the digital information V _IN is equal to or greater than the minimum value Q _m , no pulse is output from the minimum value side comparison means 210a and “0” is output. When the maximum value side comparing means 210b outputs a pulse of "1", the maximum value side analog switch 213b in the pulse period of "1" becomes conductive, and the analog switch 213b and the resistor 2 are connected from the power supply terminal.
The electric charge is accumulated, that is, charged in the capacitor 224 via 23, and the potential of the capacitor 224 rises. The output of the buffer 225 rises in response to the rise in the potential of the capacitor 224, and the reference low level voltage terminal R (−) of the A / D converter 12 is adjusted to raise the reference low level voltage value V _REF .

Then, each time the maximum value side comparing means 210b outputs a pulse of "1", the above operation is repeated, and the reference low level voltage value V _REF is adjusted until it becomes an appropriate value. When the reference low level voltage value V _REF becomes an appropriate value, the digital information V _IN is no longer the maximum value Q _M.
Since it does not become the following, the maximum value side comparing means 210b
Does not output a pulse of "1", the maximum value side analog switch 213b is not made conductive, and the capacitor 22
The potential of 4 no longer rises, and the reference low level voltage value V
_REF is not adjusted. As described above, even in the second embodiment, the range of the minimum value Q _m and the maximum value Q _M set so that the reference low-level voltage value of the A / D converter 12 is optimum. The digital image information V _IN from the A / D converter 12 which is outside is the optimum reference low level voltage value V
_It is fed back to the A / D converter 12 as _REF , and the black level is automatically adjusted.

In the first and second embodiments described above, the case where the present invention is applied to the analog image signal from the image sensor 11 has been described, but the present invention is not limited to this, and the black level adjustment is performed. The present invention can be applied as long as the above is required, and for example, can also be applied to black level adjustment of Cds, Si photodiode, and the like.

[0035]

As described above, according to the present invention, the digital information from the A / D converter for analog / digital converting the analog image information is input, and the input digital information is compared for dark signal. A dark signal determination means for outputting a dark signal level determination signal in comparison with a value, and a dark signal level determination signal from this dark signal determination means are input, and A
Since the dark signal adjusting means for outputting the level adjusting signal for adjusting the level of the dark signal in the / D converter is provided, the optimum black level can be automatically and easily adjusted. This has the effect of preventing malfunctions in black level adjustment.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an image reading apparatus including a black level adjusting circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a black level adjusting circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing an operation in the first embodiment of the present invention.

FIG. 4 is a block diagram showing a black level adjusting circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing an image reading apparatus including a conventional black level adjusting circuit.

[Explanation of symbols]

 12 A / D converter 13 Black level adjusting circuit 21 Dark signal determining means 22 Dark signal adjusting means

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[Procedure amendment]

[Submission date] June 11, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

Reference numeral 4 designates all of these pixels and dark signal samples /
A differential amplifier that receives the sample / hold potentials from the holds 2 and 3 and amplifies the potential difference between the sample / hold potentials is for correcting the black level. 5 is a variable resistor for adjusting the offset of this differential amplifier,
6 receives the output from the differential amplifier 4 and outputs analog /
An A / D converter for digital conversion, in which a white reference voltage is input as a reference high level voltage and a ground voltage is input as a reference low level voltage. The circuit composed of all the pixels and the dark signal sample / hold circuits 2 and 3 and the differential amplifier 4 is described in "Toshiba integrated circuit technical data CCD image sensor (linear sensor)" (published by Toshiba Corporation. It is shown as a dark- time output compensation circuit in FIGS. 6-18 on page 54 of the publication year: 1989).

Claims (1)

[Claims] 1. Digital information from an A / D converter for analog / digital converting analog image information is input,
A dark signal determination means for comparing the input digital information with a dark signal comparison value to output a dark signal level determination signal, and a dark signal level determination signal from the dark signal determination means is input. A black level adjusting circuit having a dark signal adjusting means for outputting a level adjusting signal for adjusting the level of the dark signal in the A / D converter.