JPH0591459A - Electronic camera - Google Patents

Abstract

PURPOSE:To drastically reduce the block distortions and also to drastically improve the picture quality in a simple circuit configuration. CONSTITUTION:A LOT(lay orthogonal transformation) part carries out a LOT operation to reduce the block distortions when the image data are compressed. An image compressing/expanding circuit 12 contains the LOT part, a DCT (discrete cosine transformation) part, and a work memory. Furthermore the circuit 12 includes a LOT arithmetic unit to perform a LOT operation of the output of a frame memory 5 and outputs this arithmetic result to a coding/ decoding circuit 7. The circuit 12 also applies an ILOT(inverse lay orthogonal transformation) operation to the data inputted from the circuit 7 and outputs this arithmetic result to the memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic camera, and more particularly to an electronic camera which improves image quality during encoding / decoding.

[0002]

2. Description of the Related Art In recent years, electronic still cameras for recording captured images on a floppy disk have been put into practical use. In addition, a digital electronic still camera that records an image on a memory card or the like using a semiconductor memory has also been developed. At present, however, only about 50 images can be recorded on one floppy disk, and even a memory card of 1 megabyte can record only about 10 to 20 images. Moreover, the memory card is extremely expensive. Therefore, improvement in image compression technology is essential for electronic still cameras, and DCT (Discrete Cos) is currently the mainstream compression method.
ine Transform: Discrete cosine transform).

As a conventional electronic camera of this type, for example, there is one shown in FIG. In FIG. 48, 1
Is an electronic camera, and the electronic camera 1 is an optical system 2 including a lens and a CCD for converting the condensed light into an electric signal.
3, the input image signal is a luminance signal Y and a color difference signal R-
A Y-C processing circuit 4 for separating Y and B-Y, a frame memory (FM) 5 for storing image data of one screen, and a DCT for executing an orthogonal transform calculation for compressing the image data.
A device 6, an encoding / decoding circuit 7 for performing encoding for storing image data in the memory card 8, decoding the data read from the memory card 8, and storing encoded image data. The image data stored in the memory card 8 and the frame memory (FM) 5 is recorded in NTS.
It is composed of a reproducing circuit 9 for converting into a C signal and reproducing.

In the above structure, first, during recording,
The image is collected by the optical system 2, converted into an electric signal by the CCD 3, and converted into a digital signal of the luminance signal Y and the color difference signals RY and BY by the Y / C processing circuit 4.
This digital signal is stored in the frame memory (FM) 5, converted into an NTSC signal by the reproducing circuit 9 and displayed. Further, in order to record many images on the memory card 8, the output of the frame memory (FM) 5 is set to the DCT device 6
After the discrete cosine transform by the encoding / decoding circuit 7
And is stored in the memory card 8. On the other hand, during reproduction, the data in the memory card 8 is encoded / decoded by the encoding / decoding circuit 7
It is further decoded, subjected to inverse discrete cosine transform by the DCT device 6, and stored in the frame memory 5. Then, the data in the frame memory 5 is converted into an NTSC signal by the reproducing circuit 9 and displayed as in the recording.

[0005]

However, in such a conventional electronic camera, since the DCT device is used for the image compression / decompression unit, the image compression is performed, as shown in the reproduction screen of FIG. 49. In addition, square block-shaped noise (block distortion) occurs in areas such as the background that have low density.
However, there is a problem that image quality is deteriorated. As shown in FIG. 50 in which the noise part of FIG. 49 is enlarged,
This noise is generated at the boundary of 8 × 8 pixels, which is the processing unit of the DCT device, and this block distortion is DC at the time of companding.
This is because the calculation error generated in the T / inverse DCT calculation causes discontinuity at the boundary between blocks. Therefore, the present invention is
An object of the present invention is to provide an electronic camera capable of significantly improving image quality with a simple circuit configuration.

[0006]

In order to achieve the above-mentioned object, an electronic camera according to the present invention electrically collects the light collected by the light collecting means and the light collecting means for collecting the light incident from the object. Photoelectric conversion means for converting into a signal, storage means for storing the image signal converted into an electric signal by the photoelectric conversion means in a predetermined form, and data between adjacent blocks of the image signal stored in the storage means On the basis of the inverse overlap orthogonal transformation image signal from the arithmetic means, which is capable of performing the overlap orthogonal transformation and superimposing the orthogonal transformation of the image signal stored in the storage means using the superposition basis function. And a signal generating means for generating a predetermined reproduction signal,
The calculating means calculates one block data at the time of LOT, calculates the data of a plurality of blocks at the time of ILOT, and the first calculating means calculates the data of one block at the time of ILOT, and calculates the data of a plurality of blocks at the time of LOT. And a second calculation means for performing the operation.

[0007]

The operation of the present invention is as follows. When the object is photographed, the light incident from the object is condensed by the condensing unit, converted into an electric signal by the photoelectric conversion unit, and the converted image signal is stored in the storage unit. Then, the image data stored in the storage means is subjected to a superposition orthogonal transformation or a reverse superposition orthogonal transformation operation using a primitive function for superposing data between adjacent blocks, and is recorded in the recording means. Also, during reproduction, the operation in the opposite direction is performed. Therefore, noise at the block boundary in image compression / decompression is reduced, and there is no block distortion, resulting in a significant improvement in image quality.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 19 are views showing an embodiment of an electronic camera according to the present invention, which is an example applied to a digital still camera. In the description of this embodiment, the same components as those in the conventional example shown in FIG. 48 are designated by the same reference numerals.

First, the structure will be described. FIG. 1 is a block diagram showing an electronic camera. In FIG. 1, reference numeral 11 denotes an electronic camera. The electronic camera 11 has an optical system (light condensing unit) 2 including a lens, a CCD (photoelectric conversion unit) 3 for converting the condensed light into an electric signal, and an input. The Y-C processing circuit 4 that separates the generated image signal into the luminance signal Y and the color difference signals RY and BY, the frame memory (FM) 5 that stores the image data for one screen, and the image data is compressed. LOT (Lapped Orthogonal Transf)
orm: overlapping orthogonal transformation) An image compression / expansion circuit 12 equipped with a LOT calculation device for executing the calculation, and encoding for storing the LOT-calculated image data in the memory card 8 and read from the memory card 8. Encoding / decoding circuit (encoding / decoding means) 7 for decoding data
A memory card (recording means) 8 for storing the encoded image data, and a reproducing circuit (signal generating means) 9 for converting the image data stored in the frame memory (FM) 5 into an NTSC signal for reproduction. It is composed by.

FIG. 2 is a diagram showing a screen structure of the electronic camera. In this figure, the luminance signal Y is 768 dots horizontally and 4 pixels vertically.
There are 80 lines, and the color difference signals RY and BY are each horizontal 1
It has 92 dots and 240 vertical lines. If one pixel is compressed to 1.5 bits, 24 sheets can be recorded on a 2MB memory card.

By the way, as described above, not only the DCT device but also the high quality coding to reduce the average number of bits per pixel lowers the image quality, and the higher compression ratio causes the deterioration of the image quality. When the current standard television signal is compressed to 1.5 Mbit / sec, the problems are the deterioration of the contour portion and the block unit (eg 8 ×) processed by the DCT device.
This is the block distortion that occurs in 8 pixels. When the inverse conversion is performed to reproduce the pixels, the DCT outputs in the block are all linearly summed. However, if even one of the 64 DCT outputs of the block including 8 × 8 pixels has information loss, The reproduced pixels in the entire block are deteriorated.

Therefore, in this embodiment, in order to reduce such block distortion, an image compression / expansion circuit 12 using the LOT operation together with the DCT device is provided as described in detail below. The image compression / decompression circuit 12 includes a DCT unit and an LO.
It consists of a T section and a working memory. The LOT calculation process will be described below with reference to FIGS. In FIG. 3, the image compression / decompression circuit 12 performs LOT operation processing at L.
It shows the OT operation device 100, and shows a block diagram of a one-dimensional LOT. In FIG. 3, 100 is LO
T operation devices, 101 and 102 are DCT devices, and DC
Various computing units shown in FIGS. 4 to 7 are connected to the T devices 101 and 102. Here, in FIG. 4, subtraction c = a + (-
b), FIG. 5 shows an operation showing addition c = a + b, FIG. 6 shows an operation for adjusting a predetermined gain (for example, 1/2), and FIG. 7 shows an operation for performing vector rotation. There is. The outputs of the DCT devices 101 and 102 are even outputs 0, 2, 4, 6 and odd (odd).
d: odd number) Outputs 1, 3, 5, and 7 are added and subtracted,
Finally, only the odd components are vector-rotated by the butterfly computing unit shown in FIG. 7 to become LOT data. In the one-dimensional LOT configuration shown in FIG. 3, if 16 pixels (X _{0 to} X ₇ , X ₀ ′ to X ₇ ′) are input to the DCT devices 101 and 102 that form the image compression / expansion circuit 12 together with the LOT calculation device, the LOT calculation is performed. Thus, the output of 8 data (Y _{0 to} Y ₇ ) is obtained. That is, in the first stage of input, one-dimensional DCT calculation is performed,
After obtaining the data and performing various calculations on the 16 data, vector rotation is performed to finally obtain 8 data. Since this LOT operation is one-dimensional, 8 times for 16 × 16 input pixels.
The output is × 16, and the vertical and horizontal directions are changed again to perform the same LOT operation to obtain 8 × 8 data.

Although two DCT devices are shown in FIG. 3, there is one DCT device in terms of hardware.
Data X, data at different timings in one DCT device
_{X '(X 0 ~X 7,} X 0' ~X 7 ') is supplied.

FIG. 8 is a diagram showing input / output pixels of the LOT calculation device 100. The LOT operation device is an extension of the conventional DCT device and performs two-dimensional block processing similarly to the DCT device. In the DCT device, 8 × 8 data was obtained when the input was 8 × 8 pixels, whereas in the LOT arithmetic device, in order to obtain 8 × 8 output, as shown by the broken line portion in FIG. 16x16 pixels, including 8x8 are required. The broken line part in FIG. 8 is the LOT input pixel, and the solid line part is the output data.

The LOT calculation device of the image compression / expansion circuit 12 will be described in detail below. FIG. 9 is a block diagram showing a calculation unit of the LOT calculation device. In FIG. 9, LOT
The arithmetic unit 21 can perform an operation (Hadamard transform) Y ₁ stage 22 using only one block of data (closed) and a Y ₁ stage that can perform an operation (Hadamard transform) only when two blocks of data are available. ₂ stage 23,
It is inserted between the odds of the Y ₁ stage 22 and the Y ₂ stage 23, and temporarily the data of the odd component (reverse LOT) from the Y ₁ stage until the calculation of the next block line is completed.
1 block line memory 24 for storing (odd component data from Y ₂ stage), Z stage 25 for performing vector rotation, switches 26 to 33 for switching data flow, and switch switching circuit 40. Has been done.

The switch switching circuit 40 includes the switch 2
6 to 33 are switched to switch the data flow at the time of LOT and ILOT. The switches 26 to 33 are for switching the flow of data by switching the bus, for example, and the configuration thereof is not particularly limited as long as the connection relationship of the buses can be switched physically or electrically. For example, a transistor switch or the like can be used.

Hereinafter, the Y ₁ stage 22 and the Y ₂ stage 23
The Z stage 25 will be specifically described with reference to FIGS. 10 to 19. The Z stage 25 is for rotating the odd-numbered component of the input data as shown in FIG. 10 for the LOT calculation and for the inverse LOT calculation as shown in FIG.
The butterfly operation is shown in FIG. K in FIG.
Is a coefficient for giving vector rotation, for example, 0.13
It is set to 0.16. This Z stage 25 is similar to the conventional Z stage, but the number of Z stages is only one. In addition, the Y ₁ stage 22 and the Y ₂ stage 23
Is a division of the Y stage shown in FIG. 10 into two stages as shown in FIGS. 16 and 17, and the operation is performed by closing it in one block (using only the data of one block) at the time of LOT. (Hadamard transformation) can be performed by the Y ₁ stage 22 (first arithmetic processing unit), LOT
Sometimes Y ₁ stage 2 for different blocks of data
The Y ₂ stage 23 (second arithmetic processing unit) is an arithmetic unit that can perform an arithmetic operation (Hadamard transform) only after the arithmetic results of 2 are complete. The 1-block line memory 24 is a memory for temporarily storing the calculation result of the Y ₁ stage in a certain block until the calculation of the Y ₁ stage in the next block is completed. 12 to 15
Shows various butterfly operations in each stage, and shows the same operation contents as the butterfly operation in FIGS. 4 to 7.

Next, the operation of this embodiment will be described. Operation of Digital Still Camera 11 First, at the time of recording, as shown in FIG. 1, an image is condensed by the optical system 2 and converted into an electric signal by the CCD 3 so that Y /
The C processing circuit 4 causes the luminance signal Y and the color difference signals RY and B-
It is converted into a Y digital signal. This digital signal is stored in the frame memory (FM) 5, converted into an NTSC signal by the reproducing circuit 9 and displayed. Further, in order to record a large number of images on the memory card 8, the output of the frame memory (FM) 5 is overlapped and orthogonally transformed by an image compression / expansion circuit 12 including the DCT devices 1001 and 1002 and the LOT operation device 1000 to be blocked. After the distortion is reduced, it is encoded by the encoding / decoding circuit 7 and stored in the memory card 8.

On the other hand, at the time of reproduction, the data in the memory card 8 is converted into a signal by the encoding / decoding circuit 7, inversely orthogonally transformed by the image compression / expansion circuit 12, and stored in the frame memory 5. Then, the data in the frame memory 5 is converted into an NTSC signal by the reproducing circuit 9 and displayed as in the recording.

The operation of the LOT arithmetic unit is as follows. Operation during LOT Calculation (see FIG . 18) FIG. 18 is a diagram showing a data flow during LOT. First, as shown in FIG. 10, DCT calculation outputs F _{0 to} F ₇ are
Hadamar conversion is performed by the Y ₁ stage 22, and G _{0 to} G
₇ Of these, even sides G ₀ , G ₂ , G ₄ , and G ₆ (hereinafter referred to as Ge) are directly input to the Y ₂ stage 23. Further, since the odd side G ₁ , G ₃ , G ₅ , and G ₇ (hereinafter, referred to as Go) must be added and subtracted with the even when the next block is calculated, the calculation points in the Y ₂ stage 23 are aligned. Therefore, it is temporarily stored in the one-block line memory 24. Subsequently, at the next timing, the block data F ₀ ′ to F ₇ ′ based on the DCT calculation output
Is converted to Hadamard by the Y ₁ stage 22,
G ₀ 'to G ₇ '. Like Ge and Go, Ge ′ is directly input to the Y ₂ stage 23, and Go ′ is stored in the one block line memory 24. Ge 'to Y ₂ Stage 2
3 is input to the Y ₂ stage 23 at the same time as it is input to 3, and the Y ₂ stage 23 executes Hadamard conversion to Go and Ge ′.
That is, the operation between data of different blocks is LOT.
Occasionally, the Y ₂ stage 23 is used. Then, the outputs H _{0 to} H ₇ of the Y ₂ stage 23 are input to the Z stage 25, and Y _{0 to} Y ₇ , which are the results of the LOT calculation, are obtained at the Z stage 25 (see FIG. 10). By the way, it is considered that the execution time is delayed by the amount of the memory access added when the output of the Y ₁ stage 22 is input to the Y ₂ stage 23.
Actually, the LOT calculation is a repetition of the above calculation, so that the total time is almost unchanged from the conventional one.

Operation at the time of inverse LOT calculation (see FIG . 19) FIG. 19 is a diagram showing a data flow at the time of inverse LOT. Input data Y ₀ '~Y _7' is converted to J ₀ '~J _7' by Z stage 25, Y ₂ stage 23 further
Convert J ₀ ′ to J ₇ ′ to K ₀ ′ to K ₇ ′. Z stage 2
Only the data on the odd side is rotated at 5, and the data on the even side is output as it is. In the Z stage 25 at the time of ILOT, odd-numbered data input and output are changed from 1 → 7,3
By twisting like → 5,5 → 3,7 → 1, it is possible to process the data at the time of ILOT with the same hardware as the hardware at the time of LOT. Then, the Y ₂ stage 23 performs an operation (Hadamard transformation) on the odd-side data rotated by the Z stage 25 and the even-side data supplied as it is. Here, in the Z stage, no calculation is performed on the even side data, but for convenience sake, the even side data is also input to the Z stage 25 in FIG. Then, like the output of the Y ₁ stage 22 at the time of LOT, Ke ′ is directly input to the Y ₁ stage 22, and Ko ′ is the one block line memory 24.
Store in. Similarly, the following input data is input to the Z stage 2
5, converted to K _{0 to} K ₇ by the Y ₂ stage 23, and Ke
Is directly input to the Y ₁ stage 22, and Ko is stored in the 1-block line memory 24. Memory 24 with Ke
Input the Ko 'data stored in the Y ₁ stage 22. Then, the IOT outputs F _{0 to} F ₇ are obtained by executing the calculation of the Y ₁ stage 22. That is, I
At the time of LOT, the Y ₁ stage 22 takes charge of calculation between different blocks.

As described above, in the present embodiment, the image data compression and the like are executed by using the image compression / decompression circuit 12 including the LOT arithmetic unit, so that the data between the adjacent blocks is, for example, 16 × 6. We will get 8x8 data from the pixels and they will be properly overlaid,
It is possible to construct a high-quality electronic camera 11 with little block distortion. In addition, the LOT operation device of this embodiment is
With dividing the Y stage LOT calculation to Y ₁ stage 22 and Y ₂ stage 23, 1 block line memory 24 for storing data until the operation of the next block line between Y ₁ stage 22 and Y ₂ stage 23 is completed Are provided, so that the Y ₁ stage 22 and the Y ₂ stage 2
The process in 3 is completed in units of 8 inputs. Also, LOT
Since the calculation between blocks is performed by different stages at the time and at the time of ILOT, the Z stage 25 can be one. Therefore, the circuit scale of the Z stage can be halved as compared with the conventional one. Further, since the one-block line memory 24 needs to store only the data on the even side, the memory capacity can be reduced.

In this embodiment, the image signal converted into an electric signal is separated by the Y / C processing circuit 4 into the luminance symbol Y and the color difference symbols RY and BY, and the frame memory (FM) 5 is used.
The image signal converted into an electric signal may be stored in a predetermined form, for example, may be stored in the form of an RGB signal, or converted into an electric signal. The image signal may be stored as it is.

(Second Embodiment) The image data processing apparatus shown in FIGS. 9 to 19 is one-dimensional (horizontal) when performing LOT calculation.
After performing LOT calculation (LOT is basically one-dimensional), one-dimensional (vertical) LOT calculation is performed again on the obtained data to obtain two-dimensional image data. For this reason, the one-dimensional processing must be repeated twice in the LOT calculation section before the quantization output section quantizes the data output from the two-dimensional DCT calculation section. Therefore, the operation of the two-dimensional DCT operation unit must be stopped until the one-dimensional LOT operation finishes the processing of the second dimension, which causes a problem that the operation time cannot be shortened and the timing is difficult. .. Therefore, the second embodiment provides an image compression / expansion circuit that can significantly reduce the image processing time.

The present embodiment will be described below with reference to the drawings. Description of Principle First, the basic idea of this embodiment will be described. In the present embodiment, the LOT arithmetic unit of the image compression / expansion circuit is closed in one block (using the data of one block), and the first arithmetic processing unit X capable of arithmetic operation (Hadamard transform) and a plurality of blocks. In the second arithmetic processing unit Y that performs an arithmetic operation using the data of 3 and the third arithmetic processing unit Z that performs a vector rotation.
It is intended to realize high-speed data processing by dividing and performing a two-dimensional operation in each operation processing unit. Therefore, as shown in FIG.
The operation unit, the Y operation unit, and the Z operation unit are divided into three parts, and two-dimensional operations are performed in each part. Further, FIG. 21 is a diagram showing the calculation contents (for one dimension) of the rotation processing in the Z calculation unit, and FIGS. 22 and 23 show the details (for one dimension) of the X calculation unit and the Y calculation unit in FIG. It is a block diagram.

Next, the specific configuration and operation of the image compression / decompression circuit according to this embodiment will be described with reference to FIGS. FIG. 24 is a block diagram showing the LOT calculation device of the image data processing device. In FIG. 24, the LOT operation device 121 includes a two-dimensional X operation unit 122 that performs two-dimensional Hadamard transform, a two-dimensional Y operation unit 123 that performs two-dimensional Hadamard transform, and the two-dimensional X operation unit 122 and two-dimensional. Inserted between the Y calculation unit 123 and the two-dimensional X calculation unit 12
One block line memories A124, B125, C1 for controlling data exchange between the two and the two-dimensional Y calculation unit 123 and delaying the data by one block line.
26 and a two-dimensional Z operation unit 1 for performing vector rotation
And 27. The two-dimensional X calculator 12
In No. 2, at the time of LOT, addition / subtraction of data of one image block is performed, so that the output of DCT can be directly processed. Further, in the reverse direction, since the operation is performed on the data of two block lines, the data of the block line memory is read and the data operation processing is performed.
The two-dimensional Y operation unit 123 performs an operation on the data of two block lines in the forward direction and outputs the data to the two-dimensional Z operation unit 127, and outputs the data from the two-dimensional Z operation unit 127 in the reverse direction. Is directly processed to write data in the block line memories A124, B125, C126. The two-dimensional Z calculation unit 127 determines that the two-dimensional Z
The data from the arithmetic unit 123 and the quantized data from the quantizer in the reverse direction are processed.

FIG. 22 is a block diagram of the two-dimensional X operation unit 122, and the two-dimensional Y operation unit 123 has the same circuit configuration. In FIG. 22, the two-dimensional X operation unit 122 includes data latches A131 and B13 that temporarily hold data.
2, C133, D134 and data latches A131, B
132, C133, D134 adder / subtractors 135, 136 for adding / subtracting the data latched, and adder / subtractor 135,
An adder 137 for adding the outputs of 136 and an adder / subtractor 13
And a subtracter 138 for subtracting the outputs of
It comprises a data selector 139 for selecting and outputting the data from 37 and the data from the subtractor 138. The data selector 139 has a function of selecting the input data and outputting the same,
Equipped with a multiplication function.

There are 64 DCT outputs for a block of 8 × 8 pixels. Therefore, 16 sets of the configuration of FIG. 22 are arranged in the X calculation unit 122, and
Corresponding four of CT outputs are input. Similarly,
Also in the Y calculation unit 123, 16 sets of the configuration of FIG. 22 are arranged. Note that in the X, Y arithmetic units 122 and 123, a predetermined number of circuits in FIG. 22 may be arranged and input data may be time-division processed.

FIG. 27 is a block diagram of the two-dimensional Z calculation unit 127. The two-dimensional Z operation unit 127 is for rotating the odd component of the input data, and the butterfly operation thereof is shown in FIG. In FIG. 21, θ is a coefficient for giving vector rotation and is set to 0.13, 0.16, for example. This two-dimensional Z calculation unit 127 is specifically
As shown in FIG. 24, two one-dimensional Z calculation units 141, 14 are provided.
2 and two block line memories A143, B144
And Z operation units 141 and 14 respectively.
2 is responsible for vertical and horizontal Z operations. The two block line memories A143 and B144 are provided to hold data necessary for performing the second-dimensional calculation. The block line memory A 143 and the block line memory B 144 switch and store the outputs of the Z calculation unit 141 for each block. Z in the block line memory A143 or the block line memory B144
While storing the output data of the calculation unit 141, the Z calculation unit 142 performs the second-dimensional Z calculation on the data stored in the buffer 144B or 143A. Here, in the Z operation, the odd component 1 of the input data in the reverse direction
It is performed by switching 3, 5 and 7 as 1⇔7 and 3⇔5.

Next, the operation of this embodiment will be described. Operation of LOT arithmetic unit as a whole The operation of each block in the forward and backward directions is shown in FIGS. 28 and 29. For example, in the case of the forward direction, as shown in FIG. 28, the two-dimensional X operation unit 122 receives the input from the DCT device from the block line memories A124, B125, C12.
Write to 6 in order. The two-dimensional Y calculation unit 123 reads data from two block line memories, performs two-dimensional processing, and outputs the data to the two-dimensional Z calculation unit 127. It should be noted that when using a memory capable of reading and writing at once, the above operation is not always necessary.

Operation of two-dimensional X operation unit and two-dimensional Y operation unit
(See FIG. 25) First, the forward direction will be described. Data latch A131 to a
(I, j) data is latched and data latch B1
32 to a (i, j + 1) and data latch C133 to a (i, j + 1).
(I + 1, j), a (i + 1, j) is stored in the data latch D134.
j + 1) are latched, and adder / subtractors 135, 1
Assuming that both 36 operate as an adder, the adders / subtractors 135 and 136 respectively provide a (i, j) + a (i, j +).
1), + a (i + 1, j) + a (i + 1, j + 1) are output, and a is output from the adder 137 and the subtractor 138, respectively.
(I, j) + a (i, j + 1) + a (i + 1, j) + a
(I + 1, j + 1) and a (i, j) + a (i, j + 1)
-A (i + 1, j) -a (i + 1, j + 1) is output. The output of the adder 137 is the b (i, j) component after conversion, and the data of the subtractor 138 is the b (i + 1, j) component. Next, when the adder / subtractors 135 and 136 are operated as subtractors, the outputs from the adder 137 and the subtractor 138 are b (i +, j + 1) and b (i + 1, j + 1). Note that the above i and j are even numbers.

More specifically, for example, the data a00, a01, a10, a11 (i = 0, j = 0) of a certain block is processed by the X calculation unit 1
22 is converted into a00 ′, a01 ′, a10 ′, a11 ′ according to the following equation. a00 '= (a00 + a01 + a10 + a11) / 2 a01' = (a00 + a01-a10-a11) / 2 a10 '= (a00-a01 + a10-a11) / 2 a11' = (a00-a01-a10 + a11) / 2 Further, the above operation is 1 All i and j in one block
For example, the four blocks A to D shown in FIG.
Converted to D '.

As shown in FIG. 28, the X calculator 122
Are stored in block line memories 124 to 126 in block line units. Then, when the X operation unit 122 operates for the next block line, Y
The arithmetic unit 123 reads the block H ′ obtained from the four blocks A ′ to D ′ from the block line memories 124 to 126. The block H'can be represented as follows. a11 ', a13', a15 ', a17', b10 ', b12', b14 ', b16' a31 ', a33', a35 ', a37', b30 ', b32', b34 ', b36' a51 ', a55 ', A55', a57 ', b50', b52 ', b54', b56 'a71', a77 ', a75', a77 ', b70', b72 ', b74', b76 'H' = c11 ', c13' , c15 ', c17', d10 ', d12', d14 ', d16' c31 ', c33', c35 ', c37', d30 ', d32', d34 ', d36' c51 ', c53', c55 ', c57 ', d50', d52 ', d54', d56 'c71', c73 ', c75', c77 ', d70', d72 ', d74', d76 '

The Y calculator 123 reads the block H '.
On the other hand, a two-dimensional Hadamard transform is executed. The specific conversion operation is the same as the operation of the X calculation unit 122 described above. The output of the Y stage is supplied to the Z calculation unit 127.
Thus, for four adjacent blocks, X
The processing by the calculation unit 122, the Y calculation unit 123, and the Z calculation unit 127 is sequentially executed.

On the other hand, in the reverse direction, the above a (i, j) is changed to (i
-1, j + 1), and the above a (i, j + 1) is a (i-
1, j + 8) and a (i + 1, j) is a (i, j +)
In 1), the above a (i + 1, j + 1) is replaced with a (i, j + 8)
Change to each. Here, the adder 137 and the subtractor 13
Since the output of 8 is twice as wide as the input of the data latches A131 to D134, the data selector 1
In 39, it is necessary to carry out the calculation of Genie adjustment by ½. That is, the two-dimensional X calculator 22 and the two-dimensional X
Since the two-dimensional calculation is performed in each calculation unit of the calculation unit 123, the calculation result is output from each calculation unit in the form of an integer. Further, the two-dimensional X calculation unit 122 and the two-dimensional Y calculation unit 123 can be configured by the same circuit. Therefore, it suffices to debug only one of the arithmetic units, and the debugging can be performed very efficiently.

As described above, in the second embodiment, DC
A two-dimensional X that can be operated by closing the LOT operation device that constitutes an image compression / expansion circuit together with the T device in one block.
2 which can be calculated by the calculation unit 122 and a plurality of blocks
Dimension Y calculation unit 123 and two-dimensional Z for performing vector rotation
The calculation unit 127 is divided into three, and each calculation processing unit divides into two.
Since the dimensional calculation is performed, the data output from the two-dimensional DCT device can be directly subjected to the two-dimensional LOT operation and output to the quantizer, and the operation of the DCT device can be performed in the two-dimensional LOT operation. It is possible to prevent delay of data such as having to take a rest until the eye processing is completed, and to improve the arithmetic processing remarkably. Also, D
Since it is possible to operate the CT device, the LOT calculation device, and the quantization device at the same time, it is possible to realize a high-speed image compression device because the timing can be adjusted very easily. Needless to say, the above-mentioned effects occur in the opposite direction, that is, data expansion, and when applied to an image data processing device for compressing / expanding image data, the image processing time can be greatly shortened.

(Third Embodiment) In the LOT operation device, encoded data can be processed at high speed with a relatively small circuit as described above, but the ALU is used to perform LO processing.
Since the configuration is such that the T operation is performed, the number of accesses to the memory is increased, and accordingly, the control of the address, the bus, and the like becomes complicated, and as a result, the circuit scale is still large. Therefore, the electronic camera according to the third embodiment provides an image compression / expansion circuit that performs LOT processing with a smaller circuit scale by performing LOT calculation and inverse LOT calculation by serial calculation that sequentially moves data by a predetermined clock. ..

The present embodiment will be described below with reference to the drawings. 30 to 47 are diagrams showing a specific configuration and operation of the image compression / decompression circuit according to the present embodiment. First, the configuration will be described. FIG. 30 is a block diagram showing the data operation unit of the LOT operation device of the image compression / expansion circuit. In FIG. 30, 2
Reference numeral 31 is a Y stage for performing a predetermined addition / subtraction process, and 232 is a Z stage for performing vector rotation. The Z stage 232 shows the calculation at the time of LOT in FIG.
The operation at the time of LOT) is for rotating the odd component of the input data as shown in FIG. 31, and the butterfly operation is shown in FIG. 15 described above. K in FIG. 15 is a coefficient for giving vector rotation, for example, 0.13, 0.1
Set to 6.

32 to 44 are block diagrams showing the data conversion section and the quantization section of the image compression / decompression circuit according to this embodiment. In FIG. 32, reference numeral 241 is the LOT arithmetic unit 240.
The data conversion unit 242 is a quantization unit, and cos 0.13π and sin 0.13π and cos 0.16π and sin, which are the operation coefficients (numerical values circled in the figure) of the data conversion unit 241.
The ratio of 0.16π is approximated by the ratio of integers as shown in Formula 1.

[Equation 1]

The integer ratio does not necessarily have to be such a ratio, and a ratio having a larger number of digits may be used and replaced with a more accurate ratio. Further, in the calculation by the integer ratio, the gain is different from the calculation that should be originally performed, so the difference in the gain is absorbed by the quantization calculation. For example, the value z created by x ₁ and x ₂ is 7 ² +3 ² = 58, so sin, co
It is the value shown in Equation 2 which is (58) ^1/2 times larger than that calculated using s.

[Equation 2] It should be noted that this correction numerical value is created from the approximation shown in Expression 2 and does not necessarily have to be this value.

In the case of the present embodiment, since the output of such an operation is the input of the operation of the next stage, the gain matching operation is performed once at z ₁ , z ₂ and z ₃ in FIG. .. Note that the gain matching in this case means that the gains of the input data match each other, and does not mean that the gains of the output data match. The ratio of the gain between the inputs is expressed by Equations 3 and 4.

[Equation 3]

[Equation 4]

In the example shown in FIG. 32, z ₁ : z ₂ : z ₃ = 5: 38: 392 is set as an example satisfying the above expressions 3 and 4.
Note that this is just an example, and it is not always necessary to use such a numerical value.

The change amount of each output gain caused by expressing the gain as an integer ratio is used by the quantizer 242.
Absorb at. That is, the calculation coefficient of the data conversion unit 241 is replaced with an integer ratio, and the gain changed by this is corrected by the quantization unit 242.

FIG. 33 is a diagram showing an inverse data conversion unit and a quantization unit in the inverse conversion of the data compression device, and shows an example of performing the inverse conversion of FIG. In FIG. 33, 25
Reference numeral 1 is an inverse quantization unit of the LOT operation device 240, and 252 is an inverse data conversion unit. In the case of the inverse transform, as in the case of FIG. 32, the operation coefficient of the inverse data transform unit 252 is replaced with an integer ratio as shown by the numerical value circled in FIG. 25, and the change in gain caused thereby is inversely quantized. The part 251 is adjusted so as to be absorbed (compensated).

In this embodiment, the LOT and inverse LOT operations are performed by the serial operation described below. First, as a basic idea, the value expressed by the ratio of integers as shown in the equation 1 should be converted into two powers as shown in the equation 5 (that is, n of 2).
It is represented by the sum or difference of powers.

[Equation 5] The reason why the numerical value is expressed as a power of 2 as shown in Expression 5 is to realize the operation by the serial circuit. That is, in FIG. 34, reference numeral 271 is an FF that responds to a clock input signal and outputs the input signal delayed by one clock.
Assuming that one time delay unit composed of (flip-flop) is represented, the one time delay unit 27
Output coming out through 1 and 1 time delay unit 2
Comparing with the output that comes out directly without passing through 71, the former is one clock later than the latter. Here, the 1-time delay unit 271 is like a shift register arranged side by side. For example, assuming that data is sequentially input from the LSB side, it means that one clock is delayed.
Means doubled. Similarly, in the case of multiplying by 8 times, if three 1 time delay units 271 are arranged and delayed by 3 clocks as shown in FIG. 35, 2 ³ becomes 8 times. In this embodiment, a serial arithmetic circuit is realized by combining the above units and performing addition and subtraction.

FIG. 36 shows the serial operation configuration of the multiplication unit, and FIG. 36 shows an example in which the input data is multiplied by 38. First, 38 is decomposed into the form of Eq.

[Equation 6] In Equation 6, multiplying a certain value x by 32 means
This is to shift x to the left (MBS direction) five times, and in FIG. 36, it is realized by passing five one-stage time delay units 271. Further, since 2 × (2 + 1) shown in the equation 6 is actually 6, 4 + 2
May be expressed as However, since the full adder 272 of FIG. 36 has one time delay unit and doubles the input data, the expression format of 2 × (2 + 1) is adopted. FIG. 37 shows the circuit configuration as described above for the entire Z stage, and is a circuit configuration diagram for performing the data conversion unit 241 of FIG. 32 by serial operation. Also,
38 to 40 are diagrams showing each unit in FIG. 37, and FIG. 38 is a time delay unit 2 including an FF.
71, FIG. 39 shows a 1-time delay unit full adder (internal Carry Type) 272 that performs addition (a + b),
FIG. 40 shows a 1-time delay unit full substructor (internal Borrow type) 273 for performing subtraction (ab). Further, in FIG. 37, a 1-time delay unit not related to the calculation is added for the alignment of the decimal point. For example, the integer value 7 at x ₁ of the data conversion unit 241 of FIG. 32 is (4 + 2 + 1)
In FIG. 37, one 1-time delay unit 271 and two full adders 272 are combined. Similarly, all the numerical values shown in FIG. 32 can be realized by a serial circuit as shown in FIG.
T can be realized by serial calculation. In this case, each unit 271, 272, 273 can be realized by an extremely small circuit having one FF, so that the circuit scale of the entire LOT operation device can be reduced.

Further, at the time of reverse LOT, the same serial operation as at the time of LOT described above can be performed. FIG. 41 is a circuit configuration diagram in which the inverse data conversion unit 252 of FIG. 33 is performed by serial operation, and the same serial operation as in FIG. 37 is executed.

FIG. 42 shows the serial operation circuit of FIG.
6 is a timing chart when 9-bit (sign + Data 8) data shown in FIG. 3 is input. As shown in FIG. 42, 9
When inputting bit data, the next 9-bit data can be input after 24 (9 + 15) time units have elapsed. Therefore, one cycle of data input is 24 time units. Generally, for n-bit input, data can be input in n + 15 time unit cycle.

The reverse LOT will be described below.
The data itself may be considered to flow from right to left in the flow graph of LOT of FIG. 30 (see FIG. 29). Considering the Z stage 232 and the Y stage 231, the Z stage 232 and the Y stage 231 are symmetrical except for the gain of the Z stage 232. As in the case of LOT, the gain of the Z stage 232 can be adjusted by absorbing the gain of the Z stage 232 and that of the Y stage if it is absorbed in advance during inverse quantization.
The stage 231 may be combined as shown in FIG. However, the input that was x ₁ in FIG.
_7, a y ₅ in x _3, the y ₃ in x _5, the y ₁ is input to the x _7, so that'll twisted equally to the output. Also,
45 and 46 are diagrams showing the entire configuration in consideration of the reverse LOT time. FIG. 45 shows the data flow at the time of LOT, and FIG. 46 shows the data flow at the time of reverse LOT.

As described above, in this embodiment, the inverse L
In consideration of the time of OT, two Z stages are provided, but as shown in FIG. 47, one Z stage is provided.
If a memory is provided in that portion, the circuit scale can be reduced. In this case, since the operation of storing data in the memory once is added, it may be considered that the high speed operation is lost. However, when the LOT operation is continuously performed, it always passes through the previous Z stage. Since the data is held, there is almost no change in the execution time itself.

In this embodiment, the coefficient is set to, for example, 7: 3.
Although an example in which the ratio is an integer is shown, the invention is not limited to this,
Any integer ratio may be used as long as it is represented by an integer ratio.

Further, although the arithmetic coefficient is expressed by the sum (difference) of the power of 2 (n to the power of 2), the arithmetic operation is performed by the serial circuit as shown in FIG. 37, but serial data processing is performed. Of course, any combination of units may be used.

As described above, in the third embodiment, the LOT and inverse LOT operations in the image compression / expansion circuit are performed by serial operations.
When the LOT operation is performed using, the circuit scale is very large and the execution time is long, but the circuit scale is significantly reduced because it will be realized by the serial circuit composed of an extremely small combination of FFs and the like. Can
In addition, the processing can be performed at high speed. It is suitable to apply the high-speed LOT operation processing with such a small circuit scale to an encoded data processing device that performs image compression and audio compression.

In the present embodiment, the data conversion unit 214,
Since the calculation coefficient of the inverse data conversion unit 252 is replaced with an integer ratio and the change in the gain is absorbed by the quantization unit and the inverse quantization unit, the calculation by the coefficient including the error is performed by the quantization unit. The operation is performed only once, and the other operations can be performed by an integer ratio that does not include a rounding error, which has the effect of achieving high operation accuracy with a small bus width.

In each of the above embodiments, DCT and Hadamard transform are applied to the image compression / decompression circuit. However, the coding method is not limited to this, and any device can be used as long as it performs LOT calculation. Needless to say, it is also applicable. For example, it can be applied to a coded data processing device using Harr transform, gradient transform (slant transform), symmetric sine transform, or the like.

[0056]

According to the present invention, the image signal stored in the storage means is subjected to the superposition orthogonal transformation and the inverse using the basis function for superposing the data between the adjacent blocks of the image signal stored in the storage means. Arithmetic means capable of executing the superposition orthogonal transformation and signal generating means for producing a predetermined reproduction signal based on the image signal subjected to the inverse superposition orthogonal transformation from the arithmetic means are provided, and the arithmetic means is one block at the time of LOT. It has a first calculating means for calculating data and calculating data of a plurality of blocks at the time of ILOt, and a second calculating means for calculating data of one block at the time of ILOt and calculating data of a plurality of blocks at the time of LOT. Since the block distortion can be significantly reduced, a high-quality image can be obtained when the same information amount is used, and a low-quality image can be obtained when the same image quality is used. It is possible to realize a broadcast of an electronic camera.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic camera according to the present invention.

FIG. 2 is a screen configuration diagram of an electronic camera according to the present invention.

FIG. 3 is a configuration diagram of a LOT calculation device of an electronic camera according to the present invention.

FIG. 4 is a diagram showing a computing unit for butterfly computing of the LOT computing device of the electronic camera according to the present invention.

FIG. 5 is a diagram showing a computing unit for butterfly computing of the LOT computing device of the electronic camera according to the present invention.

FIG. 6 is a diagram showing a computing unit for butterfly computation of the LOT computing device of the electronic camera according to the present invention.

FIG. 7 is a diagram showing a computing unit for butterfly computing of the LOT computing device of the electronic camera according to the present invention.

FIG. 8 is a diagram showing input / output pixels of the LOT calculation device of the electronic camera according to the present invention.

FIG. 9 is a block diagram of a LOT calculation device according to the first embodiment.

FIG. 10 is a diagram for explaining calculation during LOT of the LOT calculation device according to the first embodiment.

FIG. 11 is an ILOT of the LOT operation device according to the first embodiment.
It is a figure for demonstrating the calculation at the time.

FIG. 12 is a diagram showing arithmetic elements of the LOT arithmetic device according to the first embodiment.

FIG. 13 is a diagram showing an arithmetic element of the LOT arithmetic device according to the first embodiment.

FIG. 14 is a diagram showing an arithmetic element of the LOT arithmetic device according to the first embodiment.

FIG. 15 is a diagram showing a computing element of the LOT computing device according to the first example.

FIG. 16 is a configuration diagram of a Y ₁ stage of the LOT operation device according to the first embodiment.

FIG. 17 is a configuration diagram of a Y ₂ stage of the LOT operation device according to the first embodiment.

FIG. 18 is a block diagram for explaining a data flow during LOT of the LOT arithmetic unit according to the first embodiment.

FIG. 19 is an ILOT of the LOT arithmetic unit according to the first embodiment.
It is a block diagram for explaining the flow of data at the time.

FIG. 20 is a block diagram of a LOT calculation device according to a second embodiment.

FIG. 21 is a diagram showing a computing unit for butterfly computation of the LOT computing device according to the second embodiment.

FIG. 22 is a configuration diagram of an X operation unit of the LOT operation device according to the second embodiment.

FIG. 23 is a configuration diagram of a Y calculation unit of the LOT calculation device according to the second embodiment.

FIG. 24 is a block diagram of a LOT calculation device according to a second embodiment.

FIG. 25 is a two-dimensional X of the LOT operation device according to the second embodiment.
It is a circuit block diagram of a calculating part.

FIG. 26 is a two-dimensional X of the LOT operation device according to the second embodiment.
It is a figure explaining the conversion operation by a calculating part.

FIG. 27 is a two-dimensional Z of the LOT operation device according to the second embodiment.
It is a block diagram of a calculating part.

FIG. 28 is a diagram for explaining the operation of each block in the forward direction of the LOT operation device according to the second example.

FIG. 29 is a diagram for explaining the operation of each block in the reverse direction of the LOT operation device according to the second example.

FIG. 30 is a configuration diagram for explaining an operation during LOT of the LOT operation device according to the third embodiment.

FIG. 31 is an ILOT of the LOT operation device according to the third embodiment.
It is a block diagram for demonstrating the calculation at the time.

FIG. 32 is a configuration diagram showing a data conversion and quantization unit of the LOT operation device according to the third embodiment.

FIG. 33 is a configuration diagram showing an inverse data conversion and inverse quantization unit of the inverse LOT operation device according to the third example.

FIG. 34 is a diagram for explaining serial operation in the LOT operation device according to the third embodiment.

FIG. 35 is a diagram for explaining serial operation in the LOT operation device according to the third embodiment.

FIG. 36 is a diagram for explaining serial operation in the LOT operation device according to the third embodiment.

FIG. 37 is a circuit configuration diagram in the case where the data conversion unit of the LOT operation device according to the third example is configured by a serial operation circuit.

FIG. 38 is a diagram illustrating a serial arithmetic element according to the third embodiment.

FIG. 39 is a diagram illustrating a serial arithmetic element according to the third embodiment.

FIG. 40 is a diagram illustrating a serial arithmetic element according to the third embodiment.

FIG. 41 is a block diagram showing a circuit configuration for serial operation of the LOT operation device according to the third embodiment of the invention.

FIG. 42 is a timing chart of serial operation of the LOT operation device according to the third embodiment.

FIG. 43 is a diagram showing a format of input data to the serial operation element of the LOT operation device according to the third example.

FIG. 44 is an inverse LOT of the LOT operation device according to the third embodiment.
It is a figure which shows the combination of the Y stage and Z stage at the time.

FIG. 45 is a block diagram showing a data flow of the Y stage and the Z stage at the time of LOT of the LOT operation device according to the third example.

FIG. 46 is a Y stage at the time of reverse LOT of the LOT operation device,
It is a block diagram which shows the flow of data of Z stage.

[Fig. 47] Fig. 47 is a block diagram illustrating a data flow at the time of inverse LOT when the Z stage of the LOT arithmetic device is one.

FIG. 48 is a block diagram of a conventional electronic camera.

[Fig. 49] Fig. 49 is a diagram for describing block distortion of a reproduction screen of a conventional electronic camera.

FIG. 50 is an enlarged view of the noise part for explaining the block distortion of the conventional electronic camera.

[Explanation of symbols]

2 Optical system 3 CCD 4 Y / C processing circuit 5 Frame memory 7 Encoding / decoding circuit 8 Memory card 9 Playback circuit 11 Electronic camera 12 Image compression / expansion circuit 21,100 LOT arithmetic unit 22 Y ₁ stage (first arithmetic processing 23 Y ₂ stage (second arithmetic processing unit) 24 1 block line memory 25 Z stage 26-33 switch 40 switch switching circuit 101, 102 DCT device 121 LOT arithmetic device 122 two-dimensional X arithmetic unit (first arithmetic processing unit) ) 123 two-dimensional Y operation unit (second operation processing unit) 124 to 126 one block line memory 127 two-dimensional Z operation unit 131 to 134 data latch 135, 136 adder-subtractor 137 adder 138 subtractor 139 data selector 141, 142 1 Dimension Z calculator 143, 144 Block buffer 23 Y stage 232 Z stage 240 LOT calculation unit 241 the data conversion unit 242 quantization unit 251 inverse quantization unit 252 inverse data transformation unit 271 one time unit delay 272 1 time unit delay full adder 273 1 time unit delay full sub scan tractor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. 2-413515 (32) Priority date Hei 2 (1990) December 21 (33) Priority claim country Japan (JP)

Claims (1)

[Claims] 1. A condensing unit that condenses light incident from an object, a photoelectric conversion unit that converts the light condensed by the condensing unit into an electric signal, and an electric signal by the photoelectric conversion unit. The image signal stored in the storage unit is stored using a storage unit that stores the converted image signal in a predetermined form and a primitive function that superimposes data between adjacent blocks of the image signal stored in the storage unit. An arithmetic means capable of performing an overlap orthogonal transform (LOT) and performing an inverse overlap orthogonal transform (ILOT); and a signal generating means for generating a predetermined reproduction signal based on the inverse overlap orthogonal transform image signal from the arithmetic means. The calculation means calculates one block data at the time of LOT and calculates the data of a plurality of blocks at the time of ILOT, and the data of one block at the time of ILOT. And, an electronic camera, characterized in that a second calculating means for calculating a data LOT at multiple blocks.