JPH0594325A - Monitoring controller - Google Patents

Abstract

PURPOSE:To improve the through-put of a system by checking the duplex memory to preserve the system data without laying software and decreasing the software load necessary for checking in a duplex monitoring control system using a CPU and a memory. CONSTITUTION:CPU 10 and 20 write to both duplexed memories 30 and 40, and at the memories 30 and 40, by using the idle time on a subsequent bus from a writing signal, data and timing to compare the data are sent to a coincidence detecting circuit 50. At the coincidence detecting circuit 50, the data to come from both duplexed memories 30 and 40 are compared, and at the time of the non-coincidence, it is informed to the CPU 10 and 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a supervisory control device having an active spare structure, and more particularly to a supervisory control device having improved data processing efficiency for increasing system throughput.

[0002]

2. Description of the Related Art A conventional monitor and control system, as shown in FIG.
The control panel 100 is composed of an active control panel 100 and a standby control panel 200.
0 is the CPU 101, 201 and the memory 10 respectively
2,202 are installed. In the operation of this conventional example, one operates as an active system and the other operates as a standby system by a system selection signal 300 from the outside of the active system. Address bus 103, 2 between CPU and memory
03, data buses 104 and 204, write signal 10
5, 205 and call-in signals 106, 206. The supervisory control command is controlled by the active CPU 101, and the memory 10 connected from the CPU 101 is connected.
The monitoring data and other data necessary for the system are left in 2. Further, if there is any failure in the active control panel 100, it is necessary to switch to the standby control panel 200 to operate. Therefore, every time the data in the active memory 102 is rewritten, backup of the standby system data is performed via the serial bus 400. Has established working / spare dual system operation.

[0003]

Since the above-mentioned conventional monitoring and control apparatus backs up the data by using serial communication, it is not possible to remove the other spare system during the pack-up, and at the time of maintenance. There is a drawback that work is difficult. Further, in a system in which the backup of data to be written in the memory changes frequently, serial communication is also frequently performed, and there is a drawback in that the time processing efficiency of the original supervisory control is lowered.

[0004]

SUMMARY OF THE INVENTION A supervisory control device according to the present invention receives written data from both CPUs having an active system and a standby system and the CPUs of the active / spare system and sends out controlled data. Two storage means and a coincidence detection means for receiving data to be compared and a timing signal from each of the storage means, comparing them, and notifying the CPU when there is no coincidence are provided.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a supervisory control device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a memory 30 and a match detection circuit 50 which are essential parts of the present embodiment. In FIG. 1, one of the CPU 10 and the CPU 20 becomes the active system by the system selection signal 60, and the right to control the system is obtained. Temporarily CPU10
When becomes the active system, the address signal 11, the data signal 12, the write signal 13, the read signal 14, and the CLK signal 15 are passed from there to the memories 30 and 40. The operations of the memories 30 and 40 are the same for writing, but for reading, they cannot be output to the CPU 10 by the system selection signal 60 from the memory in the active system.

Next, the operation at the time of writing to the memory will be described. Generally, the timing of the CPU peripheral circuit is as shown in FIG. 3, and the reference CLK signal is changed from T1 to T.
It is divided into 4 timings up to 4 and is controlled by repeating them. When written to the memory from the CPU, the write signal is written to the memory at the end of the T3 cycle using the rising edge that changes from low level to high level. The CPU 10 simultaneously writes data in the memories 30 and 40 by the above process. In the memories 30 and 40 instructed to write, as shown in FIG. 2, the data is written into the internal memory 36 at the rising edge of the write signal 13 via the write buffer 33. The write signal 13 is delayed by the clock signal 15 to create a low pulse in the T4 cycle section, and the AND 37 of this signal and the read signal 14 is taken as the read signal of the internal memory. Therefore, the internal memory 36 performs the read operation not only when the normal read signal 14 from the CPU 10 is received but also in the T4 cycle of the write cycle. This read signal is passed to the coincidence detection circuit 50 as the comparison data output 31 (see FIG. 1). The low pulse of the T4 cycle is also passed to the coincidence detection circuit 50 as the comparison detection timing 32 at the same time. In the coincidence detection circuit 50, the comparison data 31, 41 and the comparison detection timings 32, 42 are passed from the memories 30, 40. Then, the comparison data 31 and 41 are compared, and it is determined whether the memories 30 and 40 are coincident or non-coincident at the comparison timing indicating the T4 cycle.
This signal is passed to the CPUs 10 and 20 as the non-coincidence signal 51, and in the case of FIG. 2, it is determined that the data is in agreement when the data is low, and the memory is not in agreement when the data is high. As described above, every time data is written from the active CPU 10, the active and standby memories are immediately checked to find an abnormality.

[0007]

As described above, according to the present invention, the memory 3 is used.
By providing a data simultaneous writing circuit and a data coincidence detecting circuit for 0 and 40, focusing on the operation cycle of the CPU, the memory of the system having the active and standby configurations can be implemented without imposing any burden on the software. You can backup and check it. Therefore, it is effective in reducing the load on the CPU and shortening the throughput time of the system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a main part of the present embodiment.

FIG. 3 is a time chart explaining the operation of the present embodiment.

FIG. 4 is a block diagram of a conventional supervisory control device.

[Explanation of symbols]

 10, 20 CPU 30, 40 Memory 33 Write buffer 34 Read buffer 35 Delay circuit 36 Memory 37 AND 50 Match detection circuit

Claims (1)

[Claims] 1. Two CPUs having an active system and a standby system
And two storage means for receiving written data from both the active / standby CPUs and sending out controlled data, and comparing and comparing data and timing signals from the respective storage means, if they do not match, A supervisory control apparatus comprising: a coincidence detecting unit for notifying the CPU.