JPH0594327A - On-line information control system - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to an online information control system,
The configuration control information and the power supply confirmation information sent from the service processor are once held in each board, set in synchronization with the synchronization setting signal, and sent to the interface of each device,
It is an object of the present invention to make the change processing time very short, to eliminate the system stop time, and to eliminate the error occurrence due to the timing deviation in a plurality of substrates. [Configuration] The configuration control information and the power supply confirmation information sent on each board are sequentially set in the configuration control information register 2 and the power supply confirmation information register 3, and the configuration control information register 2 and the power supply confirmation are set based on the synchronization setting signal. The information set in the information register 3 is transferred to the configuration control information copy register 5
And the power supply confirmation information copy register 6 are simultaneously copied, and the online information generated based on them is sent to the interface of each device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on-line information control system for an information processing device that processes data.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, when a service processor sets online information of devices (devices that exchange data) A0, A1, and A2 to the device B, the number of devices A is small. In the case of a small scale, the device B can be composed of one substrate, and the online information of the devices A0, A1 and A2 is set under the structure of FIG. The configuration and operation of FIG. 6 will be briefly described below with reference to the time chart of FIG.

In FIG. 6, a counter 41 counts in synchronization with the SVP clock from the service processor when the valid signal sent from the service processor is in the ON state. Is a storage address of.

The configuration control information register 42 is a register for holding the configuration control information sent from the service processor via a 1-bit bus. Power supply confirmation information register 43
Is a register for holding the power supply confirmation information sent from the service processor via the 1-bit bus.

A logical product circuit 44 performs a logical product operation corresponding to bits of the contents of the configuration control information register 42 and the power supply confirmation information register 43, and sends the result as online information to the interface of each of the devices A0 to A3. Is.

DEC is a decoder for decoding the value of the counter 41, and indicates the position where 1-bit data is stored in the configuration control information register 42 and the power supply confirmation information register 43.

Next, the operation will be described. In FIG. 7, the counter 41 is cleared to 0 when the valid signal is inactive and the SVP clock falls.

Is a valid signal active and SVP
The configuration control information and the power supply confirmation information sent from the service processor to the 1-bit bus at the rising edge of the clock are stored in the configuration control information register 42 and the power supply confirmation information register 43, respectively.

The counter 41 increments by 1 at the falling edge of the SVP clock. Thereafter, and are similarly repeated, the logical product circuit 44 performs a logical product operation of the contents of the configuration control information register 42 and the power supply confirmation information register 43, and sends the result as online information to the interface of the device A0 or A2.

[0010]

When a failure occurs in one device A and it is desired to change the configuration control information, that is, the connection information, the service processor temporarily suspends all normal operations of the other device A. After that, the relevant bit (connection information) of the device A to be changed in the configuration control information register 42 is turned off, the data is sent to the interface of the device A to change the connection, and the operation of the system that has been stopped is restarted. Was there. Therefore, when the number of devices A increases and the system becomes a large-scale system, the device B cannot be composed of one substrate and must be composed of a plurality of substrates. Problem occurs in device B.

(1) When a failure occurs in one device A and the configuration control information, that is, the connection information is changed, the service processor stops the normal operation of the other device A and changes the configuration control information. After that, if the operation is restarted, the load on the service processor becomes heavy due to the large number of devices A, the processing time for the change becomes long, and the system down time becomes long. Resulting in.

(2) Also, for example, from device A0 to device A
When a power failure such as a momentary interruption of the device A0 occurs during the data transfer to 1, the power supply confirmation information of the device A0 in each board is temporarily turned off, but if the turn-off timing is different for each board. An error may occur in the device A0 or the device A1. More specifically, the part of data exchange between the service processor and the device B is processed in synchronization with the low-speed SVP clock of the service processor, and even if there are different variations in each board, there is no particular problem and the same. Data can be exchanged. But,
Due to the different variations in each board, the operation timing of the interface is slightly different in each board. As a result, if the timing at which the power supply confirmation information of the device A0 in each board changes changes, the operation of the interface of the device A0 or A1 in each board at the time of power failure will be different, so that an error will occur in the device A0 or A1. May occur. In order to solve this, it is desired to set the power supply confirmation information and the like in a plurality of boards in synchronization with the internal system clock.

According to the present invention, the configuration control information and the power supply confirmation information sent from the service processor are temporarily held in each board, and the held information is set all at once in synchronization with the synchronization setting signal. The purpose is to send the data to the interface, to shorten the processing time for changing the configuration control information and the like, to eliminate the system down time, and to eliminate the occurrence of errors due to timing deviations in a plurality of boards.

[0014]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, the configuration control information register 2 is a register that sets the configuration control information of 1 to multiple bits sent from the service processor in synchronization with the SVP clock.

The power supply confirmation information register 3 is a register for setting the power supply confirmation information of 1 to plural bits sent from the service processor in synchronization with the SVP clock.

The configuration control information copy register 5 is a register for copying the configuration control information set in the configuration control information register 2. The power supply confirmation information copy register 6 is
This is a register for copying the power supply confirmation information set in the power supply confirmation information register 3.

When the synchronization setting signal generator 4 completes the setting of the information sent from the service processor to the configuration control information register 2 and the power supply confirmation information register 3,
These pieces of information are synchronized with the system clock, and the configuration control information copy register 5 and the power supply confirmation information copy register 6
The synchronization setting signal to be copied to is created.

[0018]

In the present invention, as shown in FIG. 1, SV is formed on each substrate.
The configuration control information and the power supply confirmation information sent from the service processor in synchronization with the P clock are sequentially set in the configuration control information register 2 and the power supply confirmation information register 3, and when the setting is completed, the synchronization setting signal creation unit 4 Creates a synchronization setting signal in synchronization with the system clock, and based on this, the information set in the configuration control information register 2 and the power supply confirmation information register 3 on each board is transferred to the configuration control information copy register 5 and the power supply. The information is copied all at once to the fixed information copy register 6, and the online information generated based on the information of the both after copying is sent to the interface of each device.

Therefore, the configuration control information and the power supply confirmation information sent from the service processor are once held in each board, and the held information is synchronized with the synchronization setting signal created by using the system clock, and all of them are collectively sent. By making a copy to the configuration control information copy register 5 and the power supply confirmation information copy register 6 and sending the online information generated based on this to the interface of each device, the processing time for changing the configuration control information and the like is greatly shortened. It is possible to eliminate the system stop time, and to eliminate the error occurrence due to the timing shift in the plurality of substrates.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, a device B is composed of a plurality of boards, receives 1-bit or multi-bit configuration control information and power supply confirmation information from a service processor, and sends this to the interface of the corresponding device A0-An. The counter 1, the configuration control information register 2, the power supply confirmation information register 3, the synchronization setting signal creation unit 4,
The configuration control information copy register 5, the power supply confirmation information copy register 6, the online information generation unit 7, and the like. Here, the synchronization setting signal creation unit 4
It is provided only on one of the boards of the device B, and this is used as a master to create a synchronization setting signal, and the other board of the device B is used as a slave to notify the synchronization setting signal, and the configuration control information register 2 and the power source are determined synchronously. The information set in the information register 3 is simultaneously copied to the configuration control information copy register 5 and the power supply confirmation information copy register 6.

The counter 1 counts in synchronization with the SVP (service processor) clock when the valid signal is in the ON state, and the configuration control information and the power supply confirmation information sent from the service processor via the 1-bit bus. ,
Configuration control information register 2 and power supply confirmation information register 3
It shows the address to be stored in the corresponding position of.

The configuration control information register 2 is a register for setting the configuration control information sent from the service processor via the 1-bit bus in synchronization with the SVP clock.

The power supply confirmation information register 3 is a register for setting the power supply confirmation information sent from the service processor via the 1-bit bus in synchronization with the SVP clock.

When the synchronization setting signal creating section 4 completes the setting of information in the configuration control information register 2 and the power supply confirmation information register 3, the configuration control information and the power supply confirmation information are collectively controlled in synchronization with the system clock. The synchronization setting signal for copying to the information copy register 5 and the power supply confirmation information copy register 6 is created.

The configuration control information copy register 5 is a register for copying the configuration control information in synchronization with the synchronization setting signal from the configuration control information register 2. The power supply confirmation information copy register 6 is a register for copying the power supply confirmation information from the power supply confirmation information register 3 in synchronization with the synchronization setting signal.

The online information generator 7 is for generating online information. The information of the configuration control information copy register 5 and the power supply confirmation information copy register 6 is ANDed in bit correspondence and the result is online information. Is generated as. This generated online information is
It is sent to the interface of each device A0 to An.

Next, the operation of the configuration shown in FIG. 1 will be described. (1) When the valid signal is inactive, the counter 1 is cleared to 0 in synchronization with the SVP clock.

(2) The configuration control information and the power supply confirmation information are transmitted to the 1-bit bus in response to the configuration control information and the power supply confirmation information being sent to the 1-bit bus while the service processor activates the valid signal. The data is stored in the register 2 and the power supply confirmation information register 3 in synchronization with the SVP clock. Then, the counter 1 is incremented by 1.

(3) Similarly, (2) is repeated,
This is repeated until the predetermined bits of the configuration control information and the power supply confirmation information are stored. (4) After storing the configuration control information and the power supply confirmation information for a predetermined number of bits in the configuration control information register 2 and the power supply confirmation information register 3, the synchronization setting signal creation unit 4 creates the synchronization setting signal synchronized with the system clock. Then, this synchronization setting signal is notified to the other boards of the device B, and the configuration control information and the power source confirmation information set in the configuration control information register 2 and the power source determination information register 3 are simultaneously sent by the synchronization setting signal. It is copied to the configuration control information copy register 5 and the power supply confirmation information copy register 6, and the online information generating unit 7 performs a logical AND operation on each of these pieces of information in bit correspondence, and the result is stored as online information in the corresponding device A0 to An. Send to the interface.

As described above, the configuration control information and the power supply confirmation information sent from the service processor via the 1-bit bus in synchronization with the SVP clock are set in the configuration control information register 2 and the power supply confirmation information register 3, and the configuration control is performed. Information and power confirmation information setting,
A synchronization setting signal synchronized with the system clock is created, and in synchronization with this, the information in the configuration control information register 2 and the power supply confirmation information register 3 is simultaneously copied to the configuration control information copy register 5 and the power supply confirmation information copy register 6,
The logical product operation of these two pieces of information is performed bit by bit, and the result is sent to the interfaces of the devices A0 to An as online information. This allows
The processing time when changing the configuration control information etc. is very short, the time to stop the system is almost eliminated,
In addition, it is possible to eliminate the occurrence of errors due to timing deviations on a plurality of substrates.

FIG. 2 shows a system configuration diagram of the present invention.
It sends configuration control information and power supply confirmation information to device B from the service processor via the 1-bit or multi-bit bus. The device B sends the result of the logical product operation of the received configuration control information and power supply confirmation information as online information to the interface of the corresponding device A0 to An to set or change the configuration. Here, the device B is composed of a plurality of substrates ID0, ID1 ... IDn. Each of the boards ID0 to IDn has the configuration of the device B of FIG. 1, the board having the synchronization setting signal generating unit 4 is the master board, and the other boards not having it are slave boards.

FIG. 3 is a diagram illustrating a specific example of the present invention. This is a specific example of the configuration of FIG. In FIG. 3, the service processor 8 provides various services. Here, in synchronization with the SVP clock, the configuration control information and the power supply confirmation information are transmitted to the device B through the 1-bit bus.
To send to.

Reference numeral 1 denotes the counter 1 of FIG. 1, which counts in synchronization with the SVP clock when the valid signal is in the ON state. Reference numeral 2 denotes the configuration control information register 2 of FIG. 1, which stores the configuration control information sent from the service processor 8 via the 1-bit bus.

Reference numeral 3 denotes the power supply confirmation information register 3 in FIG. 1, which stores the power supply confirmation information sent from the service processor 8 via the 1-bit bus. 41
1 corresponds to the synchronization setting signal generator 4 in FIG. 1 and is a synchronization circuit for generating a synchronization setting signal synchronized with the system clock.

Reference numeral 5 denotes the configuration control information copy register 5 of FIG. 1, which copies the configuration control information stored in the configuration control information register 2 in synchronization with the synchronization setting signal.

Reference numeral 6 denotes the power supply confirmation information copy register 6 of FIG. 1, which copies the power supply confirmation information stored in the power supply confirmation information register 3 in synchronization with the synchronization setting signal.

Reference numeral 71 corresponds to the online information generator 7 of FIG. 1, and is a configuration control information copy register 5
And the power supply confirmation information and the power supply confirmation information copied to the power supply confirmation information copy register 6 are AND circuits for performing a logical AND operation in bit correspondence.

Next, referring to the time chart of FIG.
The operation of the above configuration will be described in detail. In FIG.
The valid signal is inactive, and the counter 1 is cleared to 0 at the falling edge of the SVP clock.

Is a valid signal is active, S
At the rising edge of the VP clock, the configuration control information and the power supply confirmation information are stored in the configuration control information register 2 and the power supply confirmation information register 3, respectively.

Is a valid signal is active and S
Counter 1 is incremented by 1 at the falling edge of the VP clock,
Set to "1". As a result, the next configuration control information and power supply confirmation information are at the position “1” where they are stored in the configuration control information register 2 and the power supply confirmation information register 3.

In the same manner as above, the above operation is repeated, for example, one bit for eight times to store one byte of configuration control information and power supply confirmation information in the configuration control information register 2 and the power supply confirmation information register 3.

In (1), the configuration control information and the power supply confirmation information are set in the configuration control information register 2 and the power supply confirmation information register 3 for each predetermined bit (for example, 8 bits), and the valid signal becomes inactive. So
At the rising edge of the SVP clock, the synchronization circuit 41 creates a synchronization setting signal synchronized with the system clock. Here, as the synchronization setting signal, the setting signal generated at the rising edge of the SVP clock when the valid signal is inactive is sent to the three-stage FF (flip-flop) using the system clock, and the system as shown in the lower right is displayed. Created as a signal corresponding to one clock cycle. Here, the SVP clock is, for example, 300 ns, and the system clock has a cycle of 20 ns.

On the basis of the synchronization setting signal, reads out the configuration control information and the power supply confirmation information stored in the configuration control information register 2 and the power supply confirmation information register 3,
Copy (set) to the configuration control information copy register 5 and the power supply confirmation information copy register 6. Then, the logical AND operation of the configuration control information and the power supply confirmation information set in the configuration control information copy register 5 and the power supply confirmation information copy register 6 is performed bit by bit, and the result is used as online information in the corresponding device A0 or. Send to the An interface.

Incidentally, the synchronization setting signal exists only in the master substrate of the device B, and the other slave substrates of the device B receive the notification of the synchronization setting signal from the master, and copy simultaneously based on this.

[0046]

As described above, according to the present invention,
The configuration control information and the power supply confirmation information sent from the service processor are temporarily held in each board, and the held information is synchronized with the synchronization setting signal created by using the system clock, and the configuration control information copy register is sent all at once. 5 and the power supply confirmation information register 6 are used, and the online information generated based on this is sent to the interface of each device, so the change processing time of the configuration control information etc. can be made extremely short. The system stop time can be eliminated, and the error occurrence due to the timing deviation in the plurality of substrates can be eliminated. In detail, (1) When changing the configuration control information, the service processor only needs to issue the changed configuration control information to the device B. In response to this, the device B causes the system clock to change. Since the changed configuration control information is set at the same time in synchronization with the synchronization setting signal created using, the change processing time becomes very short.

(2) Further, since this changing process may be performed during the operation of the system, it is not necessary to temporarily stop the system as in the conventional case, and the system stop time is eliminated.

(3) For example, even if a momentary interruption of the device A0 occurs during data transfer from the device A0 to the device A1, all of the devices B synchronize with the synchronization setting signal created by using the system clock. , The power supply confirmation information of the device A0 is turned off at the same time, so that the operation timings of the interfaces of the devices A0 and A1 are not erroneous.
At 0 and A1, the occurrence of errors due to the timing deviation is eliminated.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a system configuration diagram of the present invention.

FIG. 3 is a configuration diagram of a specific example of the present invention.

FIG. 4 is a time chart of the configuration of FIG.

FIG. 5 is a system configuration diagram of a conventional example.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is a time chart of a conventional example.

[Explanation of symbols]

 1: Counter 2: Configuration control information register 3: Power supply confirmation information register 4: Synchronous setting signal creation unit 41: Synchronous circuit 5: Configuration control information copy register 6: Power supply confirmation information copy register 7: Online information generation unit 71: Logical product Circuit 8: Service processor

Claims (1)

[Claims] 1. In an online information control system for an information processing apparatus for processing data, a configuration control information register (2) for setting configuration control information of 1 to multiple bits sent from a service processor in synchronization with an SVP clock. ), The power supply confirmation information register (3) for setting the power supply confirmation information of 1 or more bits sent from the service processor in synchronization with the SVP clock, and the configuration control set in the configuration control information register (2). A configuration control information copy register (5) for copying information and a power supply confirmation information copy register (6) for copying the power supply confirmation information set in the power supply confirmation information register (3) are provided on each board. At the same time, complete the setting of information in the configuration control information register (2) and the power supply confirmation information register (3) on either board And a sync setting signal creating section (4) for creating a sync setting signal for copying the information to the configuration control information copy register (5) and the power supply confirmation information copy register (6) in synchronization with the system clock. And sequentially setting the configuration control information and the power supply confirmation information sent from the service processor in synchronization with the SVP clock on each board in the configuration control information register (2) and the power supply confirmation information register (3), The configuration control information register (2) and the power supply confirmation information register (3) on each board based on the synchronous setting signal created by the synchronous setting signal creating unit (4) in synchronization with the system clock when the setting is completed.
The information set in the above is simultaneously copied to the configuration control information copy register (5) and the power supply confirmation information copy register (6), and the online information generated based on the information of the both is copied to each device. An online information control method characterized by being configured to send to each interface.