JPH0594497A - Arrangement processing system - Google Patents

Abstract

PURPOSE:To provide an arrangement processing system which is capable of correction for eliminating a net violating a wiring limit at the stage of arrange ment processing and capable of reducing man-hour necessary for designing layout. CONSTITUTION:Logical connection information and substrate information is inputted at S1, all the blocks are initially arranged by considering the degree of wiring congestion at S2, the length of the wiring limit of each net at S3, is inputted the length of the virtual wiring limit is calculated from the length of the wiring limit of each net to be stored at S4, the length of the virtual wiring of all the nets are calculated and stored at S5 and the violating net longer than the length of the virtual wiring limit of each net is stored at S6. Then, the arrangement positions of the block referring to the violating net and the other nets are exchanged so as to make the length of the virtual wiring of the violating net to be less than the limiting value of the length of the virtual wiring at 9 and the length of virtual wiring is calculated again to be improved and arranged until the violating net is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout processing method, and more particularly to a layout processing method at the time of layout design when there is a condition of a net wiring length limitation in a gate array LSI.

[0002]

2. Description of the Related Art A conventional layout processing method is a gate array L.
In the layout design when there is a condition of limiting the wiring length of the net in SI, a set of blocks arranged in the vicinity is divided into one group, and the entire LSI is divided into a group consisting of several blocks. The blocks assigned to the group are placed in. Also, they are arranged so that the total sum of the virtual wiring lengths of all nets is minimized.

[0003]

According to the conventional layout processing method described above, in the layout design when there is a condition for limiting the wiring length of the net in the gate array LSI, the entire LSI is divided into groups consisting of several blocks. , When deciding and arranging the area of a group, there is a wiring length limitation because the blocks connected to the net are assigned to different groups or the size of the set group area is large depending on the division method of the group. If the blocks that make up a net are placed separately, it is possible to violate the wiring length limitation.Also, even if the nets are placed so that the total sum of the virtual wiring lengths of all nets is minimized, the virtual There is no guarantee that the wiring length will be less than or equal to the wiring length limit. There is a problem that is likely to violate the. Therefore, when a net violating the wiring limit length occurs, it is necessary to perform the placement process again, which causes a problem that the man-hour increases.

An object of the present invention is to provide a layout processing method capable of reducing the number of man-hours required for layout design, which can be corrected at the stage of layout processing to eliminate nets that violate wiring restrictions. ..

[0005]

According to the layout processing method of the present invention, in the layout processing method of the layout design of the gate array LSI, the logical connection information and the background information are inputted and stored to minimize the congestion degree of the wiring. As described above, all the blocks are initially arranged, and a set of a plurality of terminals to be logically connected between the all blocks and a wiring pattern for connecting the terminals are set as one net. Enter the wiring limit length, which is the limit given to the length of the wiring pattern that connects the terminals according to a predetermined standard for each
The virtual wiring limit length, which is a temporary wiring limit length to be compared with the virtual wiring length calculated for each net from the input wiring limit length of each net, is calculated and stored according to a predetermined criterion, and for each net. The virtual wiring length is calculated and stored, and a violating net that is a net violating a limit in which the virtual wiring length of each net is longer than the corresponding virtual wiring limit length is selected and stored, and this net is stored for each violating net. A virtual wiring length after moving and deciding a moving position for moving at least one of the blocks to which the constituent terminals belong and exchanging the positions of the blocks to which the terminals constituting the violating net belong and the blocks to which the terminals belong Is recalculated, the memory is updated, the violating net is selected again, and the improved arrangement is performed until there is no violating net.

In the placement processing method of the present invention, the virtual wiring length may be calculated by multiplying the virtual wiring length by a coefficient smaller than "1".

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flow chart of a processing procedure according to an embodiment of the present invention.

First, in step (hereinafter referred to as S) 1, L
The logical connection information and the background information are input and stored in order to perform the layout process of the SI layout design. Next, in S2, M
All blocks are initially placed by processing using the IN-CUT method or the like so as to minimize the degree of wiring congestion, and a plurality of logically connected terminals that exist between S3 blocks are connected to these terminals. One pair with the wiring pattern
One net is input, and a wiring limit length, which is a limit given to the length of the wiring pattern for connecting terminals according to a predetermined standard for each net, is input, and is calculated for each net from the input wiring limit length of each net in S4. The virtual wiring limit length, which is a temporary wiring limit length to be compared with the virtual wiring length, is calculated and stored according to a predetermined criterion, and the Steiner tree is obtained for all nets from the result of arranging all blocks in S5. The virtual wiring length is calculated, and the virtual wiring length of each net previously stored in S6 is compared with the virtual wiring limit length of each net also previously stored, and the virtual wiring length exceeds the virtual wiring limit length. Memorize the violation net. Hereinafter, in S7, it is determined whether or not there is a violating net. If there is no violating net, the process is terminated as it is.
The moving destination position where the violating nets previously stored in S8 are taken out one by one, and the blocks to which the terminals constituting the taken violating net belong are moved until the virtual wiring length of the net is within the corresponding virtual wiring limit length. Then, in step S9, the block including the terminal forming the violation net is exchanged with the block placed at the previously determined destination position. At this time, if the block is not placed at the movement destination position, the blocks forming the violation net are placed at the movement destination position. Next, in S10, the virtual wiring lengths of all the nets connected to all the blocks whose layout positions have been moved earlier are recalculated using the Steiner tree, and the previously stored virtual wiring lengths are updated. Further, it is checked whether or not the virtual wiring length of the net recalculated in S11 exceeds the virtual wiring limit length, the stored information of the violating net is updated, and the process returns to S7. The above operation is repeated until the violation net disappears.

FIG. 2 shows a case where the virtual wiring length indicated by S8 in FIG. 1 is moved within the virtual wiring length limit for a violation net whose virtual wiring length limit exceeds the virtual wiring length limit. It is an image diagram showing the arrangement position of.

The blocks 1, 2, 3, 4 have terminals 5, 6, 7, 8, 9 respectively, and are connected to each other via a wiring pattern 9 to form one net 10.

FIG. 2 (A) shows the first block 1,
The placement results of 2, 3, and 4 show that the virtual wiring length of the net 10 exceeds the virtual wiring limit length. In FIG. 2B, the blocks 3 and 4 are moved to make the virtual wiring length virtual. This indicates that the wiring length is within the limit.

To calculate the virtual wiring limit length, the virtual wiring length of each net after the block placement processing is the wiring length when the wiring route between terminals is the shortest route. Since the actual wiring length of the wiring pattern is often longer due to detours and the like, it is calculated by multiplying by a coefficient smaller than "1" while allowing for a margin. At this time, it is possible to change the coefficient depending on the length of the virtual wiring.

[0014]

As described above, according to the present invention, the logical connection information and the background information are input, all blocks are initially arranged so as to minimize the congestion degree of the wiring, and the wiring limit length of each net is input. Then, the virtual wiring limit length of each net is calculated from the input wiring limit length of each net, stored, the virtual wiring length of the net is calculated, and the virtual wiring length of each net is calculated from the virtual wiring limit length of each net. Focusing only on the blocks that make up the long violation net, swap the positions of the blocks that make up the violation net and other blocks so that the virtual wire length of the violation net is less than or equal to the virtual wire length limit value. By performing the improved placement until there is no longer, the virtual wiring length of each net after placement processing is less than the wiring limit length of each net, and there is no net that violates the wiring length limitation at the stage of placement processing, and bypass wiring is performed. Prevention By wiring so, advantageous effect is attained that it is possible to reduce the number of steps modifications required can become the bets on the layout design to eliminate the net that violates the routing restrictions at the stage of the placement process.

[Brief description of drawings]

FIG. 1 is a flowchart of a processing procedure according to an embodiment of the present invention.

FIG. 2 is a layout in which a virtual wiring length shown in S8 of FIG. 1 exceeds a virtual wiring limit length, and an arrangement position of a block including a terminal forming a violation net is moved within the virtual wiring limit length with respect to the violation net. It is an image figure which shows a position.

[Explanation of symbols]

 1,2,3,4 block 5,6,7,8, terminal 9 wiring pattern 10 net

Claims (2)

[Claims] 1. A layout processing method for layout design of a gate array LSI, wherein logical connection information and ground information are input and stored, and all blocks are initially arranged so as to minimize wiring congestion. Each net is made up of a set of a plurality of terminals which are logically connected to each other and a wiring pattern which connects between the terminals, and the terminals are connected according to a predetermined standard for each net. A virtual wiring length, which is a virtual wiring length to be compared with a virtual wiring length calculated for each net from the input wiring restriction length of the input net, is input. The wiring limit length is calculated and stored according to a predetermined standard, the virtual wiring length is calculated and stored for each net, and the virtual wiring length for each net is calculated from the corresponding virtual wiring length. A violating net that violates a long restriction is selected and stored, and a moving position for moving at least one of the blocks to which the terminals configuring the net belong is determined for each violating net to configure the violating net. Replace the position of the block to which the terminal belongs and the block of the move destination, recalculate the virtual wiring length after moving and arranging, update the memory, select the violating net again, and arrange again until the violating net disappears. An arrangement processing method characterized in that 2. The placement processing method according to claim 1, wherein the virtual wiring limit length is calculated by multiplying the virtual wiring length by a coefficient smaller than “1”.