JPH059758B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention [Field of Industrial Application] The present invention relates to an apparatus for measuring a time difference between signals under measurement.

[Conventional technology]

Generally, the following principle is used to measure time with high precision. A clock signal with a period t ₀ is passed through a gate that is open during the period of time to be measured Tx, and the number N of the clocks passing through is counted. And, Nt ₀ is the time width.

Strictly speaking, this method does not hold Tx=Nt ₀ , but rather TxNt ₀ . This is because Tx is usually not divisible by t ₀ and there are small fractional times. This is shown in FIG. In FIG. 7, ΔT ₁ in c is the starting fractional time from the rising edge of Tx to the clock C ₀ occurring immediately after that, and ΔT ₂ in d is the starting fractional time from the falling edge of Tx to the clock C 0 occurring immediately thereafter. It is the stop fractional time to Cn. Then, the gate is opened during the period between the clock signals _C0 and Cn (see e in FIG. 5), and the number of clocks passing through is counted. Letting the number of clocks in that period be N, the time width Tx [f in FIG. 5] is expressed by equation (1).

Tx = Nt ₀ + ΔT ₁ − ΔT ₂ (1) Therefore, by measuring the fractional times ΔT ₁ and ΔT ₂ , it is possible to measure the time width Tx with a resolution greater than the clock period t ₀ (1) It can be seen from the formula.

[Problem that the invention seeks to solve]

However, conventional time measuring devices have a fixed measurement order for the start fractional pulse and the stop fractional pulse, and are configured to always measure the time difference from the start fractional pulse to the stop fractional pulse.

On the other hand, in phase detectors etc., two
There are cases where the order in which two signals are generated (first and second) is uncertain, and it may not be possible to decide which signal should be used as the start, and negative time difference measurement may be required.

Therefore, conventional time measuring devices have not been able to meet such requirements.

An object of the present invention is to provide means that can measure the time difference between two introduced signals, regardless of their precedence/sequence relationship.

B "Structure of the Invention" [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides an apparatus for measuring time differences between signals under test, in which a plurality of signals under test are introduced. means 3 for outputting the signal C in synchronization with the input of the signal under test; a delay means for introducing each signal under test and passing the signal under test at a later time than the generation timing of the signal C; and the signal under test that has passed through the means 3.
output signal C and a clock signal, output the gating clock by passing the clock signal starting from the generation of signal C, and apply the signals under test A ₂ and B ₂ through delay means. a fractional pulse generation circuit that outputs fractional pulses S _A and _SB that become active in synchronization with the timing; a time/voltage converter that introduces the fractional pulses and outputs a signal according to the pulse width; and the gating circuit. A counter for counting the number of pulses, and a computer for calculating the time difference between the measured signals by introducing the counted value of the counter and the output signal of the time/voltage converter. It is something.

Note that one of the points of the present invention is to generate a trigger signal (that is, the signal C) from the signals under measurement A ₁ and B ₁ applied to the device, and to start the gating clock from the generation of this signal C. The main point is that it creates a lock and fractional pulses S _A and S _B. That is, with this configuration, the time difference between two signals can be accurately measured regardless of the relationship between the two signals.

Therefore, since the timing of the gating clock and the end of the fractional pulse are not particularly limited, the timing of the gating clock and the end of the fractional pulse is not particularly limited. The timing has not been specified.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an example of the configuration of the main parts of the time measuring device according to the present invention, FIGS. 2, 3, and 5 are time charts, and FIG. 4 is a specific example of the configuration of the fractional pulse generation circuit. FIG. 6 is a diagram showing a specific example of a time/voltage converter.

In the present invention, as shown in _FIG .
Measure the time difference (+T _I ) when signal B ₁ is earlier than A ₁ [Figure 5 a], and conversely the time difference (-T _I ) when signal B 1 is earlier than A ₁ [Figure 5 b] can do.

In Figure 1, A ₁ and B ₁ are the signals under test,
The time difference between these two signals A ₁ and B ₁ is measured.

1 and 2 are delay lines, and the introduced signal under measurement
It outputs signals A ₂ and B ₂ obtained by delaying A ₁ and B ₁ by a time T _d to compensate for the delay of an OR gate 3 (hereinafter simply referred to as gate 3), which will be described later.

Reference numeral 3 denotes a gate which introduces the signals to be measured A ₁ and B ₁ and outputs a signal C which is the logical sum of the signals A 1 and B 1 .

5 and 6 are fractional pulse generation circuits, which generate signals A ₂ ,
B ₂ , C, and clock signals sc are introduced, fractional pulses S _A and S _B and gating clock signals N _A and N _B
This outputs the following. A specific example of the configuration of the fractional pulse generating circuits 5 and 6 is shown in FIG.

7 and 10 are time/voltage converters, and the fractional pulses S _A , introduced from the fractional pulse generation circuits 5 and 6 are
A voltage signal corresponding to the pulse width of S _B is created, and this is further converted into digital values V _A and V _B and output. A specific example of the configuration of this time/voltage converter is shown in FIG.

Counters 8 and 11 output signals na _{and nb} by counting the number _of pulses of the introduced gating clock signals NA and _NB .

12 is a computer (hereinafter referred to as CPU), which receives signals V _A and V _B from time/voltage converters 7 and 10.
is introduced, signals n _a and n _b are introduced from the counters 8 and 11, and a signal corresponding to the time difference Tx between the signals under test A ₁ and B ₁ is output.

First, the operation of the fractional pulse generation circuit shown in FIG. 4 will be explained. FIG. 2 is a time chart of the circuit of FIG. 4.

In FIG. 4, 21 to 23 are flip-flops which output the state (high or low) of the D terminal to the Q terminal when a signal is applied to the clock terminal ck.

24 and 25 are gates;
The mark ◯ provided at the input terminal 25 means that the polarity of the signal is inverted (inversion of high or low). A clock signal sc shown in FIG. 2 is applied to the clock terminals ck of flip-flops 21, 22, and 23.

Fractional pulse S _A (or
_SB ) is obtained and the gating clock N _A (or N _B ) is obtained as the output of the gate 25 will be described with reference to FIG.

The output C of the gate 3 reaches the fractional pulse generating circuits 5 and 6 earlier than the signal A ₂ (or B ₂ ) due to the action of the delay lines 1 and 2 (see FIGS. 2 and 3). The first clock sc after signal C goes high
The rising edge of 1 causes flip-flop 2
The _Q3 terminal of 2 becomes "high" (see Fig. 2 4).
On the other hand, since the signal A ₂ (or B ₂ ) is "low" when the clock sc1 is generated, the flip-flop 2
1's _Q1 terminal is still "low". Therefore, the gate 25 opens starting from the point in time when the _Q3 terminal of the flip-flop 22 becomes "high" (see FIG. 2). In addition, gate 2 in FIG.
The output waveform N _A of 5 is the clock signal sc of Fig. 2 1.
The phase is inverted. The reason for this is that the phase of the clock signal sc is inverted and introduced into the gate 25 (see the circle mark on the input terminal).

After a certain time T _p after the signal C becomes "high", the signal A ₂ (or
B ₂ ) is added (see Figure 2, 3). Therefore, the output of the gate 24 into which this signal A ₂ (or B ₂ ) is introduced becomes "high". In addition, an explanation will be added regarding the above T _p . Now, assuming that the signals under test A ₁ and B ₁ have the relationship shown in Figure 5a, the rise of signal C in Figure 2 is the same as the rise of the signal under test A ₁ since gate 3 is an OR gate. Sync. Therefore, the first
Signal A ₂ applied to fractional pulse generator circuit 5 in the figure
is applied to flip-flop 21 in FIG. 4 with a delay of T _d in delay line 1. Therefore, in the fractional pulse generating circuit 5, T _p =T _d . On the other hand, in Fig. 5a, the signal under test _B1 is generated with a delay of T _I , so
In the fractional pulse generation circuit 6 shown in the figure, the
T _p = T _d + T _I.

Then, at the first rising edge of clock sc2 after signal A ₂ (or B ₂ ) goes high,
The _Q1 terminal of flip-flop 21 becomes "high" (see FIG. 2, 5). Since the gate 25 inverts the output signal of this Q ₁ terminal and introduces it, this Q ₁
When the terminal becomes "high", the gate is closed and the passage of the applied clock signal sc is blocked (see FIG. 2, 8).

Since the _D2 terminal of the flip-flop 23 becomes "high", the _Q2 terminal becomes "high" at the next rising edge of the clock sc3. Gate 24 is this
Since the output signal of _Q2 terminal is inverted and introduced,
When the Q ₂ terminal becomes “high”, the gate 2
The output of 4 becomes "low" (see FIG. 2, 7).

In this way, from the output terminal of the gate 24 in FIG. 4, the fractional pulse S _A (or S _B ) shown in FIG.
is obtained, and the gating clock N _A (or N _B ) shown in FIG. 2 is obtained from the output terminal of the gate 25.

In addition, in Fig. 7, the start and stop fractional times ΔT ₁ and ΔT ₂ (hereinafter, fractional times are referred to as ΔT) are calculated from the rising and falling edges of the measured time width Tx [Fig. 7a] and immediately after these. Clock signal generated
This was explained as the period up to C ₀ and Cn. However, since the width ΔT of the fractional pulse exists between 0 and _t0 ,
In some cases, the pulse width of the fractional pulses may have to be extremely close to zero. However, it is very difficult to generate a pulse of ΔT0, for example. Therefore, in the following explanation,
The pulse widths T _A and T _B of the fractional pulses generated by the fractional pulse generators 5 and 6 will be explained as T _A =ΔT+t ₀ . Of course, the same applies to T _B. If you do this, T _A will never become 0.

ΔT: Width of the fractional pulse explained in FIG. 7 t ₀ : Period of the clock signal sc Next, the operation of FIG. 1 will be explained with reference to FIG. 3.

A signal under test A ₁ shown in FIG. 3 is applied to the delay line 1, and a signal under test B ₁ shown in FIG. 3 is applied to the delay line 2. At gate 3, this signal A ₁ ,
Since the logical sum of _B1 is calculated, when either signal becomes "high", the output C of gate 3 also becomes "high". Note that due to the delay of the gate 3 itself, the phase of the signal C is slightly delayed from the signals under test A ₁ and B ₁ (see FIG. 3 and 4).

In the fractional pulse generating circuits 5 _{and 6} as explained in FIG.
It must become active before the signal A ₂ (B ₂ ) applied to the signal A 2 (B 2 ). The reason is that the output from the _Q3 terminal of the flip-flop 22 opens the gate 25, and the output from the _Q1 terminal of the flip-flop 21 opens the gate 25.
This is because it operates to close the . Therefore, in FIG. 1, delay lines 1 and 2 are provided to delay the signals under test A ₁ and B ₁ by the time T _d , and the signals 5 and 6 in FIG.
The signals A ₂ and B ₂ shown in
In addition to

The fractional pulse generation circuit performs the operations described above to generate fractional pulses S _A and S _B (Fig. 3, 8 and 10).
) and gating clocks N _A , N _B (3rd
(see Figures 7 and 9).

Gating clocks N _A and N _B are counted by counters 8 and 11, respectively, and their values n _a and n _b are
Sent to CPU12.

On the other hand, the pulse widths T _A and T _B of the fractional pulses S _A and S _B are converted into voltage signals by time/voltage converters 7 and 10 .

FIG. 6 shows a specific example of the configuration of the time/voltage converters 7 and 10. In FIG. 6, p1 and p2 are input terminals, and a WAIT signal is applied from the CDU 12 to p1. A fractional pulse S _A (or S _B ) is added to p2.

41 is an RS flip-flop (hereinafter simply FF41)
), a standby signal is applied to the S terminal, and a fractional pulse S _A (S _B ) is applied to the R terminal. Further, the output s41 of the Q terminal is used as a signal for controlling a current switch, which will be described later.

A delay line 42 introduces a fractional pulse S _A (S _B ) and delays it by a time τ. The output s42 of this delay line 42 is used as a signal s42 for controlling a current switch, which will be described later. Note that this delay line 42 is not necessarily necessary if the wiring is made longer to delay the signal.

Reference numerals 43 and 46 are constant current sources, and the constant current source 43 causes a constant current i ₁ to flow, and the constant current source 46 causes a constant current i ₂ to flow in the directions as shown in FIG.

44 and 45 are current switches, which can be easily constructed using transistors, for example.
The current switch 44 is controlled on and off by the output signal s41 of the FF 41, and the current switch 45 is controlled on and off by the output signal s42 of the delay line 42. Constant current source 43, current switch 44, current switch 45, and constant current source 46 are connected in series.

Reference numeral 47 denotes an integrating capacitor, which is arranged between the connection point between current switches 44 and 45 and the circuit ground. The terminal voltage of this capacitor 47 changes according to the pulse width of the fractional pulse S _A (S _B ).

48 is a clamping diode, which is provided in parallel with the capacitor 47.

Reference numeral 49 denotes a buffer amplifier, which is composed of an amplifier with high input resistance. This buffer amplifier 49 amplifies the terminal voltage of the capacitor 47, converts the impedance, and transmits it to the next stage.

50 is an AD converter, buffer amplifier 49
It converts the analog signal introduced from the computer into a digital signal and transmits it to the CPU 12. In addition, since high speed is required in the field related to the present invention,
Usually, a successive approximation type AD converter or a flash type (fully parallel type) AD converter is used.

The operation of the time/voltage converter constructed as shown in FIG. 6 is explained in detail in the specification of Japanese Patent Application No. 147570/1988 entitled "Time Measuring Apparatus" by the present applicant.

According to the circuit of FIG. 6, after the pulse width T _A of the fractional pulse S _A , the voltage V _A of the capacitor 47 is expressed by equation (2).

V _A = V _d −1/C∫ ^TA ₀ i ₂・dt = V _d −i ₂・T _A /C (2) where, V _d : Forward voltage of diode 48 C: Capacity of capacitor 47 This capacitor 47 The CPU 12 can calculate the fractional time T _A by introducing the signal V _A obtained by converting the voltage V _A into a digital signal.

Fractional time T _B can be similarly calculated.

The CPU 12 introduces the above-mentioned V _A , V _B , n _a , n _b , calculates T _A , T _B , and further calculates the time difference between the signals under measurement A ₁ and B ₁ by performing the calculation of equation (3). You can get Tx.

Tx = (t ₀ · n _b - T _B ) - (t ₀ · n _a - T _A ) (3) According to the calculation result of equation (3), if Tx < 0, the signal under test A ₁ is smaller than B ₁ . Indicates late arrival, Tx
>0 indicates the opposite.

Furthermore, by providing a set of delay lines, gates, fractional pulse generators, counters, and time/voltage converters for the configuration shown in Figure 1, each time interval can be adjusted for a large number of input signals. can be measured.

C. "Effects of the Present Invention" According to the present invention, since measurements are performed accurately down to the fractional time ΔT, the time difference can be accurately measured regardless of the order in which two signals are generated.

Furthermore, in a time measuring device, it is generally necessary to send a trigger signal to the time measuring device in advance to set the circuit state inside the device before applying a signal to be measured to the device. On the other hand, according to the present invention, the signals under test A ₁ ,
A signal C is obtained from B ₁ by gate 3 inside the device,
This signal C is used as this trigger signal. That is, in the present invention, the signals A ₂ and B ₂ are always applied to the fractional pulse generating circuits 5 and 6 after the signal C is generated. Since the gate 25 is first opened by this signal C as described above, the present invention does not require a trigger signal and it is sufficient to simply apply the signal under test to the device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of the main parts of a time measuring device according to the present invention, FIGS. 2, 3, and 5 are time charts of the device according to the present invention, and FIG. 4 is a fractional pulse generation A diagram showing a specific example of the configuration of the circuit, FIG. 6 is a diagram showing a specific example of the configuration of the time/voltage converter,
FIG. 7 is a diagram showing the principle of time measurement. 1, 2...delay line, 3...gate, 5,6...
Fractional pulse generation circuit, 7, 10... Time/voltage converter, 8, 11... Counter, 12... CPU.

Claims (1)

[Claims] 1. A device for measuring time differences between signals under test, comprising means 3 for introducing a plurality of signals under test and outputting a signal C in synchronization with the input of the first signal under test; a delay means for introducing the measurement signal and passing the signal under test at a later time than the generation time of the signal C; a signal under test that has passed through the delay means; and the means 3.
output signal C and a clock signal, output the gating clock by passing the clock signal starting from the generation of signal C, and apply the signals under test A ₂ and B ₂ through delay means. a fractional pulse generation circuit that outputs fractional pulses S _A and _SB that become active in synchronization with the timing; a time/voltage converter that introduces the fractional pulses and outputs a signal according to the pulse width; and the gating circuit. A counter for counting the number of pulses, and a computer for calculating the time difference between the measured signals by introducing the count value of the counter and the output signal of the time/voltage converter. Characteristic time measurement device.