JPH05977Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a capstan servo circuit for a VTR, and its purpose is to prevent the center of the servo lock range from changing due to changes in motor speed.

The VTR has a standard playback mode in which the magnetic tape is played back while being transported at a first speed v that is equal to the feed speed during recording, and a standard playback mode in which the magnetic tape is played back while being transported at a first speed v that is equal to the feed speed during recording. ), and a high-speed reproduction mode in which reproduction is performed while transferring at a second speed that is an integral number (n, for example, n=9) times faster. Then, in high-speed playback mode, the magnetic tape is driven by a capstan motor having a speed and phase servo so that the noise bar displayed on the screen is fixed on the screen when the track is crossed. . In that case, the frequencies of the phase comparison signal and speed detection signal to be input to the phase comparator and speed error detector are kept substantially unchanged regardless of the mode setting, and the outputs of the phase comparator and speed error detector are The capstan motor is controlled by mixing the two. The speed error detector is then adjusted so that the phase comparator output is located at the center of the servo lock range. By the way, if this adjustment is performed at the first speed and the VTR is set to high-speed playback mode, the rotation speed of the capstan motor will increase and the load will become heavier, causing the center of the phase comparator output to shift to the first speed. Compared to the case of one speed, there is a disadvantage that the capture ability against fluctuation factors that cause the upward displacement, such as a decrease in environmental temperature (in this case, the motor load increases), is reduced.

The present invention aims to provide a capstan servo circuit which can be operated over a wide locking range without substantially changing the center of the phase comparison output due to mode changes.

Next, the circuit of the present invention will be explained according to the illustrated embodiment.
In the figure, 1 is a capstan motor, 2 is a circuit that drives the motor, and 3 is a control circuit that controls the drive circuit 2 to drive the motor 1 at a standard first speed v or a faster second speed nv. 4 is a means for generating a mode identification signal in response to a mode command from the control means 3. This identification signal generating means outputs an identification signal A which is, for example, a low level signal in the standard reproduction mode and a high level signal in the high speed reproduction mode. Reference numeral 5 denotes a control head disposed opposite to the control track of the magnetic tape, which outputs a 30 Hz control signal during standard playback in NTSC and helical scan systems. 6 is means for generating a signal related to the rotation of the motor 1, which outputs a rotation detection signal of 1200 Hz during standard playback. Reference numeral 8 denotes a first frequency divider into which a control signal is input via the amplifier 7, and this first frequency divider is configured to change the frequency division ratio according to the identification signal A, that is, when the identification signal is at a low level. When the frequency division ratio is 1 and the high level, the frequency division ratio is changed to 1/n. As a result, the output of the first frequency divider 8 can output a comparison signal of 30 Hz in any mode. 10 is a second frequency divider into which the rotation-related signal G is input via the amplifier 9, and like the first frequency divider, this frequency divider is also configured to change the frequency division ratio according to the identification signal A. ing. In other words, when the identification signal is at low level, the frequency division ratio is set to 1/10, and when it is at high level, it is set to 1/91, and the rotation detection signal around 120Hz is set in any mode from the rotation detection signal of 1200Hz during standard playback. Output. Here, the reason why the frequency division ratio of the second frequency divider is set to 1/91 in the high-speed reproduction mode is as follows. When reproducing a pattern recorded so that the amount of deviation between adjacent tracks is 1/2 line period at n times high speed, the number of scanning lines H scanned in one field period is H = 262.5-1/2.
(n-1), when n=9, H=258.5, and the frequency of the rotation-related signal at this time is 1200×9×
This is because 262.5/258.5=10967.117Hz. At this time, the rotation detection signal is approximately 120.5Hz, which is almost the same as the standard rotation.

11 is a reference signal generation source that generates a reference signal;
During recording, the vertical synchronization signal of the television signal is used, and during reproduction, an appropriate oscillator, such as one obtained by frequency-dividing the output of a subcarrier generator, is used. Reference numeral 12 denotes a phase comparator that compares the phases of the reference signal B and the output C of the first frequency generator 8 and outputs a first error signal D.
This is a general type including monomultis 13 and 14, a sampling palace creation circuit 15, a trapezoidal wave creation circuit 16, and a sample hold circuit 17. Reference numeral 18 denotes a speed fluctuation detector, which inputs the rotation detection signal E which is the output of the second frequency divider 10, and connects it to a triangular wave generation circuit 20 whose charging time constant is determined by a volume control 19, and holds the output of the circuit at its peak. The circuit 21 outputs the speed error component of the rotation detection signal E as a second error signal F. The volume 19 is adjusted so that the output of the phase comparator 12 is located at the center of the phase lock range during standard playback.

22 is a mixing circuit that mixes the first error signal D, the second error signal F, and the compensation signal H. The compensation signal H is output from the mixing circuit 22 when the identification signal A is at a high level.
A constant level voltage is applied to the voltage, and the voltage is not applied when the voltage is low level. That is, the output of the identification signal generating means 4 is applied to the mixing circuit 22 via the resistor _R1 and the reverse current blocking diode 23. The level of the compensation signal is in high-speed playback mode.
In order to prevent the center of the lock range from shifting upward due to an increase in the first error signal D due to load fluctuations, etc., the identification signal A is set to exhibit a voltage commensurate with this increase, and the identification signal A is connected to a resistor _R1. The partial pressure is applied using R2 and _R2 . The mixing circuit 22 output is applied to the motor drive circuit 2 to control the motor 1.

The device of the present invention applies a constant level voltage to the output (second error signal) of the speed servo system in standard playback mode when the VTR is set to high-speed playback mode.
Since the output of the phase servo system (first error signal) is displaced around the center of the lock range during standard playback, the lock range of the first error signal does not change regardless of the VTR mode. It is practical because it can apply servo lock over a wide range to respond to load fluctuations of the capstan motor. Although this embodiment shows the case where the motor is switched to two stages, it goes without saying that even if the motor is switched to three or more stages, the lock range can be similarly guaranteed for each speed. .

[Brief explanation of drawings]

The drawing is a schematic configuration diagram of the device of the present invention. Explanation of main figure numbers, 3... Control means, 4... Identification signal generation means, 8, 10... First and second frequency dividers,
11... Reference signal generation source, 12... Phase comparator,
6... Rotation speed detection means, 18... Speed error detector, 22... Mixing circuit, H... Compensation signal.

Claims (1)

[Scope of utility model registration request] Set the speed of the capstan motor to the standard first speed v
means for generating a mode identification signal based on the output of the control means; and means for inputting the output of the control head to drive at a substantially constant frequency regardless of the speed difference. a first frequency divider whose frequency division ratio is controlled by the identification signal so as to exhibit an output of a phase comparator for outputting a first error signal; a means for detecting the rotational speed of the motor; a second frequency divider whose frequency division ratio is controlled by a signal; a speed error detector that outputs speed fluctuations of the second frequency divider output as a second error signal; and the first and second error signals. A capstan servo circuit comprising a circuit for mixing the output of the mixing circuit and a circuit for applying the output of the mixing circuit to the motor, characterized in that a compensation signal having a different level is added to the mixing circuit according to the identification signal. capstan servo circuit.