JPH06100944B2 - Clocked semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION [Overview] A clocked semiconductor integrated circuit that operates in synchronization with a clock, such as a clocked static RAM, a clocked ROM,
Regarding a clocked PLA, it is an object of the invention to provide a clocked semiconductor integrated circuit with improved operation efficiency without changing an external clock.
An internal clock generating circuit for multiplying an external clock signal and generating an internal clock signal having a predetermined pulse width specification is incorporated.

[Industrial application field]

The present invention relates to a clocked semiconductor integrated circuit that operates in synchronization with a clock, such as a clocked static RAM, a clocked ROM, and a clocked PLA.

[Problems to be Solved by Prior Art and Invention] Generally, in a clocked semiconductor integrated circuit, for example, a clocked static RAM, it is required to generate clocks having different cycles from an external clock MCK, as shown in FIG. Moreover, the pulse width specifications differ between high level and low level, but it was difficult to change to the required pulse width specifications. Therefore, there is a problem that the operation efficiency of the clocked static RAM is low in order to perform operations such as fetching the address ADD in synchronization with the external clock MCK.

Therefore, an object of the present invention is to provide a clocked semiconductor integrated circuit which has improved operation efficiency without changing the external clock.

[Means for solving problems]

A means for solving the above problems is shown in FIG. In FIG. 1, an internal clock generation circuit 1 is incorporated inside a clocked semiconductor integrated circuit. The internal clock generating circuit 1 multiplies the external clock signal MCK by, for example, 2 and generates an internal clock signal CK having a necessary pulse width specification.

[Work]

According to the above-mentioned means, one cycle of the internal clock signal CK in the clocked semiconductor integrated circuit becomes, for example, 1/2 of one cycle of the external clock signal MCK, and the pulse width specification of high level / low level is specified. Can be set to

〔Example〕

2 is a detailed circuit diagram of the internal clock generating circuit 1 of FIG. 1, and FIG. 3 is a timing chart of signals appearing in the circuit of FIG. In FIG. 2, reference numeral 2 denotes a pulse signal C having a predetermined width by detecting the rising and falling edges of the external clock signal MCK.
It is a change detection circuit that generates K ₀ . That is, when the external clock signal MCK changes as shown in FIG. 3 (A), a pulse signal CK ₀ having a predetermined width is generated as shown in FIG. 3 (B) at each rising edge and falling edge thereof. In this case, the pulse width τ ₁ of the pulse signal CK ₀ is determined by the delay time of the NAND circuits G ₁ and G ₂ of the change detection circuit 2. Reference numeral 3 is a pulse expansion circuit that expands the pulse of the pulse signal CK ₀ . That is, the pulse width τ ₁ of the pulse signal CK ₀ shown in FIG. 3 (B) is expanded to the pulse width τ _{2 as} shown in FIG. 3 (B). Pulse width τ _{2 in} this case
Is determined by the size of the capacitor C of the pulse expansion circuit 3.

As described above, one cycle of the internal clock signal CK is half of one cycle of the external clock signal MCK, and the pulse width specification has a required high level / low level ratio. Therefore, it is possible to substantially double the operation speed of the clocked static RAM and improve its operation efficiency.

Although the internal clock generation circuit 1 described above doubles the external clock signal MCK, it is multiplied by n (n = 4,8,
...).

〔The invention's effect〕

As described above, according to the present invention, the operating speed of the clocked semiconductor integrated circuit can be increased without changing the external clock signal, and the operating efficiency thereof can be improved.

[Brief description of drawings]

1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a detailed circuit diagram of the internal clock generation circuit of FIG. 1, FIG. 3 is a timing diagram showing the circuit operation of FIG. 2, and FIG. It is a figure which shows the conventional clocked semiconductor integrated circuit. 1: Internal clock generation circuit, 2: Change detection circuit, 3: Pulse expansion circuit.

Claims (1)

[Claims] 1. A clocked semiconductor integrated circuit, wherein an internal clock generating circuit (1) for multiplying an external clock signal (MCK) to generate an internal clock signal (CK) is built in the circuit. A change detection circuit (2) in which the internal clock generation circuit detects a rising or falling change of the external clock signal and generates a pulse signal (CK ₀ ).
And a pulse expansion circuit (3) for expanding the pulse width of the output pulse signal (CK ₀ ) of the change detection circuit to a predetermined width to generate the internal clock signal. Semiconductor integrated circuit.