JPH06102902A - Process controller - Google Patents

Abstract

PURPOSE:To provide a process controller which can suppress a reset winding up phenomenon against the alteration of a target value and which can suppress the adverse influence to a minimum even if a control loop becomes unstable. CONSTITUTION:A control arithmetic part 61 outputs a position form PID arithmetic result to an output limitter 27 from a control target value SV and a control input signal PV. The output limitter 27 outputs a control output signal MVn whose PID arithmetic result is limitted to within an upper limit value or a lower limit value. An integral arithmetic correction part 35 corrects the integral operation of the control arithmetic part 61 to the upper limit value or the lower limit value when the part 35 limits the result to the upper limit value or the lower limit value. An integral arithmetic correction judgement part 63 judges the normality/abnormality of the control input signal PV from the change direction of the control input signal PV and a direction where the PID arithmetic result exceeds the upper limit value or the lower limit value, inhibits the operation of the integral arithmetic correction part 35 at the time of judging abnormality and releases the inhibition when the PID arithmetic result returns to a value between the upper limit value and the lower limit value, for example.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process control device, and more particularly to improvement of a process control device used in a control loop system for process controlling process amounts such as temperature, pressure and flow rate.

[0002]

2. Description of the Related Art In process control, for example, as shown in FIG. 16, a control amount of a controlled object 1 is measured by a sensor 3, and this measurement signal is converted by an input converter 5 into a control input signal PV proportional to the control amount. The control output signal MV is converted and the control output signal MV is output by the PID calculation so that the control deviation between the control input signal PV and the control target value SV becomes “0” in the process control device 7.
The controller 9 outputs a manipulated variable proportional to the control output signal MV, and has a configuration for changing the controlled variable in addition to the controlled object 1 in the state where a disturbance element is added. Is a closed-loop control that matches the control target value SV, and is also called feedback control.
However, in actual process control, the manipulated variable from the manipulator 9 always has a saturation level. Therefore, even if the control output signal MV above the saturation level is output, the manipulated variable from the manipulator 9 is suppressed at the saturation level. Therefore, the amount of the control output signal MV that exceeds the saturation level becomes invalid and is not reflected in the control amount.

Further, in addition to the saturation level caused by the mechanical characteristics of the operating device 9 and the controlled object 1, from the viewpoint of ensuring safety of the control loop system and good production quality, the change range and change of the control output signal MV are You need to limit the rate. Therefore, the process control device 7 includes an output limiter that determines an upper limit value (hereinafter abbreviated as an upper limit) and a lower limit value (hereinafter abbreviated as a lower limit) of the control output signal MV, and a control output signal MV. It is common to provide an output change rate limiter that determines the allowable change rate.

On the other hand, a PID calculation is often used as a calculation method of the process control device 7, but in the PID calculation including the two degrees of freedom PID, an integral calculation is performed to eliminate the control deviation between the control target value SV and the control input signal PV. To use. However, when the control target value SV is changed or a large disturbance is applied to the control loop in the process control, the PID calculation result becomes a large value and the control output signal MV is limited by the output limiter, but the above-described integral calculation is continued. As a result, the PID calculation result becomes even larger, and even if the control deviation decreases, the PID calculation result does not easily fall within the output limiter limit values (upper limit value and lower limit value), and the control input signal P
A so-called reset windup phenomenon in which the excessive amount of V becomes large is likely to occur.

Therefore, when the PID calculation result exceeds the limit value of the output limiter, the above process control device 7 stops or limits the integral calculation to suppress the output increase or decrease due to the integration operation and reset. An anti-reset windup (ARW) function is provided to prevent the windup phenomenon. The PID calculation methods in the process controller 7 are roughly classified into position type and velocity type.

In the position type PID calculation, each of proportional P, integral I, and derivative D is calculated with respect to the control deviation, and these are added to directly obtain the control output signal MV as the PID calculation result. In order to prevent the wind-up phenomenon, it is general that the integral operation is limited or stopped when the absolute value of the control deviation is larger than a certain value. On the other hand, the velocity type PID calculation is performed by a change amount ΔP proportional to the control deviation, a change amount ΔI of the integral, and a change amount ΔD of the derivative.
Each of the above calculations is performed, and the PID change calculation result obtained by adding these is sequentially added to the previous control output signal MV to obtain the control output signal MV at that time.

In order to prevent the reset windup phenomenon in this speed type PID calculation, when the addition result of the PID change amount calculation result and the previous control output signal MV exceeds the limit value of the output limiter, the addition result is calculated. This is achieved by performing addition result correction processing that replaces the limit value of the output limiter. By the way, since the above-mentioned anti-reset windup function in the position type PID calculation limits or stops the integral calculation depending on the magnitude of the control deviation, it is difficult to perform manual / automatic bumpless switching of the process control device 7. Therefore, even in the position type PID control device 7, the integral calculation correction process equivalent to the addition result correction process in the velocity type, that is, when the PID calculation result exceeds the limit value of the output limiter, the integration calculation result is corrected and PI
Many process control devices are designed so that the D calculation result matches the limit value of the output limiter.

FIG. 17 is a block diagram of a conventional process control device 7 having a position type PID calculation function.
It should be noted that unless otherwise specified, the operation will be described as the reverse operation including the embodiments described later. In FIG. 17, the deviation calculator 11 obtains the control deviation En at the time n from the control input signal PVn at the time n and the control target value SVn and outputs it to the proportional calculator 13, the derivative calculator 15, and the integral change calculator 17. The proportional calculation unit 13 obtains the proportional calculation result Pn, the differential calculation unit 15 obtains the differential calculation result Dn, the integral change calculation unit 17 obtains the integral change amount calculation result ΔIn at the time point n, and the addition unit 19 obtains the proportional calculation result Pn. And the differential operation result Dn are added to obtain the PD operation result (PDn: proportional + derivative) at the time point n and the result is added to the adder 21.

The integral change amount calculation result ΔIn from the integral change calculation unit 17 is added to the addition unit 23 via the switch SW1, and in the addition unit 23, n-1 which will be described later and is stored in the storage unit (Z ^-1 ) 25. Addition unit 21 by adding the result stored at the time point
In addition, the PID calculation result (PIDn: proportional + integral + derivative) at time n is added to the output limiter 27 from the adder 21. These integral change calculator 17, switch SW1,
In the output limiter 27 in which the adder 23 and the storage 25 form the integral calculator 29, the PID calculation result PID
When n exceeds the upper limit value MH and the lower limit value ML of the output limiter set in advance, the upper limit value MH and the lower limit value ML are subtracted as the control output signal MVn at the time point n by the subtraction unit 3.
1 and output to the control target omitted in FIG. 17,
When PID> MH and PID <ML, a logic signal that changes to “1” is output to the OR gate 33.

In the subtraction section 31, n from the output limiter 27 is output.
PD control result P at time n from control output signal MVn at time
Dn is subtracted and added to the switch SW2, and the storage unit 25 delay-stores the subtraction result from the subtraction unit 31 or the addition result from the addition unit 23 for one time point via the switch SW2, and outputs it to the addition unit 23. PID calculation result PIDn is the upper limit value MH
And the lower limit value ML is exceeded, the switches SW1 and SW are switched by the integration correction signal S output from the OR gate 33.
2 is controlled to be switched from the "0" side terminal to the "1" side terminal. These subtraction unit 31, OR gate 33, switch S
An integral calculation correction unit 35 is formed at W2.

In such a position type process control device 7, if the PID calculation result PIDn falls between the upper limit value MH and the lower limit value ML of the output limiter 29 (ML≤PID
n ≦ MH), the integration correction signal S from the OR gate 33 becomes “0”, and SW1 and SW2 of the integration calculation correction section 35 are switched to the “0” side terminals, so In = (In−1) + Δ In PIDn = Pn + In + Dn (= PDn + In) MVn = PIDn, and the PID calculation result PIDn is output as it is as the control output signal MVn.

However, when the PID calculation result PIDn exceeds either the upper limit value MH or the lower limit value ML (ML> PI).
Dn or MH <PIDn), the integration correction signal S changes to “1”, SW1 and SW2 are switched to “1” side terminals, and In = (In−1) = MVn−PDn (= MH−PDn or = ML-PDn) PIDn = PDn + In = MVn (= MH or = ML), the integral calculation result In is corrected, and the PID calculation result PIDn is the upper limit value MH or the lower limit value M of the output limiter 29.
It becomes equal to L and is output as the control output signal MVn.

FIG. 18 is a block diagram of a conventional process control device 7 having a speed type PID calculation function. FIG.
In the deviation calculation unit 37, the control input signal PV at time n
The control deviation En at the time point n is obtained from n and the control target value SVn and output to the proportional change calculation unit 39, the differential change calculation unit 41 and the integral change calculation unit 43, and the proportional change calculation unit 39 calculates the proportional change calculation result ΔPn. The differential change calculation unit 41 obtains the differential change calculation result ΔDn, the integral change calculation unit 43 obtains the integral change calculation result ΔIn at the time n, and the addition unit 45 calculates the proportional change calculation result ΔPn and the differential change calculation. Result ΔDn
Is added to obtain the PD change amount calculation result (ΔPDn: proportional + derivative) at the time point n, and the result is added to the addition unit 47.

In the adder 47, the PD change amount calculation result Δ
PDn and the integral change amount calculation result ΔIn are added, and the addition unit 4
In addition to 9, the addition unit 49 calculates the ΔPID change amount ΔP
IDn and n-to be described later stored in the storage unit (Z ^-1 ) 51.
The storage result at one point is added, and the obtained PID calculation result PIDn is added to the output limiter 53. These adders 4
9 and the storage unit 51 form a change addition unit 55. In the output limiter 53, the PID calculation result PID
When n does not exceed the upper limit value MH or the lower limit value ML, the P
The ID calculation result PIDn is output as a control output signal MVn to the storage unit 51 or a control target (not shown). When the control output signal MVn is exceeded, the upper limit value MH and the lower limit value ML are output as the control output signal MVn at the time point n, and the storage unit 51 controls the control output signal MVn. The output signal MVn is stored.

In such a speed type process control device 7, if the PID calculation result PIDn falls between the upper limit value MH and the lower limit value ML of the output limiter 53 (ML≤PID
n ≦ MH), the PID calculation result PIDn is output as it is as the control output signal MVn. However, when the PID calculation result PIDn exceeds either the upper limit value MH or the lower limit value ML (ML> PIDn or MH <PIDn), MVn = MH (or = ML) MVn-1 = MVn (= MH or = ML) As described above, the upper limit value MH or the lower limit value ML is output as the control output signal MVn, and the control output signal MVn-1 one time before is not the PID calculation result PIDn but the upper limit value MH or the lower limit value ML of the output limiter 53. Will be corrected to.

The feedforward section 59 shown by the broken lines in FIGS. 17 and 18 is a section for performing a correction calculation for the control target value SVn. In such a conventional process control device 7, a normal operation change such as the control target value SV is performed.
When n is changed, as shown in the control response waveform diagrams of FIGS. 19A and 19B, when the PID calculation result PIDn exceeds the upper limit value MH of the output limiter, the control output signal MV
n is limited to the upper limit value MH, and the position PI
In D, the integral calculation result In is corrected, and in the speed type PID, the control output signal MVn-1 one time before is corrected to correct PI.
The D calculation result PIDn is made to match the upper limit value MH.

Therefore, when the control input signal PVn approaches the control target value SVn, the PID calculation result PIDn (control output signal MVn) quickly departs from the upper limit value MH as shown by the solid line to suppress the increase of the control input signal PVn. Therefore, the reset windup phenomenon is suppressed as compared with the case where the correction process is not performed as indicated by the broken line in the figure, and the overshoot amount with respect to the control target value SVn can be suppressed for both the position type and the velocity type PID. .

[0018]

However, in the conventional process control device 7 described above, an abnormal PID constant, such as 100 times the normal PID constant, is set due to an erroneous setting, and the control loop becomes unstable, or the control loop becomes continuous. When noise is mixed into the control input signal PV line and the PID calculation result vibrates and periodically exceeds the limit value of the output limiters 27, 53, the PID calculation result becomes the limit value each time the limit value is exceeded. The integral result is corrected so as to match, and the proportional output and the integral output (especially proportional output portion) corresponding to the control deviation En are lost each time the integral result is corrected. Therefore, the control output signal MV cannot converge to an original proper value with respect to the control target value SV, which may adversely affect the control loop and, in the worst case, may result in an uncontrollable state.

As shown in FIGS. 20 (A) and 20 (B), impulse noise is mixed in the control input signal PV line in the stable control state, and PID is generated at the trailing edge of the noise.
If the calculation result exceeds the upper limit value MH of the output limiter and the PID calculation result PIDn is made to match the upper limit value MH by the correction process, if the noise rises and disappears at the next time point, only the amount corrected by the correction process first. Extra PI
A pullback phenomenon occurs in which the D calculation result PIDn is pulled back, and as shown by the broken line in the figure, there is a drawback that it takes time until the control becomes stable again compared to the case of the solid line without correction processing. 21 (A) and 21 (B) show the adverse effect of the pullback phenomenon caused by the impulse noise in the direction opposite to that in FIG.

This pullback phenomenon may also occur at the time of abnormalities such as disconnection of the control input signal PV line, contact failure, short circuit, and the like, and at the time of repair thereof. These are problems when the PID calculation result exceeds the limit values of the output limiters 27 and 53 in the position type process control device 7, but even when the output change rate limiter is added, 1
If the values obtained by adding or subtracting the allowable signal change rate to the control output signal MVn-1 before the time point are regarded as the upper limit value MH and the lower limit value ML of the output limiter, respectively, a similar problem occurs. Further, the defect of the integral calculation correction process in the position type process control device 7 occurs in the same manner in the addition result correction process of the velocity type PID.

In response to such a problem, however, in the position type process control device 7, the correction operation of the integral calculation is not continuously performed, but is intermittently performed at regular time intervals.
Although there is a method in which the pullback phenomenon is mitigated by gradually performing it over a certain period of time instead of instantaneously, it is difficult to completely solve the problem of the pullback phenomenon. Further, in the speed type process control device 7, when the addition result exceeds the limit value of the output limiter 53, the sign of the control deviation En and the PID calculation result are in the opposite directions except when the limit value of the output limiter 53 is exceeded. , There is one in which the integrated value is held and the addition result is simply limited without being modified (see FIG. 19).

However, with such a configuration, since the correction of the integral value during normal operation is also eliminated, the reset windup prevention effect for the change of the control target value SV is inferior to that extent, and the overshoot amount of the control input signal PVn is slightly. It has the drawback of becoming larger. The present inventor has found that the PID calculation result P
The present invention has been completed by focusing on the relationship between the IDn and the upper limit value MH or the lower limit value ML, and the rise or fall of the control input signal PVn, that is, the pullback described above may be generated or suppressed depending on the changing direction. The present invention has been made in order to solve such a conventional drawback, and can suppress the reset wind-up phenomenon with respect to the change of the target value, and can set the PID constant, the continuous noise and the impulse type. An object of the present invention is to provide a process control device that suppresses the control output signal from being pulled back due to them even if the control loop becomes unstable due to the mixing of noise, and that adverse effects on control are minimized.

[0023]

In order to solve such a problem, the first configuration according to the present invention is to provide at least a position so as to eliminate a control deviation obtained from a control target value and a control input signal from a controlled object. Control operation unit that performs proportional proportional and integral operations of the form and adds them to obtain the operation result, and an output that outputs a control output signal that limits the operation result by the set upper and lower limit values to the control target. In addition to the limiter and the integral calculation correction unit that corrects the integral calculation value so that the calculation result matches the upper limit value or the lower limit value when the calculation result is limited to the upper limit value or the lower limit value, the integral calculation correction unit It has a judgment part. The integration calculation correction judging unit judges whether the change of the control input signal is normal or abnormal from the direction of change of the control input signal and the direction in which the calculation result exceeds the upper limit value and the lower limit value. When the correction of the value is prohibited and the calculation result returns between the upper limit value and the lower limit value, or the control input signal at that time point becomes the control input signal level one time point before the time point when the correction of the integral calculation value is prohibited. When returning, the prohibition of the correction of the integral calculation value is released.

The second configuration according to the present invention performs at least a velocity-type proportional change calculation and an integral change calculation so as to eliminate the control deviation obtained from the control target value and the control input signal from the control target. And a control operation unit that obtains the operation result of the time point by adding them to the operation result of the time point before,
An output limiter that outputs a control output signal whose operation result is limited by the set upper limit value and lower limit value to the above-mentioned controlled object, and one time before the operation result is added when the operation result is limited to the upper limit value or the lower limit value. In addition to the addition result correction unit that replaces the calculation result of (1) with the upper limit value or the lower limit value and corrects the addition result, the addition result correction determination unit is included. The addition result correction determination unit determines whether the change in the control input signal is normal or abnormal based on the direction of change of the control input signal and the direction in which the calculation result exceeds the upper limit value and the lower limit value. Addition is made when correction is prohibited and returns from the upper limit value to the lower limit value, or when the control input signal at that time point returns to the control input signal level one time point before the time point when the correction of the integral calculation value is prohibited. This is to remove the prohibition of result modification. In the above-described first and second configurations, the smaller one of the value obtained by adding the allowable signal change width to the control output signal value one time before and the upper limit value is set as the actual upper limit value.
An output change rate that limits the rate of change of the control output signal by setting the larger of the value obtained by subtracting the allowable signal change width from the control output signal before the time point and the lower limit value as the actual lower limit value in the output limiter. It can be configured to provide a limiter.

[0025]

According to the first configuration of the present invention having such means, when the position type PID calculation result exceeds the limit value of the output limiter, the integral calculation correction determination section determines whether the control input signal PV is normal or abnormal. Judgment is made from the direction in which the limit value of the output limiter has been exceeded and the direction in which the control input signal PV has changed, and the integral calculation correction process is executed or prohibited. For example, if the control target value SV is changed to a positive direction with an appropriate PID constant and the direction of change of the control input signal PV when the PID calculation result exceeds the upper limit value of the output limiter is non-negative (zero or positive). The integration calculation correction determining unit determines that the operation is normal and executes the integration calculation correction process, and the PID calculation result is returned to the limit value of the output limiter, so that the reset windup phenomenon is suppressed.

Further, the control input signal P when the PID calculation result exceeds the upper limit value of the output limiter due to the inclusion of noise or the like.
If the direction of change of V is negative, the integral calculation correction determination unit determines that it is abnormal, prohibits the integral calculation correction process, and the PID calculation result is not pulled back with respect to the abnormal change of the control input signal PV. Further, the integral correction determination unit holds the normal control input signal PV before the temporary point when it is determined to be abnormal, and P
When the ID calculation result naturally returns between the upper limit value and the lower limit value, and when the control input signal PV returns to this normal holding value, the inhibition of the integral correction process is released, so the target value change response Even if the integral correction process is temporarily prohibited due to noise, if the influence of the noise disappears, the integral correction process is re-executed to prevent the reset windup phenomenon.

On the other hand, when the PID calculation result exceeds the lower limit value of the output limiter, the integral calculation correction judging unit judges that the change is normal if the change of the control input signal PV is zero or in the negative direction, and in the positive direction. If there is, it is determined to be abnormal and the same integral calculation correction process is performed or the correction process is prohibited. Further, in the second configuration, the previous control output signal MVn-1 and PID
When the addition result of the variation calculation result ΔPIDn exceeds the limit value of the output limiter, the addition result correction determination unit determines whether the control input signal PV is normal or abnormal and the direction in which the limit value of the output limiter is exceeded and the control input signal PV. Judgment from the changing direction of, and when it is judged to be normal, execute the addition result correction processing,
When it is determined to be abnormal, those processes are prohibited. Further, in the configuration in which the output change rate limiter is provided in the first and second configurations, the allowable signal change width is added to and subtracted from the control output signal value one time point before the time point, and
The actual upper and lower limits are set in the output limiter from the addition and subtraction results and the upper and lower limits.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in the conventional example are designated by the same reference numerals. FIG. 1 is a first configuration according to the present invention, which is a position type PI.
It is a schematic block diagram which shows the process control apparatus which has a D calculation function. In FIG. 1, a control calculation unit 61 includes a position-type proportional calculation, a differential calculation and an integral calculation so as to eliminate a control deviation obtained from a control target value SV and a control input signal PV from a control target (not shown in FIG. 1). And add them to obtain the PID calculation result and output limiter (see FIG. 17)
The output limiter 27 is a PID.
Control output signal M in which the calculation result is limited by the upper limit value or the lower limit value
Vn is output to the controlled object.

The integral calculation correction section (see FIG. 17) 35 is
When the ID calculation result is limited to the upper limit value or the lower limit value, the integral calculation value of the control calculation unit 61 is corrected so that the PID calculation result matches the upper limit value or the lower limit value. The integral calculation correction determination unit 63 determines the change direction of the control input signal PV and P
Whether the change in the control input signal PV is normal or abnormal is determined from the direction in which the ID calculation result exceeds the upper limit value or the lower limit value, and when it is determined that the change is abnormal, the integral calculation correction unit 35 prohibits the correction of the integral calculation value. , When the PID calculation result returns between the upper limit value and the lower limit value, or when the control input signal PV at that time point returns to the control input signal PV level one time point before the time when the correction of the integral calculation value is prohibited. The prohibition on correction of the integral calculation value is released. The control calculation unit 61 can be formed to perform at least proportional calculation and integral calculation, and the output change rate limiter 65 will be described later.

As a second configuration according to the present invention, in order to configure a process control device having a speed type PID calculation function, in FIG. 1, the control calculation section 61 calculates at least a speed type proportional change and integral change. The minute calculation is performed, the output limiter 27 becomes the output limiter 53 of FIG. 18, the integral calculation correction unit 35 becomes the addition result correction unit 57, and the integration calculation correction determination unit 63 is changed to the addition result correction determination unit 67. So, the general structure does not change. This addition result correction determination unit 6
Reference numeral 7 indicates the control input signal P from the changing direction of the control input signal PV and the direction in which the PID calculation result exceeds the upper limit value or the lower limit value.
When the change in V is determined to be normal or abnormal, the addition result correction is prohibited when it is determined to be abnormal, and when the PID calculation result returns between the upper limit value and the lower limit value, or the control input signal PV at that time point is changed. When the control input signal PV level returns one time before the time when the correction of the integral calculation value is prohibited, the addition result correction prohibition is released.

The prohibition conditions for the correction processing in the integral calculation correction determination section 63 and the addition result correction determination section 67 are summarized as follows. Prohibited condition PIDn> MH and PVn <PVn-
1 Prohibited conditions PIDn <ML and PVn> PVn-
1 (PVn-1 is a control input signal at time n-1) Then, if the control input signal PVn-1 one time before the time when the prohibition condition is satisfied is the hold input signal value PH,
When the prohibition condition is satisfied, PH = PVn-1.

If the control input signal PVn at that time point is an abnormal value that moves in the opposite direction from the original change direction due to noise or the like, the hold input signal value PH is normal one time point before the time when the prohibition condition is satisfied. Since the control input signal value is different, the PID calculation result PIDn naturally causes the output limit values MH and ML of the output limiters 27 and 53 to cancel the correction processing prohibition.
It may be performed when the control input signal PV returns to a normal value, that is, the hold input signal value PH level. In addition, the integral calculation correction determination unit 6
3 and the prohibition cancellation conditions in the addition result correction determination unit 67 are summarized as follows.

Release condition ML ≦ PIDn ≦ MH (common with prohibition condition) Release condition PVn ≧ PH (when prohibition condition) PVn ≦ PH (when prohibition condition) Next, the above-mentioned first and second configurations A detailed configuration of the process control device will be described. FIG. 2 is a block diagram showing a first configuration (position type process control device) according to the present invention, but other configurations except the integration calculation correction determination unit 63 and the switch SW4, that is, the deviation calculation unit 11, the proportional calculation. Unit 13, differential calculation unit 15, integral change calculation unit 17, addition unit 19, addition units 21 and 23, storage unit 25, output limiter 27, integration calculation unit 29, subtraction unit 31, OR gate 3.
3, integral calculation correction unit 35 and switches SW1 and SW2
17 is almost the same as that of FIG. 17 and is characterized by the integral calculation correction determining unit 63. Illustration of the feedforward unit 59 is omitted.

The integration calculation correction determination unit 63 is provided with the OR gate 3
Integration correction signal S from 3, the upper limit value MH and the lower limit value ML
It is determined whether or not the above-described prohibition condition and prohibition cancellation condition are present based on the logic signal that changes to "1" when the limit is reached by the control input signal PVn and prohibits or cancels the operation of the integral calculation correction unit 35. . In addition, switch SW
4 will be described later. FIG. 3 is a block diagram showing in detail the integral operation correction determination unit 63 of FIG. 2 and its periphery. In FIG. 3, the control input signal PVn is stored in the storage unit 69,
The storage unit 69 is connected to the subtraction unit 71 and the flag reset unit 73, stores the control input signal for one time point, and stores the control input signal PVn-1 one time point before the time point.
5 and the subtraction unit 71.

The storage unit 75 has a flag holding unit 77 described later.
The control input signal PVn-1 from the storage unit 69 is held and the hold signal PH is output to the flag reset unit 73 when the integration correction inhibition signal T from 0 changes from "0" to "1". The subtraction unit 71 outputs the input signal change amount DP obtained by subtracting the control input signal PVn from the control input signal PVn−1 from the storage unit 69 to the flag setting unit 79. The flag setting unit 79 has the input signal change amount DP and the upper limit value M input to the OR gate 33.
A logic signal that changes to "1" when limited by H and the lower limit value ML, and the flag state of the flag holding unit 77 are taken in, the above-described prohibition condition or determination is executed, and when the prohibition condition is satisfied, the flag holding unit The flag of 77 is set to "1", and when the prohibition condition is satisfied, it is set to "2",
In other cases, it has a function of setting (clearing) to "0".

The flag holding unit 77 sets the integration correction prohibition signal T to "1" when the flag is "1" or "2", and sets it to "0" when the flag is "0" to one input of the AND gate 81. It has a function of adding to the side by negative logic and adding to the storage unit 75 described above. The flag reset unit 73 has a hold signal PH and a control input signal PV from the storage unit 75.
n, the integration correction signal S from the OR gate 33 and the flag state of the flag holding unit 77 are taken in, the above-described cancellation conditions and judgment are executed, and when any of the cancellation conditions is satisfied, the flag of the flag holding unit 77 is set to It has the function of clearing to "0".

The AND gate 81 is an O gate in the conventional configuration.
It is inserted between the R gate 33 and the switch SW2,
The integration correction signal S from the OR gate 33 is added to the other input side, and the output side is added to the switch SW2. When the integration correction prohibition signal T from the flag holding unit 77 is "1", the integration correction signal is It is an open / close gate that prohibits the application of S to the switch SW2 and adds it when the integration correction prohibition signal T is "0". That is, the integral calculation correction process is prohibited while the integral correction prohibition condition is satisfied. The switch SW3 in FIG. 2 and FIG. 3 is a selection switch for continuing the integration calculation during the integration correction prohibition period as usual, or stopping the integration calculation and holding it at the integration value before prohibition.
Normally, it is desirable to switch the control calculation unit 61 depending on the sign of the control deviation En and the magnitude of the absolute value, but the description thereof will be omitted.

The operation timing of the integral calculation correction determining section 63 will be briefly described as follows, for example, as shown in FIGS. When the PID calculation result PIDn exceeds the upper limit value MH due to the change of the control target value SVn, the PID
The calculation result PIDn (control output signal MVn) is the upper limit value MH.
However, if the pulse noise is generated on the way and the control input signal PVn decreases, the flag setting unit 79 determines that the prohibition condition is satisfied, and the flag holding unit 77 sets the flag “1”. , The control input signal PVn-1 one time before is held in the storage unit 75,
During the period in which the flag is set, the integration correction inhibiting signal T from the flag holding unit 77 becomes "1", the AND gate is closed, and the integration calculation correcting process by the switch SW2 is prohibited.

Then, the control input signal PVn increases to 1
When the control input signal PVn-1 level before the time point is reached, the flag reset unit 73 determines the release condition, clears the flag of the flag holding unit 77, and the integral correction prohibiting signal T from the flag holding unit 77 is "0". Then the AND gate is opened and the integration correction signal S restarts the integration calculation correction process. Although not shown, the process control device according to the first configuration described above is generally configured by a CPU, a ROM storing an operation program of the CPU, and a microcomputer mainly including an interface I / O, and the process control device is fixed. It is repeatedly executed at intervals (sampling period).

5 and 6 are flow charts for explaining the operation of the process control device 7 according to the first configuration.
For the sake of convenience, the figures are divided into two figures, but both figures show a series of processing operations. When the program is started, in step 500, the proportional calculation result Pn and the differential calculation result D at time n
n, PD calculation result PDn, integral change calculation result ΔIn,
PI for obtaining the integral calculation result In and the PID calculation result PIDn
D calculation processing is performed, and in step 501, the flag holding unit 7
The content of the flag in 7 is determined, and if the flag is "0", the process proceeds to step 506, and if it is other than "0", the process proceeds to step 502 or 504 to compare the control input signal PVn with the hold input signal value PH. .

When the flag is determined to be "1" in step 501, the process proceeds to step 502 to determine whether PVn≥PH. If this step 502 is NO, step 50
6, the flag is cleared to "0" in step 503 if YES, and the process proceeds to step 506. Step 5
If the flag is judged to be "2" at 01, step 504
Then, it is judged whether PVn ≦ PH or not, and this step 5
If 04 is NO, the routine proceeds to step 506, and if YES, the flag is cleared to "0" at step 505 and the routine proceeds to step 506. These are flag reset processing (correction prohibition state cancellation processing) when it is determined that the control input signal PVn has returned to the normal value.

Subsequently, at step 506, the input signal change amount DP is calculated from the difference between the control input signal PVn-1 one time before and the control input signal PVn at that time, and the routine proceeds to step 507. In step 507, the PID calculation result PIDn is compared with the lower limit value ML or the upper limit value MH. If the PID calculation result PIDn is between the lower limit value ML and the upper limit value MH (within the limit range), ML ≦ PIDn ≦ MH. For example, in step 508, MVn is set to PIDn and step 51 in FIG.
Move to 1.

When it is determined that MH <PIDn in step 507, MVn = MH is set in step 509 and the process proceeds to step 512 in FIG. 6, where ML> PIDn in step 507.
When it is determined that MVn = ML in step 510, the process proceeds to step 520 in FIG. These are output limiter processes. Next, in step 508 of FIG. 5, MVn is set to PI.
When it is set to Dn, the flag is forcibly cleared to "0" in step 511 of FIG. 6 and the process proceeds to step 517. In step 517, the previous integration value In-1 is changed to the current integration value In.
And the previous control input signal PVn-1 is updated with the current control input signal PVn and the process ends.

In step 509 of FIG. 5, MVn = M
When it is set to H, the routine proceeds to step 512 in FIG. 6 and it is determined whether the flag is “1”. If NO, the prohibition processing is continued, the routine proceeds to step 517 via step 516, and the previous integrated value In -1 and the previous control input signal PVn-1 are updated with the current integrated value In and the control input signal PVn, and the processing is ended. If the operation of stopping the integral calculation while the correction process is prohibited and holding the integral value is selected, the integral calculation result In is set as the previous integral value In-1 and the integral value is not updated in step 516. If YES in step 512, it is determined in step 513 whether the input signal change amount DP is larger than 0, that is, the sign of the input signal change amount DP is determined, and the input signal change amount DP is positive (the change direction of PVn is negative). ), If step 513 is YES, step 514 is executed to prohibit the integral correction process.
The flag content is set to "1".

In the following step 515, the hold input signal value PH of the storage unit 75 is updated with the previous input signal PVn-1, and the process proceeds to step 517 via step 516. In step 517, the previous integrated value In-1 and the previous control input are input. The signal PVn-1 is updated with the current integrated value In and the control input signal PVn, and the process ends. Also in this case, when the operation of stopping the integral calculation while the correction process is prohibited and holding the integral value is selected, the integral calculation result In is set as the previous integral value In−1 and the integral value is not updated.

If the sign of the input signal change amount DP is not positive (the change direction of PVn is zero or positive), step 513 is NO.
In the case of, the flag is cleared to "0" in step 518, the integral calculation correction process is executed in step 519, and the current integral calculation result In is corrected as In = MVn-PDn = MH-PDn, The process proceeds to step 517 and ends. Further, when MVn = ML is set in step 510 of FIG. 5, it is determined in step 520 of FIG. 6 whether or not the flag is “2”. If NO, the prohibition process is continued, and the process proceeds to step 517 via step 524. Move, step 517
Then, the previous integrated value In-1 and the previous control input signal PVn-1 are updated with the current integrated value In and the control input signal PVn, and the processing is ended.

Also in this case, if the operation of stopping the integral calculation while the correction process is prohibited and holding the integral value is selected, the integral calculation result In is set as the previous integral value In-1 and the integral value is not updated. If YES in step 520, it is determined in step 521 whether the input signal change amount DP is smaller than 0 (negative or not), and the input signal change amount DP is negative (PV
If the changing direction of n is positive) and step 521 is YES, the flag content is set to "2" in step 522 to prohibit the integration correction process, and the hold input signal value PH of the storage unit 75 is previously input in step 523. The signal PVn-1 is updated, and the process proceeds to step 517 via step 524, and the previous integrated value In-1 and the previous control input signal PVn-1 are similarly updated and the process ends.

Also in this case, when the operation of stopping the integral calculation while the correction process is prohibited and holding the integral value is selected, the integral calculation result In is set as the previous integral value In-1 and the integral value is not updated. When the sign of the input signal change amount DP is positive and step 521 is NO, the flag is cleared to "0" in step 518, the integral calculation correction process is executed in step 519, and the current integral calculation result In is set to In. = MVn-PDn = ML-PDn, the process proceeds to step 517, and the process ends similarly.

As described above, since the process control device 7 of the first configuration according to the present invention is provided with the integral calculation correction determining section 63 for prohibiting or canceling the operation of the integral calculation correcting section 35 in the position type PID calculation, When the control target value SVn is changed and the PID calculation result PIDn exceeds the upper limit value MH of the output limiter 27, the control output signal MVn is limited to the upper limit value MH, and the integral calculation result In is changed from the upper limit value MH to the PD calculation result. Since the correction process for correcting PDn to a value obtained by subtraction is executed to match the PID calculation result PIDn with the upper limit value MH, the control input signal PVn changes to the control target value SVn.
The control output signal MVn quickly departs from the upper limit value MH, and works to suppress the increase of the control input signal PVn.
The reset windup phenomenon is suppressed and the control target value S
The overshoot amount with respect to Vn is improved.

Further, the PID calculation result PIDn may vibrate and periodically exceed the limit value MH or ML due to instability of the control loop due to an abnormal PID constant setting or continuous noise mixed in the control input signal PVn. In such a case, impulse-like noise is mixed into the control input signal PVn and the PID calculation result PIDn is the limit value M when the noise rises.
Even if the noise disappears after H or ML is exceeded, the integral calculation correction determination unit 63 prohibits the correction processing under the condition that the pullback phenomenon occurs, and the abnormal PID
The adverse effects associated with constant, continuous noise and impulse-like noise can be minimized. FIG. 7 is a block diagram showing in detail the second configuration (speed type process control device) according to the present invention.

In this configuration, the addition result correction unit 57,
Addition result correction determination unit 67 and switches SW4 to SW6
Other than the above, other configurations, that is, the deviation calculator 37, the proportional change calculator 39, the differential change calculator 41, the integral change calculator 43,
Adders 45, 47, 49, storage 51, output limiter 5
3, the change amount adding unit 55 is shown in FIG.
The addition result correction determination unit 67 is similar to
The configuration is substantially the same as that of the integral operation correction determination unit 63 having the above configuration. Illustration of the feedforward unit 59 is omitted. In FIG. 7, the integral change calculation unit 43 is connected to the addition unit 47 via the switch SW4, and the addition unit 47 is further connected to the addition unit 49. The addition unit 49 has a storage unit (Z ⁻¹ ) 51.
The PID calculation result (PIDn: proportional + integral + derivative) at the n-th time is added to the stored result at the (n-1) -th time stored in the step (3) and output to the output limiter 53.

The output limiter 53 outputs the PID calculation result PI.
When Dn exceeds the upper limit value MH and the lower limit value ML,
The upper limit value MH and the lower limit value ML are used as the control output signal MVn at the time point n, which is not shown in the figure, or the switch SW5.
And outputs to the OR gate 33 a logic signal that changes to “1” when being limited by the upper limit value MH or the lower limit value ML. The storage unit 51 delay-stores the control output signal MVn from the output limiter 53 or the addition result from the addition unit 49 for one time point via the switch SW5, and outputs it to the addition unit 49. The addition result correction unit 57 is formed by this switch SW5.

Then, the addition result correction judging section 67 has the storage sections 69 and 75, the subtracting section 71, the flag setting section 79, the flag resetting section 73, the flag holding section 77 and the OR of FIG. Although it is formed of the gate 33, the addition result correction prohibiting signal T is directly applied to the switches SW5 and SW6 from the flag holding unit 77 without passing through the AND gate 81 like the first structure. It should be noted that SW6 in FIG. 7 switches the operation of the integral calculation during the correction prohibition period, like SW3 in FIG.

Unlike the position type process control device 7, such a speed type process control device 7 takes the purpose of adding only the control output signal MVn-1 one time before from the output of the output limiter 53. Although the addition result correction process is naturally performed without providing the correction unit 57, the addition result correction unit 57 needs to be independent as shown in FIG. 7 in order to prohibit or allow the correction process under a certain condition. There is. The speed type process control device 7 according to the second configuration as described above is also generally configured by a microcomputer, and operates as shown in the flowcharts of FIGS. 8 and 9. For the sake of convenience, the illustration is divided into two views and is similar to FIGS. 5 and 6.

The flow chart of the process controller 7 according to the second configuration is shown in FIG. 5 except that the PID calculation is speed type and the integral calculation correction process is addition result correction process.
And, since it is similar to FIG. 6, different steps will be described. That is, when the program is started, the proportional change calculation result ΔPn, the differential change calculation result ΔDn, the integral change calculation result ΔIn, the PID change calculation result at the time point n at step 500 as shown in FIGS. 8 and 9. The PID calculation process for obtaining ΔPIDn and the PID calculation result PIDn is performed, and the process proceeds to step 501, and the subsequent steps 501 to 5
The processes of 15, step 518, and steps 520 to 523 are the same as those in FIGS. 5 and 6.

In FIG. 9, in step 511 and step 518, the flag of the flag holding unit 77 is set to "0" and P
ID calculation result PIDn is within the output limit range or P
The ID calculation result PIDn is the output limit value MH or ML.
If it exceeds the limit but the correction prohibition condition is not satisfied, step 52
In step 5 or 529, the previous control output signal MVn-1 is updated with the current control output signal MVn. On the other hand, when the flag is set to "1" or "2" in step 514 or step 522 and the correction prohibition condition is satisfied, step 5
26 or step 530, the previous control output signal MVn-1
Is updated with the current PID calculation result PIDn.

Then, when the operation of stopping the integral calculation while the correction process is prohibited and holding the integral value is selected,
In step 527 or step 531, the previous control output signal MVn-1 is updated with a value obtained by subtracting the integral change amount calculation result ΔIn from the current PID calculation result PIDn. Also in the speed type process control device 7 according to the second configuration as described above, the addition result correction determination unit 6 that prohibits or cancels the addition result correction operation with respect to the addition result correction unit 57.
7 is provided, when the control target value SVn is changed and the PID calculation result PIDn exceeds the upper limit value MH of the output limiter 27, the control output signal MVn is limited to the upper limit value MH and the control output signal one time before is output. Since the correction process of MVn-1 is executed and the PID calculation result PIDn matches the upper limit value MH, when the control input signal PVn approaches the control target value SVn, the control output signal MVn quickly leaves the upper limit value MH, and the control input It works to suppress the increase of the signal PVn, suppresses the reset windup phenomenon, and suppresses the control target value SV.
The overshoot amount for n can be suppressed.

Further, even if an abnormal PID constant is set, continuous noise, or impulsive noise is mixed, correction processing is prohibited under the condition that a pullback phenomenon occurs by the addition result correction determination unit 67. And those abnormal PIs
It is possible to minimize the adverse effects of the D constant, continuous noise, and impulse noise. Although each of the first and second configurations described above has the output limiters 27 and 53, in the present invention, the output limiters 27 and 53 are provided.
In addition to this, a configuration in which an output change rate limiter 65 is added is also possible.

FIG. 10 shows the output limiters 27 and 5 described above.
3 is a block diagram showing a configuration in which an output change rate limiter 65 is added to FIG. In the figure, the control output signal MVn from the output limiters 27 and 53 is stored in the storage unit 83, and the control output signal MVn-1 one time before is output to the addition unit 85 and the subtraction unit 87, and the addition unit 85 outputs the control output. Signal MVn
-1 and the allowable signal change width MΔ are added to obtain the row selector 89.
In addition, the subtraction unit 87 subtracts the allowable signal change width MΔ from the control output signal MVn−1 and adds it to the high selector 91. The low selector 89 subtracts the smaller one of the addition result and the upper limit value MH from the actual upper limit value M1. Output limiter 27,
In addition to 53, in the high selector 91, the subtraction result and the lower limit value M
An output change rate limiter 65 is formed by adding the larger one of L to the output limiters 27 and 53 as the actual lower limit value M2.

That is, with respect to the upper limit value MH and the lower limit value ML set in the output limiters 27 and 53, the actual upper limit value M1 and the lower limit value M2 are as follows. M1 = MIN [MH, (MVn−1) + MΔ] M2 = MAX [ML, (MVn−1) −MΔ] where MH is the upper limit value of the output limiter set from the outside, and ML is the output limiter. Is a lower limit value of the output change rate limit width, and the code MIN (a, b) is a and b.
, Whichever is smaller, and the code MAX (a, b), whichever is larger, a or b. In this way, the output limiter 65 to which the output change rate limiter 65 is connected has the same effects as those of the above-described first and second configurations.

By the way, such an output change rate limiter 65 is used for both the position type and the velocity type output limiters 2.
It goes without saying that it is possible to carry out even with 7, 53. Next, with respect to the above-described present invention and the conventional process control device 7, FIGS. 11 to 15 show their operation simulations. As an example, each simulation was performed for a position-type measured value differential PID calculation (PID calculation in which the input of the differential calculation is a control input signal instead of a control deviation).

11 to 15, In + 0.6: Integral calculation result (bias 0.6) FLAG: Flag ("0" = 0.5, "1" =
0.6, "2" = 0.4) * Output limiter: upper limit value = 1.0, lower limit value = 0.0. FIG. 11 shows both the conventional type and the control response according to the present invention for the normal change of the control target value SV, in which the control output signal MVn is the control target value SV.
Immediately after the change of n, the upper limit value MH of the output limiter is applied and the limit is applied. However, at this time, the correction process is executed without prohibition, so that the overshoot amount of the control input signal PVn is suppressed to a small value and the conventional type and the There is no difference in invention.

FIG. 12 shows an example in which a pullback phenomenon occurs due to oscillation in the control loop system using the conventional process control device 7 and adversely affects the control.
The illustration of the flag is omitted. In FIG. 12, among the three constants of the proportional constant P, the integral time I, and the differential time D,
Since the control loop system was intentionally destabilized by setting the integral time I and the differential time D at 100 times or more of the respective appropriate values, the correction processing is performed every time the control output signal MVn vibrates and exceeds the limit value of the output limiter. As a result of the pullback, the control input signal PVn moves toward a point away from the control target value SVn.

FIG. 13 shows the present invention under the same conditions as FIG. 12, but the correction process is prohibited because the direction of change of the control input signal PVn is positive when the lower limit value ML of the control output signal MVn output limiter is exceeded. Is not pulled back,
The control input signal PVn converges toward the control target value SVn. FIG. 14 shows a control input signal PV in the conventional example.
It shows an adverse effect on the control by the continuous impulse noise mixed in n, and is an example in which positive and negative continuous impulse noise is mixed in the control input signal PVn.

In FIG. 14, since the pullback is repeatedly generated at the falling edge of the positive noise and the rising edge of the negative noise, the control output signal MVn oscillates and the control input signal PVn is separated from the control target value SVn. Moving towards. FIG. 15 shows the present invention under the same conditions as in FIG. 14, but the execution or prohibition of the correction process is determined depending on the changing direction of the control input signal PVn when the control output signal MVn exceeds the limit value of the output limiter. The pullback does not occur, and the control input signal PVn converges toward the control target value SVn.

[0066]

As described above, in the first configuration of the present invention, the position type process control device is provided with the integral calculation correction determining section for prohibiting or canceling the operation of the integral calculation correcting section. The reset windup phenomenon is suppressed with respect to the change of the value SVn, and the overshoot amount can be suppressed. Moreover, even if the control loop fluctuates significantly due to an abnormal PID constant setting, continuous noise or impulse noise, etc., the adverse effects caused by the abnormal PID constant, continuous noise and impulse noise are minimized. Can be suppressed to Further, in the second configuration according to the present invention, in the speed type process control device, since the addition result correction unit and the addition result correction determination unit for prohibiting or canceling the addition result correction operation are provided, the control target value SVn of The reset windup phenomenon is suppressed against the change, and the overshoot amount is suppressed.
The detrimental effects associated with D constants, continuous noise and impulse-like noise can likewise be minimized. Then, in the first and second configurations, the smaller or larger of the value obtained by adding and subtracting the allowable signal change width to the control output signal value one time before and the upper limit value or the lower limit value of the output limiter is the actual upper limit value or In the configuration including the output change rate limiter set to the output limiter as the lower limit value, similarly, the good suppression effect of the reset windup phenomenon and the bad effects caused by the abnormal PID constant, continuous noise, and impulse noise are good. Can be suppressed to

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing first and second configurations of a process control device of the present invention.

FIG. 2 is a block diagram showing details of a first configuration according to the process control apparatus of the present invention.

FIG. 3 is a block diagram specifically showing an integral calculation correction determination unit in FIG.

FIG. 4 is a schematic waveform diagram illustrating an operation timing of the process control device of FIG.

5 is a flowchart illustrating an operation of the process control device of FIG.

FIG. 6 is a flowchart illustrating an operation of the process control device of FIG.

FIG. 7 is a block diagram showing details of a second configuration according to the process control apparatus of the present invention.

8 is a flowchart illustrating an operation of the process control device of FIG.

9 is a flowchart illustrating an operation of the process control device of FIG.

FIG. 10 is a block diagram showing an embodiment of an output change rate limiter for the process control device of the present invention.

FIG. 11 is a response waveform diagram when simulating the operations of the present invention and the conventional process control device.

FIG. 12 is a response waveform diagram when simulating the operation of the conventional process control device.

FIG. 13 is a response waveform diagram when simulating the operation of the process control device of the present invention.

FIG. 14 is a response waveform diagram when simulating the operation of the conventional process control device.

FIG. 15 is a response waveform diagram when simulating the operation of the process control device of the present invention.

FIG. 16 is a block diagram showing a general process control loop.

FIG. 17 is a block diagram showing a conventional position type PID process control device.

FIG. 18 is a block diagram showing a conventional speed type PID process controller.

FIG. 19 is a preferable control response waveform diagram in the process control device of FIGS. 17 and 18.

20 is an undesired control response waveform diagram in the process control apparatus of FIGS. 17 and 18. FIG.

FIG. 21 is another undesirable control response waveform diagram in the process control apparatus of FIGS. 17 and 18.

[Explanation of symbols]

 1 Control Target 3 Sensor 5 Input Converter 7 Process Control Device 9 Manipulator 11 Deviation Calculator 13 Proportional Calculator 15 Differential Calculator 17 Integral Change Calculator 19, 21, 23, 45, 47, 49, 85 Adder 25, 51, 69, 75, 83 Storage unit 27, 53 Output limiter 29 Integral calculation unit 31, 71, 87 Subtraction unit 33 OR gate 35 Integral calculation correction unit 37 Deviation calculation unit 39 Proportional change calculation unit 41 Differential change calculation unit 43 Integral change Calculation unit 55 Change amount addition unit 57 Addition result correction unit 59 Feed forward unit 61 Control calculation unit 63 Integration calculation correction determination unit 65 Output change rate limiter 67 Addition result correction determination unit 73 Flag reset unit 77 Flag holding unit 79 Flag setting unit 81 AND gate 89 Low selector 91 High selector SW1 to SW6 switches

Claims (4)

[Claims] 1. A control calculation unit for performing at least a position-type proportional calculation and an integral calculation so as to eliminate a control deviation obtained from a control target value and a control input signal from a controlled object, and adding them to obtain a calculation result. And an output limiter that outputs a control output signal that limits the calculation result to the controlled object by the set upper limit value and lower limit value, and when the calculation result is limited to the upper limit value or the lower limit value. A process control device that corrects the integral calculation value so that the calculation result matches the applicable upper limit value or lower limit value, and a change direction of the control input signal and the calculation result. Determines whether the change of the control input signal is normal or abnormal from the direction in which the value exceeds the upper limit value and the lower limit value, and the integration operation is performed when it is determined to be abnormal. Of the control input signal at the time when the calculation result returns to between the upper limit value and the lower limit value, or when the control input signal at that time prohibits the correction of the integral calculation value. A process control device comprising an integration calculation correction determination unit that releases the inhibition of the correction of the integration calculation value when the signal level is reached. 2. An output change rate limiter for limiting a change rate of the control output signal, which is a smaller one of a value obtained by adding an allowable signal change width to the control output signal value one time before and the upper limit value. Is set as the actual upper limit value, and the larger one of the value obtained by subtracting the allowable signal change width from the control output signal one time before and the lower limit value is set as the actual lower limit value in the output limiter. The process control device according to claim 1, further comprising: 3. A proportional change calculation and an integral change calculation of at least a velocity type are performed so as to eliminate a control deviation obtained from a control target value and a control input signal from a control target, and the calculation results one time before are calculated. And a control calculation unit that obtains a calculation result at that time point, an output limiter that outputs a control output signal that limits the calculation result by the set upper limit limit value and lower limit limit value to the control target, and the calculation result. Is added to the upper limit value or the lower limit value, the addition result correction unit that replaces the operation result of the previous time point to be added with the corresponding upper limit value or lower limit value to correct the addition result, In a process control device having: Ordinarily or abnormally determined, prohibiting the correction of the addition result when it is determined to be abnormal, when the operation result returns between the upper limit limit value and the lower limit limit value, or the control input signal at the time is the When it returns to the control input signal level one time before the time when the correction of the integral calculation value is prohibited,
A process control device, comprising: an addition result correction determination unit that releases the prohibition of the addition result correction. 4. An output change rate limiter for limiting a change rate of the control output signal, which is a smaller one of a value obtained by adding an allowable signal change width to the control output signal value one time before and the upper limit value. Is set as the actual upper limit value, and the larger one of the value obtained by subtracting the allowable signal change width from the control output signal one time before and the lower limit value is set as the actual lower limit value in the output limiter. The process control device according to claim 3, further comprising: