JPH06111490A - Digital PLL device - Google Patents

Abstract

(57) [Summary] [Structure] 6-bit counter 1 for standard playback clock SRCK
The 9-bit counter 137 counts and measures the cycle of the output signal divided by 32 with the master clock MCK, and the measured value is a value K representing the center cycle of the reproduction clock.
_Set to ₃ . Further, this measured value is multiplied by the lock lower limit cycle ratio by the multiplier 86M to obtain a constant K ₁ representing the lower limit cycle of the lock range, and the lock upper limit cycle ratio is calculated by the multiplier 8
It is multiplied by 7M to obtain a constant K ₂ representing the upper limit cycle of the lock range. [Effect] Even if the clock rate of the input signal changes, the lock center cycle and the upper and lower limits of the lock range are automatically determined, so that the circuit configuration can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL device for digitally performing a phase synchronization operation, and more particularly to a digital PLL device for automatically generating a PLL lock range.

[0002]

2. Description of the Related Art Generally, a PLL (Phase Locked Loop) circuit is a phase locked loop circuit that follows the phase of an input signal, and is composed of an analog phase comparator, a low pass filter, a voltage controlled oscillator and the like. In recent years, there has been proposed a digital PLL circuit that digitally performs the operation inside the PLL circuit.

Here, in a normal PLL circuit, the center frequency of the reproduced clock is predetermined. In the above digital PLL circuit and the like, unless some kind of limitation is applied, the lock range becomes considerably wide, and there is a problem that pseudo lock easily occurs at the time of pulling in.
It may be necessary to set the upper and lower limits of the lock range.

Normally, one system plays at a rate of one.
Since the type is the type, the setting of the upper limit value and the lower limit value of the PLL is only one type. Even if the rate changes, if the master clock rate can be changed at the same rate, the internal circuit of the digital PLL can be unchanged. Therefore, PLL I
The above constant setting in C may be fixed.

[0005]

However, for example, DA
Like T (Digital Audio Tape Recorder),
The diameter of the rotating drum can be any diameter of 15 mm or more, and the playback rate will change accordingly.
In the LL circuit, many constants and switching control are required, which leads to an increase in the number of IC elements and pins and complexity.

The present invention has been made in view of the above circumstances, and automatically determines the lock center frequency and the upper and lower limits of the lock range for an input signal of any reproduction rate. Therefore, it is an object of the present invention to provide a digital PLL device in which the same circuit can cope with a change in the reproduction rate.

[0007]

According to the digital PLL device of the present invention, the PLL reproduction clock is generated based on the phase error data obtained by detecting the phase error between the PLL reproduction clock and the input signal using the master clock. The digital PLL device to be controlled is provided with a circuit for measuring the cycle of the reference clock having the same frequency as the reproduction clock in units of the master clock. The measured value is used as the central cycle of the PLL reproduction clock to obtain the upper limit cycle and the lower limit cycle. By setting the range between the upper limit cycle and the lower limit cycle as the lock range of the PLL, the above problem is solved.

Here, it is preferable that the upper limit period is obtained by multiplying the measured value by a constant larger than 1, and the lower limit period is obtained by multiplying the measured value by a constant smaller than 1. Further, based on an edge detection signal obtained by detecting the edge of the input signal in units of the master clock and an edge position signal indicating the position of the input edge in the master clock, the PLL reproduction clock is input. It is preferable to obtain the phase error data with respect to the signal edge in units of time shorter than the master clock cycle.

[0009]

Since the upper and lower limits of the lock range are obtained with the value obtained by measuring the period of the reference clock having the same frequency as the above-mentioned reproduced clock as the central period, an appropriate lock range is automatically set for signals of any reproduced rate. Can be set to, and the same circuit can handle changes in the playback rate.

[0010]

FIG. 1 is a block circuit diagram showing a schematic configuration of an input signal edge time measuring circuit used in a digital PLL device as an embodiment of the present invention.

In FIG. 1, an input terminal 11 is supplied with an RF (high frequency) input signal RF _in for reproducing a clock, and an input terminal 12 is supplied with a reference master clock signal MCK. The RF input signal RF _in is
The master clock signal MCK is supplied to the data input terminal D of the flip-flop 13, which is input as a clock, so that it is fetched at the timing of this master clock. The output signal from the flip-flop 13 is an exclusive OR (Ex) of the signal and a signal delayed by one master clock cycle in the flip-flop 14.
An edge is detected by being sent to the (-OR) circuit 15. The detection signal ED indicating the presence / absence of an input edge synchronized with the master clock signal MCK is taken out through the output terminal 16.

Further, the RF input signal RF from the input terminal 11
_in is an exclusive OR (Ex-OR) with the delay element 21 having a delay time sufficiently shorter than the master clock cycle T _MC.
Edge detection is performed by the circuit 22 and sent to the clock input terminal of the flip-flop circuit unit 23. The flip-flop circuit unit 23 has a number n of stages of the ring oscillator 30.
According to (n is an odd number, for example, n = 15), n flip-flops are provided in parallel. That is, the flip-flop circuit unit 23 having these n flip-flops indicates the state of each stage of the (n-bit) ring oscillator 30 formed by connecting n-stage inverting elements in a ring shape to the edge of the input signal RF _in . Each data input terminal D according to the detection output
Is to be taken into. In this example, n = 1
A 5-bit or 15-bit ring oscillator 30 is assumed, and the flip-flop circuit section 23 has 15 flip-flops provided in parallel in order to capture the state of the 15 internal stages.

Now, the ring oscillator 30 will be described with reference to FIG. In the example of FIG. 2, a ring oscillator 30 ′ having the number of stages n of 5 is shown for simplification of description. As shown in FIG. 2, a 5-stage (generally an odd-stage) or 5-bit ring oscillator 30 ′ has five inverting elements (inverters) 3
1 _a , 31 _b , 31 _c , 31 _d and 31 _e are connected in a ring shape. Since an odd number of inverting elements are connected, even if the input changes to “H”, the output remains the same polarity, for example, “H”, and there is always one element with a logical contradiction that does not change. When the output changes to "L" after the delay time of the element, the logic contradiction moves to the next element. In this way, stable oscillation can be obtained. Here in the example of FIG. 2, the start of oscillation of the ring oscillator 30 ', in order to stop, and with a two-input NAND (negative logical product) gate as element 31 _a, the NAND gate 31 _a
The output signal from the inverter 31 _e is sent to one end of the signal, and the signal STOP (where STOP represents a signal obtained by inverting the polarity of the stop signal STOP) is sent to the other end.

FIG. 3 illustrates the operation of the configuration of FIG. 2 above.
It is a diagram showing the signal waveform of each part forSTOP
And each element 31_a, 31_b, 31_c, 31_d, 31_eOr
These output signals a, b, c, d and e are shown. This
Here, each element 31_a, 31_b, 31_c, 31_d, 31_e
Each delay time of τ_a, Τ_b, Τ_c, Τ_d, Τ_eWhen
is doing. Above signalSTOPRises, time τ_aProgress
Later element 31_aThe inverted output signal a from
Lower element 31_b, 31_c, 31_d, 31_eDue to
And output signal waveforms as shown in b to e of FIG. 3 are obtained.
To be One cycle T of these output signals_RNThe ring osh
2 revolutions of logical contradiction propagating through 5 elements of the lator 30 '
Is equivalent to T_RN= 2 (τ_a+ Τ_b+ Τ_c+ Τ_d+ Τ_e) Is. Delay time τ of each element_a, Τ_b, Τ_c, Τ_d, Τ
_eAre equal to each other, for example τ₀(Τ_a= Τ_b= Τ_c= Τ
_d= Τ_e= Τ₀), T_RN= 10τ₀ The time it takes for this logical contradiction to return to its original position by rotating twice (ring
Oscillator oscillation operation time for one rotation, that is, oscillation
Operating cycle) T_RNIs the cycle T of the master clock MCK_MCYo
The delay amount and the number of stages per element are set so that
To be done. This is a ring oscillation within the master clock MCK.
If the same state of the data appears more than once, the time cannot be determined.
Because it is.

Focusing only on the rising edges of the output signals a to e in FIG. 3 (see arrows in the figure), the signal b, the signal d, the signal a, the signal c, and the signal e appear in this order, and one rotation of these appears. The one cycle T _RN is obtained. These signals b, d, a,
The ring oscillator outputs S ₁ , S ₂ , S ₃ ,
As S ₄ and S ₅ , the output terminals 32 ₁ , 32 ₂ , 3
It is taken out from 2 ₃ , 32 ₄ , 32 ₅ . These output signals S _{1 to} S ₅ are respectively sent to a plurality of (for example, five in this case) flip-flops that constitute the flip-flop circuit section. In the embodiment of FIG. 1, the ring oscillator 30 has 15 stages (15 elements).
15 output signals S _{1 to} S ₁₅ from each element are used.
Are sent to the respective data input terminals D of the 15 flip-flops of the flip-flop circuit section 23. In the flip-flop circuit section 23, the output signals S _{1 to} S ₁₅ from the ring oscillator 30 are fetched into the respective flip-flops at the timing of the RF input signal RF _in , whereby fine time measurement described later, particularly master clock MCK The position of the input signal edge with respect to the rising edge of is detected. in this way,
Regarding the state of each element of the ring oscillator (each output signal), for example, when focusing only on the rising edge of the signal as described above, the measurement unit time τ _{UN, which} is a unit for measuring the input signal edge position described later, is Element delay time τ ₀
2 (τ _UN = 2τ ₀ ).

Next, FIG. 4 shows a signal waveform for explaining the input edge detection operation in master clock units by the flip-flops 13 and 14 and the Ex-OR circuit 15 of FIG. In FIG. 4, the flip-flop 13 is an RF input signal from the input terminal 11 of FIG.
RF _in is taken in at the rising timing of the master clock signal MCK and the signal FF ₁₃ is output. The flip-flop 14 delays the output signal FF ₁₃ by one clock (master clock) cycle T _MC and outputs the signal FF ₁₄ . The Ex-OR circuit 15 outputs the signals FF ₁₃ and FF.
The exclusive OR of ₁₄ is taken and the signal EX ₁₅ is sent to the output terminal 16. "H" (high level) state of this output signal EX ₁₅ is, represents the edge detection state at clock period immediately before. As a result, the presence or absence of the edge of the input signal can be detected in units of master clock.

Next, referring to the signal waveforms shown in FIG.
The operation of measuring the edge time by the 15-element ring oscillator 30 of FIG. 1, that is, the operation of measuring a fine edge position within the master clock cycle T _MC will be described. In FIG. 5, the 15-element ring oscillator 3
0 indicates the time in the measurement unit time τ _UN, which is finer than the master clock MCK, like the output signal RS. The rising edge of the master clock MCK at this time and the RF
The time difference d from the rising or falling edge of the input signal RF _in is measured by the ring oscillator output signal RS in the above measurement unit time τ _UN .

Specifically, the master clock MCK from the input terminal 12 is provided in the flip-flop circuit section 27 which is composed of flip-flops for the number of elements (15 pieces) for taking in the state of each element of the ring oscillator 30. Is supplied as a clock, and the state of each element of the ring oscillator 30 is captured (latched) in each flip-flop at the timing of the rising edge of the master clock MCK. An example of the output from the flip-flop circuit section 27 is shown by the signal FF ₂₇ in FIG.

The delay element 21 and the exclusive OR (E
The edge of the RF input signal RF _in from the input terminal 11 is detected by the (x-OR) circuit 22.
The EX ₂₂ is sent to the clock input terminal of each flip-flop of the flip-flop circuit section 23, so that the states of the respective elements of the ring oscillator are taken into the respective flip-flops at the timing of the edge of this input signal.
The output signal FF ₂₃ from each flip-flop of the flip-flop circuit section ₂₃ is sent to the flip-flop circuit section 24 of the next stage.
Of the master clock MCK.
Is supplied as a clock, the signal FF is output at the timing of the rising edge of the master clock MCK.
The re-capturing (re-latching) of ₂₃ is performed, and the output signal FF ₂₄ is obtained from the flip-flop circuit section 24.

Here, the ring oscillator output signal of FIG.
As for RS, a number (15 states) corresponding to each state inside the 15-element ring oscillator, that is, each state (15 states) obtained by dividing one cycle (oscillation operation cycle) T _{RN of} the ring oscillator by the number of elements ( 1 to 15), the output signals FF ₂₃ , FF _{24 of} each flip-flop circuit unit,
Also for FF ₂₇ , numbers corresponding to the internal state of this ring oscillator are attached. For example, the state of the ring oscillator output RS at the rising time t ₁ of the master clock MCK in FIG. 5 is "1", and this state "1" is captured by the flip-flop circuit unit 27 (of which 15 flip-flops). Therefore, the output (output of 15 flip-flops) from the flip-flop circuit unit 27 after this time t ₁ becomes the state of “1”.

In FIG. 5, as a specific example of the fine position measuring operation within the master clock cycle T _MC , from the rising edge time t ₁₁ of the input signal RF _in to the rising time t ₂ of the next master clock MCK. The measurement operation of the time d1 will be described.

At the edge time t ₁₁ of the input signal RF _in ,
The state of the ring oscillator output RS is "2", and this state "2" is taken in by the flip-flop circuit section 23 and the output becomes "2". The output “2” from the flip-flop circuit section 23 is taken into the flip-flop circuit section 24 at the time t ₂ and sent to the binary conversion circuit 25. The state of the ring oscillator output RS at this time t ₂ is “9”, and since this state “9” is taken in by the flip-flop circuit section 27, the output “9” is sent to the binary conversion circuit 28. The outputs from these flip-flop circuit units 27 and 24 are respectively plural (15
It is the state of the output of each flip flop,
These states are converted into numerical data BN ₂₈ and BN ₂₅ by binary conversion circuits ₂₈ and ₂₅ , and are sent to the subtractor 26 as numerical values "9" and "2" in the example of FIG. A specific configuration example of the binary conversion circuits 28 and 25 will be described later with reference to FIG.

The time d1 at which the value of the output from the subtractor 26 indicates the fine position of the input edge is the measurement unit time τ.
Corresponds to the values expressed in _UN, during the period from the time t ₂ to the rise time t ₃ of the next master clock MCK is "7"
(= 9-2). That is, the input edge time t
Time d from ₁₁ to master clock rise time t ₂
1 is the measurement unit time τ of the ring oscillator 30.
Delay time 7τ _UN (= 7 _UN (= 2τ ₀ ))
It is measured to be approximately equal to 14τ ₀ ).

Similarly, the time d2 from the falling edge time t ₁₂ of the input signal RF _in to the next rising time t ₄ of the master clock MCK is the ring oscillator output RS at the times t ₁₂ and t ₄ . state "7", by "10" is subtracted by the subtractor 26 are in a time t ₄ after captured, is determined as an output value from the subtractor 26 "3" (= 10-7).

Next, a specific configuration example of the binary conversion circuits 27 and 25 will be described with reference to FIG. In FIG. 6, in order to simplify the description, 7
It shows a configuration in which seven states from a ring oscillator composed of element inverters are converted into binary.

[0026] In FIG. 6, seven flip-flops F1~F7 is equivalent to the flip-flop circuit 24 or 27, these flip-flops F1~F7 of each input signal S ₁ to S ₇ The state is captured at the timing of the rising edge of the master clock MCK. Each output from these flip-flops F1~F7 is first sent to a detection circuit 41 (the rising portion of the signal), and has a rising immediately after the portion of the respective signal S ₁ to S ₇ (top) The signal is detected. That is, of the signals S _{1 to} S ₇ , only the output corresponding to the signal at the beginning is “1” and the other outputs are “0”. This is because when the signals S _{1 to} S ₇ are arranged in the order in which the signals rise with the lapse of time, one signal S _k is “H” and the next signal S _{k + 1} is “L”. , The signal S _k is the beginning (the portion immediately after the rise). Here, k is a value of 1 to 7, and when k = 7, k + 1 = 1
Becomes Thus, in order to determine the condition that one signal S _k is “H” and the next signal S _{k + 1} is “L”, the negative gates (inverters) N1 to N7 and the AND gates are provided in the head detection circuit unit 41. Gates A1 to A7 are provided.

Regarding the output from the head detection circuit section 41, only the output corresponding to the signal of which the head is detected among the signals S _{1 to} S ₇ becomes "H"("1") and the other outputs. Are all "L"("0"), so to make this binary (binary) representation, AND gate A1
A 7-3 encoder 42 consisting of 0 to A12 is provided. This 7-3 encoder 42 has the least significant bit (L
SB) The head detection circuit unit H is provided in the AND gate A10 on the B ₀ side.
D's second, fourth, and sixth AND gates A2, A4, A6
Is supplied, the output from the third, fourth, and seventh AND gates A3, A4, and A7 of the head detection circuit unit 41 is supplied to the AND gate A11 of the next digit, and the most significant bit (MSB) is supplied. Lead detection circuit section H on AND gate A12 on the side
Fifth, sixth, and seventh AND gates A5, A6, and A7 of D
Is supplied to convert the 7-line input into a 3-bit binary code. Therefore, when the output from the AND gate A1 of the head detecting circuit unit 41 becomes "1", the 3-bit output from the 7-3 encoder 42 becomes "000", and thereafter, the outputs of the AND gates A2 to A7 sequentially become "1". When it becomes "1", the 3-bit output sequentially becomes "001" to "110".

As described above, each of the flip-flops 2
The states of the outputs from 7 and 24 are the binary conversion circuits 2 described above.
Converted to binary values at 8 and 25,
These values are sent to the subtractor 26, and the output value of the binary conversion circuit 25 is subtracted from the output value of the binary conversion circuit 28. The output value from the subtractor 26 is the input signal
The time from the edge of RF _in to the next rise of the master clock MCK (time d1 and d2 in FIG. 5 described above) is a value represented by the measurement unit time τ _UN of the ring oscillator 30, and this subtracted output value Are sent to the multiplier 36.

In the multiplier 36, in principle, the input edge fine position time d1 or d2 is calculated by multiplying the subtraction output value by the measurement unit time τ _UN based on each element state of the ring oscillator 30. To do. Since this fine position time is convenient for processing in the subsequent block, it is represented by a number with the master clock period T _MC being 1. Here, in the present embodiment, one cycle T _RN of the operation of the ring oscillator 30 from the ring delay time measuring circuit 33.
Is sent to the multiplier 36. The number of the multiplication output is converted into the time (for example, T _MC -d1, T _MC -d2, etc.) between the input edge time and the rising edge of the master clock MCK immediately before that by the 1/0 inversion in the inverter 37. . This is the output terminal 3 as the edge position signal EP.
It is taken out from 8. For example, this edge position signal EP
Is 6 bits, the master clock period T _{MC is set} to 1 and the binary rising decimal value from (0.) 000000 to (0.) 111111 (however, actually is from the rising edge of the master clock MCK to the next rising edge). Is not used for the leading integer part 0).

Next, a configuration example of the phase locked loop will be described with reference to FIG. In FIG. 7, terminal 1
2 is the master clock MCK, and terminal 16 is an edge detection signal ED for detecting the presence or absence of the input signal RF _in edge.
However, the terminal 38 is also supplied with an edge position signal EP representing the input edge position with the master clock cycle T _{MC set} to 1.

The edge detection signal ED supplied to the terminal 16 is input to a shift register 51 of a plurality of bits, for example, 9 bits, a plurality of bits (9 bits) are output in parallel in the order of time, and a reproduction clock 1 cycle length window. Circuit 5
It is sent to the reproduction clock cycle latch circuit 53 via the signal. The 9-bit output from the reproduction clock cycle latch circuit 53 is converted into a 4-bit binary value by the edge position integer part decoder 54 and sent to the subtractor 55. Further, the edge position signal EP supplied to the terminal 38
Is data in which the edge position when the master clock cycle T _{MC is set} to 1 as described above is represented by a plurality of bits (for example, 6 bits), and the plurality of bits (6 bits) are in parallel for a plurality of stages (for example, 9 stages). Of the shift register 56. The output from the shift register 56, for example, 6-bit parallel and 9-stage parallel is sent to the selector 57 to select edge position data of a plurality of bits (6 bits) of the stage corresponding to the bit where the input edge exists. And is sent to the reproduction clock cycle latch circuit 53. This is combined as the decimal part data (6 bits) of the edge position with the lower side of the integer part data (4 bits) from the edge position integer part decoder 54 and sent to the subtractor 55.

Next, the reproduction clock cycle data T _RC, which will be described later, is supplied to the terminal 61, and this reproduction clock cycle data T _RC is sent to the adder 62. The adder 62 constitutes a loop including a latch circuit 63 and an adder 64, and this loop corresponds to a VCO (voltage controlled oscillator) which is also the heart of the PLL. That is, during one loop of this loop, the adder 62 adds the reproduction clock cycle data, and the adder 64 adds the phase error correction data. The phase error correction data to the adder 64 is
It is given from the subtracter 55, for example, via the 1/4 circuit 58 and via the flip-flop circuit section 59. The in-window edge detection signal from the edge position integer part decoder 54 is supplied to the adder 64 as an addition control signal. When there is an edge in the window, the output data of the latch circuit 63 and the flip-flop circuit part The error correction signal data from 59 is added and output, and when there is no edge in the window, the output data from the latch circuit 63 is output as it is.

Reproduced clock cycle data T from the terminal 61
_RC is halved by the ½ circuit 65 to be reproduced clock half-cycle data T _RC / 2, which is sent to the adder 66 via the latch circuit 63. The lower 6-bit data of the 9-bit output data from the adder 64, for example, is supplied to the adder 66, and the addition result output is sent to the window generator 67. The window generator 67 is supplied with data of the lower (input stage) four stages of the 6-bit parallel 9-stage parallel shift register 56, that is, 24 bits of data, and the output from the window generator 67 is the reproduction clock 1 It is sent to the cycle length window circuit 52.

Next, the upper 3 bits of the 9-bit output from the adder 64, for example, are sent to the comparator 71. Further, the master clock MCK from the terminal 12 is sent to the 3-bit counter 72, and the output signal from the 3-bit counter 72 is sent to the comparator 71. When these two inputs of the comparator 71 coincide with each other, the coincidence output is sent as a reproduction clock cycle enable signal RCE to each enable terminal of the reproduction clock cycle latch circuit 53 and the latch circuit 63 and the output terminal 73. The reproduction clock cycle enable signal RCE is taken out as a reproduction clock output signal RCK from the output terminal 75 via the flip-flop 74. Further, the coincidence output (the reproduction clock cycle enable signal RCE) from the comparator 71 is sent to the AND gate 76, and is shaped RF via the flip-flops 77 and 78.
The output signal RF _out is taken out from the output terminal 79.
The master clock MCK from the terminal 12 is supplied to the clock input terminals of the flip-flops 74, 77 and 78,
The AND gate 76 is supplied with the in-window edge detection signal from the edge position integer part decoder 54.

Here, in general, the digital PLL detects how much the input edge is from "the position (time) of the input edge which should be supposed" in a master clock unit,
The reproduced clock phase is changed according to the deviation amount. The "properly input edge position" can be finely calculated by measuring one cycle length more finely than the master clock and integrating it, but since the minimum unit of the input edge time is the master clock, one master clock cycle T _Includes time error of _MC width. Edge is master clock cycle T
Calculated assuming that it is exactly in the center position of _MC , but eventually 1
The error in the width of the cycle of the master clock cycle T _MC remains included. On the other hand, in the embodiment of the present invention, the fine position of the edge can be determined by the edge position signal EP. Utilizing this has two advantages. One is the calculation of the accurate edge position error, and the other is the calculation of the accurate window boundary. The operation will be described below while focusing on these advantages.

The edge detection signal ED supplied to the terminal 16 of FIG. 7 is supplied to the shift register 5 of, for example, 9 bits.
It is input to 1 and it becomes a 9-bit parallel output in order of time,
It is sent to the reproduction clock cycle latch circuit 53 through the reproduction clock 1 cycle length window circuit 52. The 9-bit parallel output from the shift register 51 is latched at the timing at which the edge presence signal is output to the output bit at a predetermined position (normal center position) when the PLL is locked and the phase error of the input edge is 0. The latching interval is the reproduction clock R
It is the cycle T _RC of CK.

The edge position signal EP of 6 bits, for example, supplied through the terminal 38 of FIG.
It has been entered in 6. 6 from this shift register 56
Bit parallel output of 9 stages is sent to the selector 57, and a bit having an edge polarity in the output of the edge detection signal ED obtained from the shift register 51 through the window circuit 52. The 6-bit parallel output of the stage corresponding to is selected. Selector 5
The 6-bit parallel output 7 is fetched by the reproduction clock cycle latch circuit 53 at the cycle T _RC of the reproduction clock RCK.

The timing for latching is made so as to match the rate and phase of the edge of the input signal in the phase synchronization circuit. When an edge-existing signal appears at a predetermined position, the input edge has a relationship of scheduled timing with no phase error. Conversely, when there is no time shift such as peak shift in the input edge, it is inevitably latched when the signal with the edge is output to the predetermined position of the shift register. Therefore, when the latched edge presence / absence signal is at a position shifted by 1 bit from the predetermined position, it means that there is a phase shift (time shift) of about 1 bit before and after the master clock period T _MC . 1
Before and after a bit means that the exact position cannot be known by itself. However, since the edge position signal latched at the same time is at the timing when the edge presence signal has an edge, it is possible to know at which position in the master clock by looking at this.

Here, the position of the edge of the master clock unit is 1, 2, ...
It is represented by an integer such as 1, -2, .... On the other hand, the edge position signal representing the position in the master clock is represented by a decimal number from 0 to less than 1 from the earliest to the later according to the flow of time. By combining the integer part and the decimal part, the input edge position can be represented as a numerical value. For example, as shown in FIG. 8, the earliest temporal position in the central bit is 0.0. In addition,
In the specific example of FIG. 8, in order to simplify the illustration, the number of stages of the shift register is 7, the integer part is represented by 3 bits, and the edge position signal is represented by 4 bits (0000 to 1111). .

On the other hand, the timing of latching is calculated in more detail rather than in bit units. That is, the reproduction clock cycle T _RC is, for example, 5T in the master clock cycle T _MC.
It is not a value represented by an integral multiple, such as _MC or 6T _MC , but a value with a fractional part. This is integrated, and the integer part of the integration result makes the timing to latch, but naturally there is also a decimal part, and when latched, the input edge with no phase error is
The edge presence / absence signal is fetched at the central position, and the edge position signal coincides with the position of the fractional part of the numerical value forming the latch timing. A specific example of this is shown in FIG. In the concrete example of FIG. 9, in order to simplify the illustration, the integer part is 3 bits, the decimal part is 3 bits, and one cycle length T of the reproduction clock is set.
_RC is set to 100.011.

Therefore, by subtracting the fractional part of the numerical value that creates the latch timing from the numerical value representing the edge position obtained above, it is possible to know how much the edge deviates from the essential time. Only a fractional part needs to be subtracted because the integer part is used to determine the timing of the latch, and the position of the signal in master clock units of the latched edge is adjusted to the center when the error is 0. Because it is equivalent to already drawn in. In this way, the edge phase error can be obtained with the accuracy of the input edge position signal (precision sufficiently higher than the master clock).

To summarize the above operation, the output from the shift register 51 to which the edge detection signal ED is input is latched by the latch circuit 53 for each reproduction clock cycle enable signal RCE via the window circuit 52,
Separately from this, the edge position signal EP corresponding to the bit for which the edge detection flag is set in the output of the shift register is selected from the shift register 56 via the selector 57 and is similarly latched in the latch circuit 53. In addition,
The reproduction clock cycle enable signal RCE is an enable signal generated in accordance with the “intended edge position” calculated inside the phase synchronization circuit. If the output from the shift register 51 fetched by the latch circuit 53 is P
If the LL is locked and the input edge is just (just) the timing (at the same position as the "proper position" above), be sure to select the center bit (for example, the 5th bit of the 9-bit shift register). I'm supposed to stand. In the decoder 54 which receives the output from the latch circuit 53, the center position is set to 0, and then it is early (right side).
Values that increase toward the negative side, such as -1, -2, ..., as the bits shift, and values that increase toward the positive side, such as +1, +2, ..., as the bits shift to the slower (left) bit Is output. The decoder 54 also outputs the in-window edge presence / absence detection result indicating whether or not any bit in the window has an edge detection flag. Then, the value of the edge position signal simultaneously latched by the latch circuit 53 is added to the value of the edge bit position below the decimal point to obtain an accurate input edge position. This number is 0.0 at the beginning of the central bit in time. From this number, if the above-mentioned “originally desired edge position” is subtracted (however, since the integer part is 0, only the decimal part is subtracted), the error of the input edge can be obtained with high accuracy. This error amount is appropriately attenuated to obtain an appropriate loop gain, for example, attenuated to 1/4 by the 1/4 circuit 58 to create an error correction signal, and added to the loop for calculating the "ideal edge position". This controls the phase. In this way, the error amount of the edge is accurate, so that the reaction of the phase control does not become dull or sensitive.

The calculation of accurate window boundaries, which is another advantage of using the edge position signal EP, will be described below.

The edge detection signal ED supplied to the terminal 16 of FIG.
It is input to 1 and it becomes a 9-bit parallel output in order of time,
It is sent to the reproduction clock cycle latch circuit 53 through the reproduction clock 1 cycle length window circuit 52. The 9-bit parallel output from the shift register 51 is latched at the timing at which the edge presence signal is output to the output bit at a predetermined position (normal center position) when the PLL is locked and the phase error of the input edge is 0. The latching interval is the reproduction clock R
It is the cycle T _RC of CK. Since it is not latched at every reproducing clock period T _RC, since the shift register 51 until the next fetching only travels regeneration clock period T _RC content only when the output is capturing all bits (9 bits), the latch An edge once captured in the circuit 53 is again captured in the next acquisition, and one edge is counted twice. To avoid this, play clock 1
A period length window circuit 52 is inserted and arranged between the shift register 51 and the latch circuit 53, and a bit corresponding to ± 1/2 reproduction clock period (± T _RC / 2) is centered around a predetermined bit of the shift register 51. Through the output of
I try not to pass it outside.

The signal of the latching timing is obtained as the reproduction clock cycle enable signal RCE from (the comparator 71 of) the phase synchronization circuit. This reproduction clock cycle enable signal RCE is not the unit of the master clock cycle T _MC. , Is finely obtained in the unit of the measurement unit time τ _UN up to the position within the master clock cycle T _MC . This is because the reproduction clock cycle T _RC is obtained by a numerical value having a decimal point when the master clock cycle T _{MC is set} to 1, and the phase correction signal also moves the reproduction clock RCK in small units after the decimal point. Is. Therefore, if there is no error in the input edge presence / absence signal to be latched next, it is taken in to a predetermined (center) bit, but since that edge is also predicted to the position within the master clock, it should be as it should be. It is the position of the edge (with no phase error).

Regenerated clock 1 cycle length window circuit 52
The boundary of the window in is at ± 1/2 reproduction clock period (± T _RC / 2) from the original edge position. The left boundary of FIG. 7 is made by adding 1/2 reproduction clock cycle (T _RC / 2), but the right boundary is the left boundary of the previous latch and the difference in the number of bits between the previous latch and this latch You can use the place shifted by the amount of. Further, the right boundary can be omitted by unifying the polarity of the signal that shifts the shift register with respect to the bit that passed through the window in the previous latch (erasing the edge).

It may be possible to determine by rounding off whether or not the result of adding 1/2 reproduction clock just includes the bit that hits the boundary in the window, but in the present embodiment, the bit at the boundary is the edge position. Looking at the position of the input edge with the signal EP, when it is smaller than the decimal part of the boundary value, it is included in the window, and when it is larger, the bit is turned out of the window and is fetched at the next latch next time. Thus, the window is obtained with the same accuracy as the edge position signal has.

10 and 11 show the window generator 67 for calculating the window range as described above.
3 is a block circuit diagram showing a specific example of FIG. 4 and an explanatory diagram for explaining the operation thereof. First, in the adder 66 of FIG. 10, as described with reference to FIG. 7, the reproduction clock half cycle T obtained from the 1/2 circuit 65 via the latch circuit 63 is described.
And data X _A indicating the _RC / 2, and the data X _B representing a certain should edge position of the 9-bit output within the central bit of the lower 6 bits of the from the adder 64 is supplied. Of the 9 bits of these addition results, the upper 3 bits of data X
_C is the information indicating the bit with the boundary, and the lower 6
The bit data X _D is information indicating the position of the boundary within this boundary bit. Each of these data values X _A to X _D is shown in Figure 11.

Four 6-bit parallel outputs on the left side which are later in time from the center position (JUST) of the shift register 56 of FIG.
68d. These comparators 68a, 68
In b, 68c, and 68d, the lower 6-bit output of the 9-bit output from the adder 66, that is, the data X _D indicating the position of the boundary within the boundary bit is compared with each other, and when X _D is larger, "H" (high level or "1") is output. Data X _C indicating a bit with the boundary which is the upper 3-bit output of the adder 66 is sent to the decoder 68e, the data X _C is 1 or more when the AND gate 69a, when X _C is 2 or more and "H" is sent to the gate 69b and the OR gate 69e, and to the AND gate 69c and the OR gate 69f when X _C is 3 or more, and to the AND gate 69d and the OR gate 69g when X _C is 4. The output from the comparator 68a is sent to the AND gate 69a via the OR gate 69e, the output from the comparator 68b is sent to the AND gate 69b via the OR gate 69f, and the output from the comparator 68c is sent via the OR gate 69g. It is sent to the AND gate 69c, and the output from the comparator 68d is sent directly to the AND gate 69d. The outputs from the AND gates 69a to 69d are taken out as window signals W1 to W4,
It is sent to the reproduction clock 1 cycle length window circuit 52 of FIG.

In FIG. 11, when the previous desired edge position is at the point p2 of the input edge information string, the 9 bits to be latched last time are 4 bits before and after the bit (center bit) including this point p2. Point p1 to point p
The range is up to 5. At this time, the boundary on the left side of the window (future side which is later in time) is created by adding the reproduced clock half-cycle data X _A to the edge position (point p2) where the center bit should be. Point p4
Is obtained. It should be noted that as the right boundary, the previous (previously before) left boundary may be used as it is. here,
The position where the edge should be at this time is almost the reproduction clock cycle T _RC from the point p2, that is, the point p7 obtained by adding twice the half cycle data X _A , and is latched this time with the bit at the point p7 as the center. The target 9 bits are the range from point p3 to point p9. The point p8 obtained by adding the half-cycle data X _A to the left side (future side) from the position (point p7) where the edge should be this time is the position of the left boundary. For the position of the right boundary, the point p4, which is the previous left boundary, may be used.

Whether or not such a bit corresponding to the boundary is included in the window cannot be determined accurately by rounding off, for example. However, in the embodiment of the present invention, the edge position signal of the bit corresponding to the boundary is determined. And the position within the bit of the boundary calculated as described above (components after the decimal point) are compared. If the edge is inside the boundary, the bit is included in the window, and if it is outside, it is regarded as outside the window. I am trying to capture at the timing of. Even if the boundary bit does not have an edge and the edge position signal has a random value, there is no edge, so it does not make sense whether the boundary bit is within the window or not. Only valid if there is an edge at. A random error of an actual reproduction signal is detected because the edge is shifted by one reproduction clock cycle T _RC when the edge shifts due to the peak shift phenomenon and the noise gets on the direction of expanding the shift. Most of the time this happens. Therefore, the accuracy of the window boundaries improves the error rate.

The right boundary is obtained by unifying the polarity of the signal that shifts the shift register with respect to the bit that passed through the window at the time of the previous latch, that is, by eliminating the edge. , Can be omitted. A specific configuration example for this purpose is shown in FIG. In FIG. 12, the edge detection signal that has passed through the window circuit 52 and is latched by the latch circuit 53 is transmitted to the next stage of the shift register 51 after being cleared to 0 (with no edge). Since the once-latch edged signal is not further transmitted by the shift register 51, the window circuit configuration on the right side of the center can be omitted.

Since a window with high accuracy can be created in this way, the phase of the input edge can be compared with that of the recovered clock at the correct timing. That is, it can be regarded as an edge corresponding to a reproduction clock that is correct in terms of timing, and the signal error generated by the PLL due to the bit shift is reduced.

Returning to FIG. 7 again, the error amount of the high-precision input edge obtained by the subtractor 55 becomes 1 in the 1/4 circuit 58.
When it is attenuated to / 4, it is set as an appropriate loop gain and becomes an error correction signal, which is sent to the adder 64 via the flip-flop circuit section 59. The adder 64 constitutes a loop that serves as the heart of the PLL together with the adder 62 and the latch circuit 63. One cycle T _{RC of the} reproduced clock is added to the adder 62 and the correct error correction amount is added to the adder 64. Are added respectively. The latch circuit 63 is a flip-flop which uses the reproduction clock cycle enable signal RCE as an enable signal, and takes in data at every reproduction clock cycle T _RC . If the error correction amount is always 0, the number in this loop only increases by one cycle of the reproduction clock cycle T _RC .

On the other hand, there is provided, for example, a 3-bit counter 72 that counts up every master clock MCK, and this serves as a measure of time. When the output from the counter 72 matches the bit unit amount of the output value (9 bits) from the loop (the above integer part of the upper 3 bits), the comparator 71 outputs the reproduction clock cycle enable signal RC.
E is output and the output signal of the edge detection signal ED from the shift register 51 or the like is taken in, or the numerical value in the loop is updated to the one increased by one cycle length of the reproduction clock. The value in the loop updated here (adder 64
Is the value at the time when the next reproduction clock cycle enable signal should be output. When the count value of the counter 72 reaches that value, the comparator 71 causes the next reproduction clock cycle enable signal RCE. Is output.

The numerical value of the loop is also a value indicating "the position where the edge should originally be". That is, of the 9 bits output from the adder 64 of the loop, the integer part of the upper 3 bits controls the time at which the reproduction clock cycle enable signal RCE is output, so that the input edge of the just register is the shift register 51. When it comes to the center, it becomes the timing of fetching, and the decimal part of the lower 6 bits is used to obtain the error amount by subtracting from the value of the position of the input edge. In the window generator 67, the number of the reproduction clock half cycle is added to the numerical value of the loop, the integer part indicates the bit-wise window boundary, and the decimal part indicates the detailed boundary value in the bit.

As a final reproduction clock RCK, the reproduction clock cycle enable signal RCE is used as the master clock M.
I'm hitting with CK. That is, the master clock M
By transmitting the reproduction clock cycle enable signal RCE to the flip-flop 74 whose clock is CK, the reproduction clock output RCK synchronized with the master clock MCK is obtained from the flip-flop 74. Further, as the data output, the in-window edge presence / absence detection signal from the edge position integer part decoder 54 is produced by hitting the reproduction clock cycle enable signal RCE with the master clock MCK. The output from the AND gate 76 is shaped RF output signal RF _out via the flip-flops 77 and 78.
Is taken out from the terminal 79.

Next, the reproduction clock 1 for obtaining the reproduction clock 1 cycle length data (T _RC ) to be supplied to the terminal 61.
A specific example of the cycle length measuring circuit and a circuit configuration for setting the lock range of the PLL will be described with reference to FIG.

In FIG. 13, the master clock MCK from the terminal 12 is sent to each clock input terminal of the 6-bit counter 81, the 10-bit counter 82, and the 10-bit latch circuit 83. The reproduction clock cycle enable signal RCE from the terminal 73 is sent to the enable terminal of the 6-bit counter 81, and the 6-bit counter 8
The count output from 1 is sent to the load terminal of the 10-bit counter 82 and the enable terminal of the 10-bit latch circuit 83, respectively. "1" is always supplied to the data input terminal of the 10-bit counter 82. The output from the 10-bit counter 82 is the 10-bit latch circuit 8
3 to the comparator 84 and the selector 85, respectively. Or to the comparator 84, the constant K ₁ as a comparative minimum (lowest) value from the lock range setting unit to be described later, the constant K ₂ to the maximum (upper limit) value are sent respectively, it is within these ranges The comparison output indicating whether or not it is sent to the selector 85. The selector 85 switches and selects the output from the 10-bit latch circuit 83 and a constant K ₃ as a center (center) period from a lock range setting unit described later according to the output from the comparator 84. , To the terminal 61 as reproduced clock 1 cycle length data (T _RC ).

Next, the operation of this portion will be described. The reproduction clock 1 cycle length data (T _RC ) is represented by a number with the master clock cycle T _RC being 1. Looking at only one cycle of the reproduction clock, the number of master clocks in the reproduction clock is not large, so that highly accurate measurement cannot be performed. Therefore, the number of master clocks included in a plurality of reproduction clocks, preferably 2 ⁿ (n is an integer of 2 or more), is counted and the value is divided by 2 ⁿ . To divide by 2 ⁿ , it suffices to shift by n bits, and highly accurate measurement can be easily performed.

The value is not used as it is as one cycle length of the reproduction clock, and it is checked whether or not it is within the lock range. That is, in the comparator 84, the above cycle lower limit value K
₁ , compared with the upper limit value K _2, and if the values are in the range of K _{1 to} K ₂ , the output from the 10-bit latch circuit 83 is selected by the selector 85. The center cycle value K ₃ is selected and output as the reproduction clock 1 cycle length data in place of the measured value. This is because if the lock range is not limited, there are problems that it takes a long time to lock and that so-called pseudo lock easily occurs.

Next, the lock range setting section (and standard reproduction clock cycle measuring section) in FIG. 13 will be described. The standard reproduction clock SRCK from the input terminal 131 is sent to the 6-bit counter 132, for example. This standard reproduction clock SRCK has the same rate as the clock RCK reproduced by the PLL, and is always present in the system.
For example, DAT (Digital Audio Tape Recorder)
In, a clock having a recording waveform rate made by a crystal oscillator is prepared for recording, and the recording signal is sent to the tape by this clock. Therefore, the clock reproduced during reproduction has exactly this frequency. However, even if the frequency is the same, the crystal oscillation clock cannot follow the jitter or the like of the reproduction signal, and therefore cannot be used as the reproduction clock. This standard playback clock SR
The length of the CK cycle is measured in units of the master clock cycle T _MC. However, in order to obtain a measured value in binary with a precision of, for example, 6 digits after the decimal point, it is sent to the 6-bit counter 132 and 64 I try to measure the length of the cycle.

That is, in FIG. 14, the output CN ₁₃₂ obtained from the most significant bit (6th bit) of the 6-bit counter 132 by counting the standard reproduction clock SRCK is the standard reproduction clock SRCK. 64 cycles of 1 cycle (“L” (low level) and “H” (high level) alternate every 32 cycles).

The flip-flops 133 and 134, the inverter 136, and the AND gate 136 are circuit parts for detecting the falling edge of the output CN ₁₃₂ from the 6-bit counter 132 in units of master clocks. The master clock MCK is supplied to the input terminal. That is, the flip-flops 133 and 134 are driven by the master clock MCK shown in FIG.
By sequentially capturing output CN ₁₃₂ from the bit counter 132, these flip-flops 133 and 134
The respective outputs from are like signals FF ₁₃₃ and FF ₁₃₄ in FIG. The signal FF ₁₃₃ is inverted by the inverter 135, and the signal FF ₁₃₄ is inverted.
By ANDing with AND gate 136,
And output AN ₁₃₆ is obtained. This and output an
₁₃₆ is obtained every 64 cycles of the standard reproduction clock SRCK and is sent to the load control terminal of the 9-bit counter 137 and the enable terminal of the 9-bit latch circuit 138, for example. The 9-bit latch circuit 138 is provided with a 9-bit counter 1 each time the AND output AN ₁₃₆ is obtained.
The count output value from 37 is latched. Counter 13
7 counts the master clock MCK, and the count initial value "1" is loaded every time the AND output AN ₁₃₆ is obtained. These counter 137 and latch circuit 1
A concrete example of each output from 38 is shown by signal CN ₁₃₇ and signal LT ₁₃₈ in FIG.

The output from the latch circuit 138 is 1/64
The measured value (including the decimal point) is multiplied by 6 (shifted by 6 bits or the lower 6 bits are defined as a decimal value), and one cycle length of the standard reproduction clock SRCK is represented in units of the master clock cycle T _MC (including the decimal point). Is the above-mentioned selector 6 as the above-mentioned constant K ₃ representing the center cycle of the recovered clock.
Sent to 1. Also, for this measured value, the terminal 86T
The lock range lower limit period ratio smaller than 1 is sent to the multiplier 86M for multiplication, whereby the lower limit period constant K ₁
And the lock range upper limit cycle ratio greater than 1 from the terminal 87T is sent to the multiplier 87M to be multiplied to obtain the upper limit cycle constant K ₂ , and these constants K ₁ and K ₂ are compared to the comparator. I am sending it to 84. As a specific example of the lower limit period ratio from the terminal 86T and the upper limit period ratio from the terminal 87T, for example, when it is desired to limit the lock range to ± 10% in frequency, the lower limit period ratio is the same as the upper limit frequency ratio. /1.1=0.909, and since the upper limit period ratio is the same as the lower limit frequency ratio, 1 / 0.9 =
It becomes 1.111. If you want to limit the lock range to ± 20% in frequency, the lower limit cycle ratio is 1 / 1.2 =
0.833, and the upper limit cycle ratio is 1 / 0.8 = 1.25
Becomes

FIG. 15 is a time chart showing the waveforms of each part of the reproduction clock 1 cycle length measuring circuit section. The master clock signal MCK from the terminal 12, the reproduction clock cycle enable signal RCE, and the count value of the 6-bit counter 81. CN ₈₁ and a carry output signal CN _81C, shows 10 counts output signals CN ₈₂ from the bit counter 82, and 10-bit latch circuit 83 a specific example of the latch output signal LT ₈₃ respectively. The operation is as described above.

By adopting the structure shown in FIG. 13, the present invention can be applied to the case where the diameter of the rotary drum is 15 or more, such as DAT, and the reproduction rate changes accordingly. Since the lock center frequency and the upper and lower limits of the lock range are automatically determined, the same circuit can handle changes in the playback rate, prevent the increase in the number of IC elements and pins, and complicate the configuration. It can be avoided.

By the way, returning to FIG. 1 above, if the difference between the value of the ring oscillator 30 captured at the input edge (state of the output RS) and the value of the ring oscillator 30 captured at the master clock MCK is calculated, the input edge is obtained. However, in order to obtain the difference, the signal fetched at the input edge by the flip-flop circuit unit 23 is further fed by the flip-flop circuit unit 24 to the master clock MCK.
It is necessary to re-capture and use as the master clock synchronization signal. However, the signal re-acquired by the master clock is a signal that changes at the timing of the input edge asynchronous with the master clock. For this reason, if the input to the flip-flop circuit unit 24 unfortunately changes within the setup time or the hold time of the master clock re-fetch flip-flop circuit unit 24, either the input before the change or the input after the change is input. It is uncertain whether to import. Since the flip-flop circuit section 24 is composed of flip-flops corresponding to the number of stages of the ring oscillator 30 as described above, old and new data are mixed for each bit.

That is, for example, FIG. 16 shows an input RF signal.
Output from the flip-flop circuit unit 23 _in response to RF _in
FF ₂₃ , master clock MCK, flip-flop circuit section 2
4 shows the output FFs ₂₄ from the ring oscillators 4, and “a”, “b”, “c”, etc. in the figure indicate the ring oscillator 30.
Indicates the value (state) of. In FIG. 16, for example, the master clock MCK rises at time t ₁ while the flip-flop circuit unit 23 is capturing the ring oscillator value (state) “a”, and the flip-flop circuit unit 2
4 captures the value "a". At the rising edge time t ₁₁ of the input signal RF _in , the flip-flop circuit section 23 takes in the ring oscillator value “b”, and the flip-flop circuit section 24 takes in this at the rising time t ₂ of the master clock MCK. Here, when the master clock MCK rises at time t ₃ immediately after the falling edge time t ₁₂ of the input signal RF _in , the flip-flop circuit unit 23 fetches the ring oscillator value “c” at time t _12. The flip-flop circuit section 24 captures the data within the hold time between the time t and
The output from the flip-flop circuit unit 24 after ₃ may be a mixture of the value “b” and the value “c” in each bit.

Therefore, in the embodiment of the present invention, FIG.
By using the circuit configuration as shown in (3), the drawbacks due to the above-mentioned asynchronous signal acquisition are avoided. In this FIG.
The parts modified from the configuration of FIG. 1 are the configuration between the flip-flop circuit unit 23 and the subtractor 26, and the configuration from the flip-flops 13A and 13B to the OR gate 15C. With respect to the other parts, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Regarding the ring delay selection circuit 34, the ring oscillator 3
This is for switching and selecting the element delay time of 0, which will be described later.

In FIG. 17, the output from the flip-flop circuit section 23 is sent to each of the flip-flop circuit section 24A fetched at the rise of the master clock MCK and the flip-flop circuit section 24B fetched at the fall of the master clock MCK. The output from the flip-flop circuit section 24A is passed through the binary conversion circuit 25A, and the output from the flip-flop circuit section 24B is passed through the binary conversion circuit 25B.
Sent to. The output from the selector 25C is sent to the subtractor 26 and subtracted from the output of the binary conversion circuit 28.
Further, the input RF signal RF _in from the input terminal 11 is sent to the flip-flop 13A which is fetched at the rising of the master clock MCK and the flip-flop 13B which is fetched at the falling of the master clock MCK. The output from the flip-flop 13A is the flip-flop 1
4A and the exclusive OR (Ex-OR) circuit 15A, and the output from the flip-flop 13B is sent to the flip-flop 14B. The output from the flip-flop 14A is sent to the Ex-OR circuit 15B, and the Ex-OR circuit
The outputs from the flip-flop 14B are sent to the circuits 15A and 15B, respectively. Ex-OR circuit 15A,
The output from 15B is sent to the selector 25C as a selection control signal and is also sent to the OR gate 15C. The output from the OR gate 15C is the edge detection signal E
It is taken out from the terminal 16 as D.

The basic idea of the above configuration is that the latch output data at the input edge from the flip-flop circuit section 23 is data that changes at the timing of an error when it is taken in at the rising edge of the master clock MCK. In consideration of the fact that an error does not occur if it is fetched at the next falling edge of the master clock MCK. Here, if the data is captured only at the falling edge of the master clock MCK, the timing data that is captured at the falling edge and becomes an error causes a new problem. Therefore, the error between the rising edge and the falling edge of the master clock MCK is I try to select the captured data at the timing of those who do not.

That is, FIG. 18 is a time chart showing the waveforms and states (values) of the signals of the respective parts of FIG.
₂₃ such shows an output from the flip-flop circuit 23 or the like, the signal EX _15B, etc. indicates the output from the Ex-OR circuit 15B, etc., the signal SL _25C shows the output from the selector 25C. In the example of FIG. 18, the master clock MCK is generated at time t ₀₂ immediately after the falling edge time t ₁₂ of the input edge.
Is falling, and the rising time t _{13 of the} input edge
The master clock MCK rises at a time t ₄ immediately after.

In the example as shown in FIG. 18, the input which has transited to the section in which the master clock MCK is "L" (low level), that is, the time t _{01 to} t _{2, the} time t _{02 to} t _3, etc. Latch data from the flip-flop circuit unit 23 due to an edge (for example, time t ₁₃ between times t _{03 and} t ₄₎
Flip-flop circuit section 2 at the input edge raised by
For the data "d" taken in 3), when the master clock MCK rises again (time t ₄ ) and is re-latched, when the input edge is immediately before the rise of the master clock, the setup time of the flip-flop circuit unit 23 ( Since the hold time) may not be satisfied and the data may not be captured correctly, the data is captured in the flip-flop circuit section 24B at the next falling edge of the master clock MCK (time t ₀₄ ).

On the contrary, the latch data by the input edge which transits during the section in which the master clock MCK is "H" (high level), that is, between the times t _{1 to} t ₀₁ and t _{2 to} t _02, etc. (For example, time t between time t ₂ and time t _02
With respect to the data "c" fetched by the flip-flop circuit unit 23 at the input edge that fell at ₁₂ , when the master clock MCK falls (time t ₀₂ ) and is re-latched, the input edge is immediately before the fall of the master clock. In such a case, the setup time may not be satisfied and the data may not be fetched correctly. Therefore, the flip-flop circuit section 24A is not activated at the next rise of the master clock MCK (time t ₃ ).
Take in.

To summarize these ideas, for example, latched data by the input edge in the section where the master clock MCK is "L" is left in the section where the master clock MCK is "H" and re-latched at the next falling edge. Therefore, if there is an input edge in the section where the master clock MCK is "L", it is premised that the edge of the input signal does not come in the section where the next master clock MCK is "H". Since the direction of the master clock period T _MC than the playback clock cycle T _RC should not be longer, the edge interval of the input signal is essentially longer than the master clock period T _MC. at least,
The ratio of master clock frequency / reproduced clock frequency is 1
The larger it is, the more important it is, and if it is 2 or more, this effect is not conclusive.

Here, the master clock half cycle ( _TMC /
2) When the input edges are continuous (two continuous) in units, both edges can be canceled by using a circuit as shown in FIG. The circuit shown in FIG. 19 shows only the portion corresponding to the configuration from the terminals 11 and 12 to the terminal 16 of FIG. 17, and FIG. 20 shows the output signals from each flip-flop circuit.

19 and 20, four Ex-OR (exclusive OR) circuits 91, 92, 93,
Of the 94, the Ex-OR circuit 93 is the Ex-OR circuit 15A of FIG. 17, and the Ex-OR circuit 92 is the Ex-OR circuit of FIG.
Each of them corresponds to the circuit 15B, and the edges before and after the master clock half cycle ( _TMC / 2) are also seen. The AND gate 96 takes the logical product of the negation of the output of the Ex-OR circuit 91, the output of the Ex-OR circuit 92, and the negation of the output of the Ex-OR circuit 93, and thus the "H" section of the master clock MCK. The AND gate 96 detects the input edge in the inside, and the AND gate 96 negates the output of the Ex-OR circuit 92,
Edge detection is performed in the “L” section by taking the logical product of the output of the Ex-OR circuit 93 and the negation of the output of the Ex-OR circuit 94. In this way, only when there is no edge in the section before and after the half cycle section where the edge was,
The edge detection signal ED rises.

Next, the ring delay selection circuit 34 of FIG. 17 will be described. As described above, the ring oscillator 3
When 0 is applied to the digital PLL, it is possible to measure the input edge time with high accuracy, and there is an advantage that a master clock having a low frequency is sufficient. However, this ring oscillator uses the delay of the inverting gate element, and this delay greatly changes due to variations in the semiconductor manufacturing process, power supply voltage used, temperature used, and the like. Further, when the rate of the digital signal input to the PLL changes, the change in the reproduced clock is dealt with by the change in the circuit center frequency, which causes a large increase in the circuit. Therefore, the master clock is similar to the reproduced clock. It is preferable to change the ratio. Here, a specific example of the rate of change of the rate of the digital signal input to the PLL is assumed to be about 1: 8, and the rate of change of the master clock frequency at this time may be set to about 1: 4. preferable.

As described above, in the system in which the delay of the inverting gate element and the master clock cycle T _MC are not constant,
When the master clock period T _MC is short, the gate delay is short enough to have sufficient resolution, and when the master clock period T _MC is long, the ring oscillator has a period time that is long enough that the ring oscillator does not make one revolution within the master clock period T _MC . It is not realistic to have a ring oscillator with a huge number of stages. Therefore, a ring oscillator having a function capable of stepwise switching the delay amount per stage is used, and the ring delay amount selection circuit 34 causes the ring oscillator to be the most within a range where the ring oscillator does not make one or more rounds within the master clock cycle T _MC . A small delay amount for each stage is selected.

Automatic switching or automatic selection of the delay amount of the ring oscillator will be described with reference to FIGS. 21 to 23. FIG. 21 is a block circuit diagram showing a specific example of the ring delay time measuring circuit 33 and the ring delay selecting circuit 34 of FIG. In FIG. 21, the input terminal 101 of the ring delay time measuring circuit 33 is connected to the above-mentioned FIG.
7 ring oscillator 30 (However, the specific configuration is shown in FIG.
2 ring oscillator 30 ″ is preferable), and the output signal from any one element is supplied from the output terminal 109, and the measured output of, for example, 11 bits is sent to the multiplier 36 of FIG. 22 shows a specific configuration example of the ring oscillator 30 ″ whose delay time is selectively controlled by the ring delay selection circuit 34 of FIG. 21, and FIG. 23 can be used for the ring oscillator 30 ″. One specific example of the inverting element is shown.

Here, the ring delay time measuring circuit 33 calculates one cycle (one rotation) T _RN of the operation of the ring oscillator as follows.
The master clock cycle T _MC is measured as a unit. As the measurement waveform, the output waveform of any one inverting element of the ring oscillator is used. However, since accuracy cannot be obtained with one waveform (one cycle), one waveform (one cycle) is obtained by measuring the length of a plurality of waveforms (a plurality of cycles) and dividing by the number of waveforms. Actually, it is sufficient to measure the time of 2 ^N (N is a natural number) waveforms and shift it by N bits to obtain a value that is 1/2 ^N. In the example of FIG. 21, N =
The number is 6, and the number of master clocks entering during 64 waveforms is measured.

That is, in FIG. 21, an output signal from any one element of the ring oscillator supplied via the terminal 101 is supplied to, for example, a 6-bit counter 102, and its MSB (most significant bit) output (so-called) is output. Q
₆ ) is sent to the flip-flop 103 and latched,
Flip-flop 104, inverter (inverting element) 10
5, the AND gate 106 differentiates to detect an edge (falling edge). Each flip-flop 1
The master clock MCK is used as the clock for 02 and 103.
Is used. The output signal from the AND gate 106 has a pulse period of 64 _times the ring oscillator period T _RN .
Doubled 64 T _RN and pulse width 1 master clock cycle T _MC
Has become. This output signal is applied to, for example, the load terminal of the 11-bit counter 107 and the 11-bit latch circuit 108.
The number of master clocks MCK within the time of 64T _RN is obtained by sending the master clocks MCK to the enable terminal. Specifically, the output pulse from the AND gate 106 loads "1" into the 11-bit counter 107 (resets to an initial value "1"), and the value immediately before resetting is taken into the latch circuit 108. ing. If a point between the 6th bit and the 7th bit from the LSB (least significant bit) of the 11-bit output from the latch circuit 108 is regarded as the decimal point, the position of the decimal point of the 11-bit integer value output is moved to the upper side by 6 bits. This means a shift, which is 1/64. This is one of the operations of the above ring oscillator.
The rotation cycle T _RN is measured with an accuracy of 1/64 of the master clock cycle T _MC .

The ring delay selection circuit 34 is for selecting the delay amount of the ring oscillator to an appropriate value.
For example, when the value measured by the ring delay time measurement circuit 33 is 1 or less, the ring oscillator makes one or more revolutions within one cycle T _MC of the master clock, so it is necessary to select a delay amount one rank larger. Is. At this time, it is preferable to perform switching with a margin so that the delay amount is switched to one rank larger when the measured value does not reach 1 but falls below a predetermined lower limit value k _MIN of about 1.2, for example. . Further, if the measured value is too large, the cycle T _RN of one rotation of the operation of the ring oscillator is unnecessarily large, so that the measurement unit time τ _UN obtained by dividing this by the number of stages of the ring oscillator becomes large and measured. The accuracy (resolution within the master clock cycle T _MC ) will decrease. Therefore, the upper limit value k _MAX is also set, and this upper limit value k
_{When exceeding MAX} , it is preferable to perform switching control to a delay amount one rank smaller.

In the ring delay selection circuit 34 shown in FIG. 21, in the comparator 111, the measured output value from the latch circuit 108 is set to the lower limit value k _{MIN of} about 1.2 and the upper limit value k _MAX (for example, about 2). ), When it is in the range of the lower limit value k _MIN to the upper limit value k _MAX , “0” is set, and when it is smaller than the lower limit value k _MIN, “+1”.
When it is larger than the upper limit value k _MAX , “−1” is sent to the adder 112. The addition output from the adder 112 is the above-mentioned 6 from the AND gate 106.
The pulse output of the 4T _RN cycle is sent to the latch circuit 113 input to the enable terminal, and the output from the latch circuit 113 is sent to the adder 112 and the decoder 114. The decoder 114 decodes the output signal from the latch circuit 113 into, for example, five signals X _{1 to} X ₅ and outputs the decoded signals.

Next, FIG. 22 shows an example of the ring oscillator 30 "the delay amount by the signals X ₁ to X ₅ is switching control, n (n is an odd number) of the inversion (inverter) circuit 31
_{1 to} 31 _n are connected in a ring shape, and output signals S _{1 to} S _n are taken out from each connection point. Each of the inverting circuits 31 _{1 to} 31 _n has a configuration in which the delay time can be switched in five stages by the signals X _{1 to} X ₅ from the ring delay selecting circuit 34 of FIG. A concrete example of the inverting circuit 31 capable of switching the delay time in five stages is shown in FIG.
3 shows.

The input terminal 120 of the inverting circuit 31 of FIG.
Is a delay element 1 with delay times τ ₁ , τ ₂ , and τ ₃ , respectively.
21 and 122 and 123 are connected to one end of a series connection circuit, and AND gate 124 and AND gate 12 are connected.
5 are connected respectively. The output terminal of the delay element 121 is connected to the AND gate 126, the output terminal of the delay element 122 is connected to the AND gate 127, and the output terminal of the delay element 123 is connected to the AND gate 128. AND gates 124 to 128 have the signals X ₁ to
X ₅ are supplied, the AND gate is turned any one of the signals X ₁ to X ₅ is to "H".
The outputs from the AND gates 125 to 128 are sent to the NOR gate 130 via the OR gate 129, and the output from the AND gate 124 is sent to the NOR gate 130. The output from the NOR gate 130 is the inverter circuit 31.
Is output from the terminal 131.

In the configuration of FIG. 23, when the delay times of the AND gates 124 to 128 are equal to τ _AND , the delay time of the _OR gate 129 is τ _OR, and the delay time of the NOR gate 130 is τ _NOR , The delay amount τ _X1 of the inverting circuit 31 when X ₁ is selected and becomes “1” is τ _X1 = τ _AND + τ _NOR . Similarly, the delay amounts τ _X2 , τ _X3 , τ _X4 , and τ _X5 of the inverting circuit 31 when the signals X ₂ , X ₃ , X ₄ , and X ₅ are selected and become “1” are respectively τ _X2 = τ _AND ＋ τ _OR ＋ τ _NOR τ _X3 ＝ τ ₁ ＋ τ _AND ＋ τ _OR ＋ τ _NOR τ _X4 ＝ τ ₁ ＋ τ ₂ ＋ τ _AND ＋ τ _OR ＋ τ _NOR τ _X5 ＝ τ ₁ ＋ τ ₂ ＋ τ ₃ ＋ τ _AND ＋ τ _OR ＋ τ _NOR . Therefore, the delay amount increases in the order in which X ₁ to X ₂ , X ₃ , X ₄ , and X ₅ are selected.

In this case, the above-mentioned respective delay amounts τ which can be switched and selected
When setting _{X1 to} τ _X5 , it is preferable that the ratios of adjacent delay amounts, for example, τ _X2 / τ _X1 , τ _X3 / τ _X2, etc., are set to be equal to or less than a predetermined value R. The switching condition of the ring delay time is, for example, to increase the delay amount by one step when the measured value of the ring oscillator cycle T _RN (value when the master clock cycle T _MC is 1) is less than or equal to the lower limit value k _MIN. If the delay amount is decreased by one step when the value exceeds the upper limit value k _MAX, it is necessary to satisfy the relationship of k _MAX / k _MIN > R. If this relationship is not satisfied, for example, R = 2, k _MIN = 1.2, k _MAX =
In the case of 2.0, the delay time is increased by one step when the ring delay time measurement output is smaller than the lower limit value k _MIN = 1.2 but is very close to 1.2 from the time of selecting X ₁ above. Then, the above X ₂ is selected, but R = τ _X2 /
Since τ _X1 = 2, the ring delay time measurement output is 2.4.
It is a slightly smaller value. This is the upper limit value k _MAX =
Since the value is larger than 2.0, the switching control for reducing the delay time by one step is automatically performed, and the measured output is again smaller than the lower limit value k _MIN = 1.2 but close to 1.2. The above operation will be repeated. That is, the delay amount switching operation becomes unstable. From this, the above k
_It is clear that it is necessary to satisfy the relationship of _MAX / k _MIN > R.

As described above, by automatically switching the delay time of the ring oscillator, the normal PLL operation can be performed even if there are variations in semiconductors or variations in element delay due to temperature changes, power supply voltage variations, etc. This can be maintained, and, for example, mass production design as an LSI is actually possible. Further, when applied to a PLL, it can be dealt with by changing the master clock in response to a change in the input signal rate of the PLL, and the circuit configuration can be simplified.

The present invention is not limited to the above-described embodiment, and for example, the number of bits of the ring oscillator (the number of stages, the number of elements), the number of bits of the ring delay time measurement output, the edge position signal, the edge detection signal, etc. The number of bits, the number of stages, etc. of the shift register, the latch circuit, etc. for taking in the data are not limited to the illustrated example. Of course, various modifications can be made without departing from the scope of the present invention.

[0092]

As is apparent from the above description, according to the digital PLL device of the present invention, the upper limit of the lock range is set with the value obtained by measuring the period of the reference clock having the same frequency as the PLL reproduction clock as the central period, Since the lower limit is sought, an appropriate lock range can be automatically set for a signal of any reproduction rate, and the same circuit can handle changes in the reproduction rate. Therefore, when integrated into an IC, the circuit configuration can be simplified and an increase in the number of pins and complication can be prevented.

[Brief description of drawings]

FIG. 1 is a digital PL as an embodiment according to the present invention.
It is a block circuit diagram which shows schematic structure of the edge time measurement circuit part of the input signal of L apparatus.

FIG. 2 is a circuit diagram showing a configuration example of a ring oscillator used in the embodiment.

FIG. 3 is a timing chart for explaining the operation of the ring oscillator shown in FIG.

FIG. 4 is a timing chart for explaining an edge detection operation of an input signal.

FIG. 5 is a timing chart for explaining an edge position detecting operation of an input signal.

FIG. 6 is a circuit diagram showing a specific example of a binary conversion circuit.

FIG. 7 is a digital PL as an embodiment according to the present invention.
It is a block circuit diagram which shows the schematic structure of the phase locked loop circuit part of L apparatus.

FIG. 8 is a diagram showing a specific example of a value of a signal indicating an edge position.

FIG. 9 is a diagram for explaining calculation of an edge position where a phase error is 0.

10 is a block circuit diagram showing a specific example of the window generator in FIG.

FIG. 11 is a diagram for explaining the operation of the window generator of FIG.

12 is a block circuit diagram showing a specific configuration example of a window circuit in FIG. 7 and circuits in the vicinity thereof.

FIG. 13 is a block circuit diagram showing a specific example of a reproduction clock 1 cycle length measuring circuit.

FIG. 14 is a waveform diagram for explaining the operation of a partial configuration of the circuit of FIG.

15 is a waveform chart for explaining the operation of the configuration of another portion of the circuit of FIG.

FIG. 16 is a timing chart for explaining erroneous detection of an input edge position.

FIG. 17 is a block circuit diagram showing a schematic configuration of an edge time measuring circuit section of an input signal in which erroneous detection of an input edge position is prevented.

FIG. 18 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 19 is a circuit diagram showing a main part configuration of another specific example for preventing erroneous detection of an input edge position.

20 is a timing chart for explaining the operation of the circuit of FIG.

21 is a block circuit diagram showing a specific configuration example of a ring delay time measuring circuit and a ring delay selecting circuit in FIG.

FIG. 22 is a block circuit diagram showing a specific example of a ring oscillator whose delay time can be switched and selected.

FIG. 23 is a circuit diagram showing a specific example of an inverting circuit used in a ring oscillator whose delay time can be switched and selected.

[Explanation of Codes] 11 ... RF signal input terminal 12 ... Master clock signal input terminal 13, 14, 74, 77, 78 ... Flip-flop 15, 22 ... Exclusive-OR (Ex-OR) circuit 23, 24, 27, 59 ... Flip-flop circuit section 25, 28 ... Binary conversion circuit 26, 55 ... Subtractor 30, 30 ', 30 "... ring oscillator 33 ... ring delay time measurement circuit 34 ... ring delay selection circuit 36 ... multiplier 51 ... 9-bit shift register 52 ... Regenerated clock 1 cycle length window circuit 53 ... Regenerated clock cycle latch circuit 54 ... Edge position integer part decoder 56 ... 6 bit parallel 9 bit shift register 57 .... Selector 58 ... Quarter circuit 61 ... Reproduced clock 1 cycle length measured value supply terminal 62, 64, 66 ... Adder 63 ... Latch circuit 67 ... Window generator 71 ... Comparator 72 ... 3-bit counter 81, 132 ... 6-bit counter 82 ... 10-bit counter 83 ...・ 10-bit latch circuit 84 ・ ・ ・ Comparator 85 ・ ・ ・ Selector 86M, 87M ・ ・ ・ Multiplier 86T ・ ・ ・ Lock lower limit period ratio input terminal 87T ・ ・ ・ Lock upper limit Period ratio input terminal 131: Standard reproduction clock input terminal 137: 9-bit counter 138: 9-bit latch circuit

Claims (3)

[Claims] 1. A digital PLL device for controlling a PLL reproduced clock based on phase error data obtained by detecting a phase error between a PLL reproduced clock and an input signal using a master clock, and a reference clock having the same frequency as the reproduced clock. Of the master clock as a unit, the measured value is used as the central period of the PLL reproduction clock to determine the upper limit period and the lower limit period, and the range between the upper limit period and the lower limit period is the lock range of the PLL. A digital PLL device characterized by: 2. The upper limit cycle is obtained by multiplying the measured value by a constant larger than 1, and the lower limit cycle is obtained by multiplying the measured value by a constant smaller than 1. The described digital PLL device. 3. A PLL reproduction based on an edge detection signal obtained by detecting an edge of the input signal in units of the master clock, and an edge position signal indicating a position of the input edge within the master clock. 3. The digital PLL device according to claim 1, wherein the phase error data between the clock and the input signal edge is obtained in units of time shorter than the master clock cycle.