JPH06112219A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent short circuit between a gate and a source drain of a MOS transistor having a polysilicon side wall on the side surface of a gate electrode. CONSTITUTION:Relating to a MOS transistor having a polysilicon side wall 8 on the side surface of a gate polysilicon 5, an oxide film side wall 10 is provided to the side surface of the polysilicon side wall 8. With this, a titanium silicide 9 on the gate polysilicon 5 is sufficiently separated from the titanium silicide 9 on a source.drain 7, for preventing short circuit between the gate and source.drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art The structure and manufacturing method of a gate and a source / drain of a conventional MOS transistor in which all LDD portions are located directly below a gate electrode will be described with reference to FIG.

A 200 Å gate oxide film 2, a 200 Å polysilicon film 3, a 200 Å oxide film 4 and a 3000 Å polysilicon film 5 are sequentially formed on a silicon substrate made of a low concentration p-type region 1.

Next, anisotropic etching is sequentially performed on the polysilicon 5 and the oxide film 4 by the photolithography technique. Then, phosphorus is used, for example, with an energy of 100 Ke.
Ions are implanted with V and a dose amount of 7 × 10 ¹³ cm ⁻² to form a low concentration n-type region 6 (FIG. 3A).

After vapor phase growth of 2000 Å polysilicon 8, polysilicon 8 and polysilicon 3 are anisotropically etched to form sidewalls. The energy of arsenic is 70 KeV and the dose is 1 × 10 ^16.
Ions are implanted at a cm ⁻² to form a high concentration n-type region 7 (FIG. 3B).

The oxide film 2 is removed by anisotropic etching, titanium is formed by a sputtering method, and then annealing is performed to form polysilicon 8 and polysilicon 5 and a selective titanium sidewall 9 only on the high concentration n-type region 7. To form. The polysilicon 5, the polysilicon 8 and the polysilicon 3 are electrically connected.

The advantage of the MOS transistor as shown in FIG. 3C is that the low-concentration n-type region corresponding to LDD is completely located under the gate electrode (polysilicon 3), so that the gate oxide film is formed. It can be mentioned that the resistance of the low-concentration n-type region 6 immediately below 2 decreases. That is, when a forward voltage is applied to the gate, the potential in the vicinity of the surface of the LDD portion below the gate electrode is lowered and a channel is formed, which lowers the resistance of the LDD portion.

[0008]

In the structure of the conventional MOS transistor described above, titanium silicide 9 (TiS) formed on the gate and the source / drain is used.
There is a problem that i ₂ ) is short-circuited.

An object of the present invention is to provide a semiconductor device in which a gate and a source / drain are prevented from being short-circuited and a manufacturing method thereof.

[0010]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a first polycrystal provided on one main surface of a semiconductor substrate of one conductivity type via a gate oxide film. Silicon, a first oxide film provided on the first polycrystalline silicon, a second polycrystalline silicon provided on the first oxide film, and a side surface of the second polycrystalline silicon. And a second oxide film provided on a side surface of the third polycrystalline silicon, and a third polycrystalline silicon provided on the semiconductor substrate below the third polycrystalline silicon. A first reverse-conductivity type impurity diffusion region having a shallow concentration; a second high-concentration reverse conductivity type impurity diffusion region provided adjacent to the first reverse-conductivity type impurity diffusion region; Provided on the polycrystalline silicon and on the impurity diffusion region of the second opposite conductivity type Those having a genus silicide.

In the method of manufacturing a semiconductor device according to the present invention, a gate oxide film, a first polycrystalline silicon film, a first oxide film and a second polycrystalline silicon film are sequentially formed on the main surface of a semiconductor substrate. A step of forming a stacked layer, a step of etching the second polycrystalline silicon and the first oxide film, and a first impurity on the substrate using the etched second polycrystalline silicon and the first oxide film as a mask Forming a diffusion region, forming third polycrystalline silicon, etching the third polycrystalline silicon and the first polycrystalline silicon, and forming a sidewall on a side surface of the second polycrystalline silicon. Forming a second impurity diffusion region, forming a second oxide film, etching the second oxide film and the gate oxide film, and removing the third polysilicon film. Side to side And a step of forming a metal film and performing annealing to selectively form a metal silicide only on the second polycrystalline silicon and the second impurity diffusion region. It is a waste.

The second oxide film is a nitride film.

[0013]

In the MOS transistor having the polysilicon sidewall 8 on the side surface of the gate polysilicon 5,
An oxide film side wall 10 is provided on the side surface of the polysilicon side wall 8. As a result, the titanium silicide 9 on the gate polysilicon 5 and the titanium silicide 9 on the source / drain 7 can be sufficiently isolated, so that a short circuit between the gate and the source / drain is prevented.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a vertical sectional view showing a first embodiment of the present invention in the order of steps.

In FIG. 1A, 200 Å gate oxide films 2 and 2 are formed on a silicon substrate composed of a low concentration p-type region 1.
00Å polysilicon 3 and 200Å oxide film 4 and 300
Then, 0Å polysilicon 5 is sequentially formed.

Then, the polysilicon 5 and the oxide film 4 are sequentially anisotropically etched by using the photolithography technique. And phosphorus, for example, energy 100 Ke
Ions are implanted with V and a dose amount of 7 × 10 ¹³ cm ⁻² to form a low concentration n-type region 6.

As shown in FIG. 1 (b), after 2000 Å polysilicon 8 is vapor-phase grown, the polysilicon 8 and the polysilicon 3 are anisotropically etched to form sidewalls. Arsenic is ion-implanted at an energy of 70 KeV and a dose amount of 1 × 10 ¹⁶ cm ⁻² to form a high concentration n-type region 7.

Next, as shown in FIG. 1C, an oxide film 10 is formed on the entire surface, and then the oxide film 10 and the gate oxide film 2 are anisotropically etched to form sidewalls.

Next, as shown in FIG. 1 (d), 1000Å
Titanium is formed by a sputtering method, and titanium silicide 9 (TiSi ₂ ) is selectively formed only on the polysilicon 8 and the high-concentration n-type region 7 by a lamp annealing method. The polysilicon 5, the polysilicon 8 and the polysilicon 3 are electrically connected.

As described above, since the titanium silicide 9 on the gate polysilicon 8 and the titanium silicide 9 on the high-concentration n-type region 7 can be sufficiently isolated by the side wall 10 of the oxide film, the gate and the source / drain can be separated. A short circuit can be prevented.

(Embodiment 2) FIG. 2 is a vertical sectional view showing Embodiment 2 of the present invention.

In this embodiment, the oxide film sidewalls 10 are replaced with nitride film sidewalls 11.
Since the nitride film has a higher breakdown voltage as an insulating film than the oxide film, it is possible to obtain higher reliability by using the nitride film in the sense of preventing a short circuit between the gate and the source / drain.

[0024]

As described above, according to the present invention, by providing the side wall of the oxide film on the side surface of the gate of the conventional MOS transistor, the titanium silicide on the gate and the titanium silicide on the source / drain can be sufficiently formed ( Since they can be separated by several thousand Å), a short circuit between the gate and the source / drain can be eliminated.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a vertical cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 3 is a vertical cross-sectional view showing a conventional example in the order of steps.

[Explanation of symbols]

 1 Low-concentration p-type region 2 Gate oxide film 3 Polysilicon 4 Oxide film 5 Polysilicon 6 Low-concentration n-type region 7 High-concentration n-type region 8 Polysilicon 9 Titanium silicide 10 Oxide film 11 Nitride film

Claims (3)

[Claims] 1. A first polycrystalline silicon provided on one main surface of a semiconductor substrate of one conductivity type via a gate oxide film, and a first oxide provided on the first polycrystalline silicon. A film, second polycrystalline silicon provided on the first oxide film, third polycrystalline silicon provided on a side surface of the second polycrystalline silicon, and third polycrystalline silicon A second oxide film provided on a side surface of the first polysilicon film, a low-concentration and shallow first reverse-conductivity-type impurity diffusion region provided on the semiconductor substrate below the third polycrystalline silicon, and the first reverse film. A high-concentration and deep second reverse-conductivity-type impurity diffusion region provided adjacent to the conductivity-type impurity diffusion region, and provided on the second polycrystalline silicon and the second reverse-conductivity-type impurity diffusion region. A semiconductor device having a metal silicide. 2. A gate oxide film on the main surface of a semiconductor substrate,
A step of sequentially laminating a first polycrystalline silicon film, a first oxide film and a second polycrystalline silicon film, a step of etching the second polycrystalline silicon and the first oxide film, and an etching process A step of forming a first impurity diffusion region on the substrate by using the second polycrystalline silicon and the first oxide film as a mask, and forming a third polycrystalline silicon, the third polycrystalline silicon and the Etching the first polycrystalline silicon,
Forming a sidewall on a side surface of the second polycrystalline silicon; forming a second impurity diffusion region; forming a second oxide film; and forming the second oxide film and the gate oxide film. By etching to form sidewalls on the side surfaces of the third polycrystalline silicon, and by forming a metal film and annealing,
7. A method of manufacturing a semiconductor device, comprising the step of selectively forming metal silicide only on the polycrystalline silicon and on the second impurity diffusion region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the second oxide film is a nitride film.