JPH06112429A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] D without increasing the storage electrode height
A semiconductor memory device having a plane pattern of storage electrodes that can secure a necessary capacitor capacity for a RAM cell and does not make it difficult to contact a layer below the storage electrodes from a wiring above the storage electrodes and the same. It is to provide a manufacturing method. In a semiconductor memory device in which a plurality of memory cells each having a MOS transistor and a capacitor connected to one of a source and a drain of the transistor are arranged on a semiconductor substrate, a storage electrode 22 of the capacitor has a minimum processing size. The storage electrodes 22 having a large projected area with a separation interval smaller than the minimum processing size are formed by combining square patterns to form a cross shape and using the corner portions of the patterns to separate the adjacent storage electrodes 22. To do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a dynamic RAM (DRAM) having a stack type capacitor structure.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been highly integrated and have a large capacity.
In a MOS dynamic RAM (DRAM) composed of individual MOS capacitors, research into miniaturization of the memory cell is progressing. With the miniaturization of such memory cells, the area of the capacitor that stores information (charge) is reduced, and as a result, the memory contents are erroneously read out, or the memory contents are destroyed by α rays or the like. Etc. is a problem.

As a method for solving such a problem and achieving high integration and large capacity, the occupied area of the capacitor is substantially expanded, the capacity of the capacitor is increased, and the storage capacity is increased without increasing the occupied area. Various methods have been proposed to increase the amount of charge. One of them is a DRAM having the following stack type capacitor structure.

This DRAM has a plan view shown in FIG.
7 shows a sectional view taken along the line FF ′ in FIG. 26, the element isolation region 2 (2 ₁ , 2 ₂ ...) And the element region 9 (9 ₁ , 9 ₂
...), and further the word lines 3 (3 ₁ , 3 ₂ ...) to form MOS transistors, and the bit lines 10 (1
0 _1, 10 ₂ ...), the storage electrode 4 (4 _1, 4 ₂ ...), the capacitor insulating film 5, to form a plate electrode 6 to form a DRAM cell. In addition, 7 is a storage electrode contact, 8
Indicates an insulating film.

In such a structure, not only the projection surface but also the side surface contributes to the capacitor area as the storage electrode.
By increasing the height of the storage electrode, the capacitance of the capacitor can be increased.

However, in this structure, since the projected area and the peripheral length of the plane pattern of the storage electrode are not sufficiently large, in order to obtain the capacitor capacity required for the DRAM cell,
The storage electrode height must be increased. Therefore, there is a problem that it is difficult to make contact with a layer below the storage electrode from the wiring above the storage electrode.

[0007]

As described above, in the conventional plane pattern of the storage electrode, the projected area and the peripheral length of the plane pattern of the storage electrode are not sufficiently large, so that the capacitance of the capacitor required for the DRAM cell is increased. There is a problem in that it is necessary to increase the height of the storage electrode, and it becomes difficult to make contact with the layer below the storage electrode from the wiring above the storage electrode.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to secure a capacitor capacity necessary for a DRAM cell without increasing the height of the storage electrode so much. It is an object of the present invention to provide a semiconductor memory device having a planar pattern of a storage electrode, which makes it easy to contact a layer below the storage electrode from a wiring above the storage electrode, and a manufacturing method thereof.

[0009]

According to the present invention, by using a corner portion of a pattern for separating storage electrodes of a memory cell, a storage electrode having a projected area with a separation interval smaller than the minimum processing dimension and a large planar pattern peripheral length is provided. Is formed.

That is, according to the present invention, in a semiconductor memory device in which a plurality of memory cells each having a MOS transistor and a capacitor connected to one of a source and a drain of the transistor are arranged on a semiconductor substrate, a storage electrode of the capacitor is provided. It is characterized in that square patterns having a minimum processing size are combined to form a cross shape, and storage electrodes having a separation interval smaller than the minimum processing size are formed.

According to the present invention, in the method of manufacturing a semiconductor memory device having the above structure, a step of forming an element region on the surface of a semiconductor substrate of one conductivity type, and forming a word line and a bit line on the substrate via an insulating film. And a step of forming a contact of the storage electrode on the insulating film, a step of depositing a conductive film to be the storage electrode on the entire surface, and a step of depositing a mask material film for patterning the film on the conductive film. And a step of processing the mask material film into a cross-shaped storage electrode pattern,
The method includes: a step of patterning a conductive film using the processed mask material film; a step of forming a capacitor insulating film on the surface of the processed conductive film; and a step of subsequently forming a capacitor upper electrode. .

[0012]

According to the above structure, since the storage electrode is structured such that it can be separated at the corner portion of the pattern like a cross pattern, the projected area of the separation interval smaller than the minimum processing size and the peripheral length of the planar pattern are large. A storage electrode can be formed. Therefore, it becomes possible to realize the capacitor capacitance required for the DRAM memory at the height of the storage electrode such that it is not difficult to make contact from the wiring above the storage electrode to the layer below the storage electrode.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing a schematic structure of a DRAM according to a first embodiment of the present invention, FIG. 2 (a).
1 is a sectional view taken along the line AA 'in FIG. 1, and FIG. 2B is a sectional view taken along the line BB' in FIG. Element regions 23 (23 ₁ , 23 ₂ ...) Are formed on the p-type silicon substrate 26, and the other regions are separated by field oxide films 29 (29 ₁ , 29 ₂ ...). Word line 20 (20 ₁ , 2
0 ₂ ...) and the bit lines 21 (21 ₁ , 21 ₂ ...) are orthogonal to each other, and the bit lines 21 (21 ₁ , 21 ₂ ...) are connected to the elements via the bit line contacts 24 (24 ₁ , 24 ₂ ...). Connected to the region 23, two MOSs for one element region
Forming a transistor.

The opposite side of the bit line contact of this transistor is connected to the storage electrode contact 25 (25 ₁ , 25
₂ ...) through the storage electrode 22 (22 _1, it has led 22 ₂ ...) and. The storage electrode 22 uses a corner portion of the pattern for separation, thereby forming a storage electrode having a projected area with a separation interval smaller than the minimum processing size and a large peripheral length of the plane pattern. Then, the storage electrode 22 and the insulating film 2
7 and the plate electrode 28 form a capacitor.
In the figure, 100 (100 ₁ , 100 ₂ ...), 101 (101 ₁ , 101)
₂ ...) indicates an interlayer insulating film.

Next, regarding the method of manufacturing the apparatus of this embodiment,
This will be described with reference to FIGS. 3 and 4. Note that FIG. 3 corresponds to a cross section taken along the line AA ′ in FIG. 1, and FIG. 4 corresponds to a cross section taken along the line BB ′ in FIG. 1.

First, as shown in FIG. 3 (a),
A field oxide film 29 for element isolation is formed on the silicon substrate 26 by thermal oxidation. Field ion implantation may be performed to form the element isolation region. Then, channel ion implantation, gate insulating film formation, word line 20 formation are performed in the transistor region, and further source and drain ion implantation is performed.

Next, as shown in FIGS. 3 and 4B, after forming the interlayer insulating film 100, the bit line 21 is formed. Subsequently, as shown in FIG. 3C and FIG. 4C, after the interlayer insulating film 101 is formed, the storage electrode contact 25 is formed.
To form. Further, as shown in FIGS. 3 and 4D, the storage electrode 22 is formed.

Next, a capacitor insulating film 27 and a plate electrode 28 are formed on this, and D as shown in FIGS.
RAM is manufactured.

As described above, according to this embodiment, the storage electrode 2
Since the planar pattern of No. 2 is formed in a cross shape from the conventional rectangle and the adjacent storage electrodes 22 are separated by the corner portion of this cross pattern, it can be seen by comparing the storage electrode patterns of FIG. 1 and FIG. In addition, the area of the storage electrode plane pattern is larger in this embodiment. Furthermore, the cross-shaped pattern also increases the area of the side surface portion. Therefore, the storage capacitance can be increased as compared with the conventional one, and the height of the storage electrode can be lowered to obtain the same storage capacitance as the conventional one.

Here, the area of the storage electrode pattern on the plane is larger than that of the conventional one, in addition to the cross-shaped pattern, the adjacent storage electrodes are separated at the corner portion of the cross pattern. Because. It is obvious that the separation is easier when the corner portions are adjacent to each other than when the edge portions are adjacent to each other. Therefore, according to the present embodiment, the D
The capacitor capacitance required for the RAM cell can be secured, and it becomes easy to contact the wiring below the storage electrode to the layer below the storage electrode.

(Embodiment 2) FIG. 5 is a plan view showing a schematic structure of a second embodiment of the present invention, and FIG.
FIG. 6B is a sectional view taken along the line C-D 'and FIG. Although the basic structure is the same as that of the first embodiment, this embodiment is different from the first embodiment in the relationship between the storage electrode pattern and the contact position.

A device region 33 (3
3 ₁ , 33 ₂ ...) Is formed, and the other regions are separated by field oxide films 39 (39 ₁ , 39 ₂ ...). The word lines 30 (30 ₁ , 30 ₂ ...) And the bit lines 31 (31 ₁ , 31 ₂ ...) Are orthogonal to each other, and the bit lines 31 are bit line contacts 34 (34 ₁ , 34 _2).
,) To the element region 33, and two MOS transistors are formed for one element region.

The opposite side of the bit line contact of this transistor is the storage electrode contact 35 (35 ₁ , 35 ₂ ...)
Is connected to the storage electrodes 32 (32 ₁ , 32 _2, ...) Via the. The storage electrode 32 uses a corner portion of the pattern for separation to form a storage electrode having a large separation pattern influence area smaller than the minimum processing size and a large planar pattern peripheral length. The storage electrode 32, the insulating film 37, and the plate electrode 38 form a capacitor.

Next, the manufacturing method of the apparatus of this embodiment will be described.
This will be described with reference to FIGS. 7 and 8. Note that FIG. 7 corresponds to a cross section CC 'of FIG. 6 and FIG. 8 corresponds to a cross section DD' of FIG.

First, as shown in FIGS. 7 and 8A,
A field oxide film 39 for element isolation is formed on the silicon substrate 36 by thermal oxidation. Field ion implantation may be performed to form this element isolation region. Then, channel ion implantation, gate insulating film formation, word line 30 formation are performed in the transistor region, and further source and drain ion implantation is performed.

Next, as shown in FIGS. 7 and 8B, after forming the interlayer insulating film 102, the bit line 31 is formed. Subsequently, as shown in FIGS. 7 and 8C, after the interlayer insulating film 103 is formed, the storage electrode contact 35 is formed.
To form. Further, as shown in FIGS. 7 and 8D, the storage electrode 32 is formed.

Next, a capacitor insulating film 37 and a plate electrode 38 are formed on this, whereby a DRAM as shown in FIGS. 5 and 6 is manufactured. Even with such a configuration, the area of the storage electrode pattern on the plane and the side wall area can be increased, and the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIG. 9 is a sectional view showing a schematic configuration of a third embodiment of the present invention. The plan view is shown in FIG.
9A is the same as FIG. 9A, and FIG.
FIG. 9B corresponds to a cross section taken along the line DD ′ of FIG.

This embodiment is different from the second embodiment only in the structure of the storage electrode, and the other structure is the same. That is, the plan view of the storage electrode is the same as that of the second embodiment,
An electrode 40 made of polysilicon or the like stands in a cylindrical shape outside the periphery of the pattern of the storage electrodes 32 (32 ₁ , 32 ₂ ...),
It is connected to the portion of the storage electrode plane pattern. However,
In this structure, it is necessary to form the pattern of the storage electrode 32 in a small size by optimizing the exposure time of the resist so as not to connect with the adjacent storage electrode.

Next, the manufacturing method of the apparatus of this embodiment will be described.
This will be described with reference to FIGS. 10 and 11. Note that FIG. 10 shows a cross section corresponding to FIG. 9A and FIG. 11 shows a cross section corresponding to FIG. 9B.

The process is the same as that of the second embodiment until the interlayer film on the bit line is formed and the storage electrode contact is formed. Next, as shown in FIG. 10 and FIG. 11A, after forming the storage electrode contact 35, polysilicon is deposited and arsenic or phosphorus is doped, and then CV
A D-SiO ₂ film 41 is deposited. And this CVD-
The resist 4 is used as a mask for patterning the SiO ₂ film 41.
2 is exposed.

Then, as shown in FIG. 10 and FIG. 11B, CVD-SiO is performed by using the register 42 as a mask.
_{2 The} film 41 and the polysilicon thereunder are anisotropically etched, and then polysilicon is deposited and doped with arsenic or phosphorus. Subsequently, as shown in FIG. 10 and FIG. 11C, the polysilicon on the entire surface is anisotropically etched to leave a polysilicon crown structure 40. Then CVD
The —SiO ₂ film 41 is isotropically etched with NH ₄ F or the like.

Then, a capacitor insulating film 37 and a plate electrode 38 are formed on this, whereby a DRAM as shown in FIG. 9 is manufactured. With this configuration,
Of course, the same effect as that of the first embodiment can be obtained.
The side wall area of the storage electrode can be increased, which is effective in expanding the storage capacitance.

(Embodiment 4) FIG. 12 is a sectional view showing a schematic structure of a fourth embodiment of the present invention. The plan view is the same as FIG. 5, and FIG. 12A corresponds to a cross section taken along the line CC ′ of FIG. 5, and FIG. 12B corresponds to a cross section taken along the line DD ′ of FIG. .

This embodiment differs from the second embodiment in the structure of the storage electrode. That is, the plan view of the storage electrode is the same as that of the second embodiment, but the storage electrode 32 (32 ₁ , 32 ₂ ...)
An electrode made of polysilicon or the like stands in a cylindrical shape inside the periphery of the pattern, and is connected to the portion of the storage electrode plane pattern. However, in this structure, it is necessary to optimize the exposure time of the resist for the pattern of the storage electrode 32 so as not to connect with the adjacent storage electrode.

Next, the manufacturing method of the device of this embodiment will be described.
This will be described with reference to FIGS. 13 and 14. Note that FIG. 13 shows a cross section corresponding to FIG. 12A and FIG. 14 shows a cross section corresponding to FIG.

The process is the same as that of the second embodiment until the interlayer film on the bit line is formed and the storage electrode contact is formed. Next, as shown in FIGS. 13 and 14A, after forming the storage electrode contact 35, polysilicon or the like is deposited, arsenic or phosphorus is doped, and the entire surface is anisotropically etched. The storage electrode contact 35 is filled with polysilicon or the like. Then, the CVD-SiO ₂ film 4
1 is deposited. Then, the register 42 is exposed with a mask for patterning the CVD-SiO ₂ film 41.

Next, as shown in FIG. 13 and FIG. 14B, CVD-SiO is formed by using this resist 42 as a mask.
_{2 The} film 41 is anisotropically etched, polysilicon is subsequently deposited, and arsenic or phosphorus is doped. Subsequently, as shown in FIGS. 13 and 14C, the polysilicon on the entire surface is anisotropically etched. When performing this anisotropic etching, an insulating film or the like may be embedded in the groove in order to leave the polysilicon at the bottom of the groove. After that, CVD-
The SiO ₂ film 41 is isotropically etched by NH ₄ F or the like.

Then, a capacitor insulating film 37 and a plate electrode 38 are formed on this, whereby a DRAM as shown in FIG. 12 is manufactured. With such a configuration, the side wall area of the storage electrode can be made larger as in the third embodiment, which is effective in expanding the storage capacitance.

(Embodiment 5) FIG. 15 is a plan view showing a schematic configuration of a fifth embodiment of the present invention, and FIG. 16 is a view E-in FIG.
It is an E'sectional view. In this embodiment, the bit line is formed above the storage electrode. That is, the bit line 14
From (14 ₁ , 14 ₂ ...) To the element region 15 (15 ₁ , 15 2
₂ )) via the bit line contacts 16 (16 ₁ , 16 ₂ ...) so as to be insulated from the storage electrodes 11 (11 ₁ , 11 ₂ ...) and the word lines 13 (13 ₁ , 13 ₂ ...). To make contact.

[0042] In the drawing, 12 (12 _1, 12 ₂ ...) of the storage electrode contact, 17 (17 _1, 17 ₂ ...) of the plate electrode, 18 (18 _1, 18 ₂ ...), 19 (19 _1, 1
9 ₂ ...) indicates an interlayer insulating film.

Even with such a structure, by forming the storage electrodes in a cross pattern and using the corner portions of the patterns for separating the storage electrodes, as in the first embodiment,
The capacitor capacitance required for the DRAM cell can be secured without increasing the height of the storage electrode so much that it becomes easy to make a contact from the wiring above the storage electrode to the layer below the storage electrode.

In each of the above-mentioned embodiments, the plane pattern of the storage electrode has a cross shape, but the shape is not limited to the cross shape, and any structure that can be separated at the corner portion of the pattern may be used. The element structure and the manufacturing method are not limited to those shown in the embodiments, and various modifications can be carried out without departing from the scope of the present invention.

By the way, when the storage electrode pattern (cross shape) in the above-mentioned embodiment is formed by photolithography, it becomes difficult to form it with high resolution as the pattern becomes smaller. Therefore, in the following examples, a capacitor pattern was formed using a phase shift mask.

(Embodiment 6) FIGS. 17 and 18 are for explaining a sixth embodiment. FIG. 17 is a plan view of a pattern of a phase shifter of an (H type) phase shift mask, and FIG.
FIG. 18A shows a finished SN-shaped plane pattern formed by using this phase shift mask, and FIG. 18B shows a bird's eye view thereof.

By using the phase shifter 61 as shown in FIG. 17, the phase is rotated by 180 ° and the phase shifter 61 is rotated.
The light intensity becomes 0 along the edge of. Therefore, by using the negative resist, the resist is removed along the edge of the phase shifter 61 and a fine space is formed. This is a so-called edge-based phase shift mask. If you use an excimer, stepper, etc.
A space of 0.2 μm is realized. As a result, FIG.
The shape of the storage electrode (SN) 62 as shown in (a) and (b) is realized.

Since this SN shape has a peripheral length about twice as long as that of the conventional simple SN structure, Cs becomes twice as large when compared at the same SN height and the same capacitor insulating film thickness.
That is, twice as many Cs can be obtained in the same number of steps as forming a conventional simple SN structure. This Cs is equal to or higher than that of a crown structure having many steps, in which the number of capacitor steps is almost doubled. This is clear when the H of the simple SN structure and the C of the conventional type are compared from the characteristics of FIG. 19 (changes in storage capacity with respect to design rules in various SN structures).

Further, thin polycrystalline silicon is formed, and then a structure as shown in FIG. 18B is once formed with a CVD oxide film or the like, and then polycrystalline silicon is deposited on the entire surface and reactive ion etching or the like is performed. The side wall is left by
It is also possible to form an H-shaped crown structure as in (c). When this structure is used, the peripheral length is almost doubled, and as shown in FIG. 19, doubled Cs is obtained.

(Embodiment 7) FIG. 20 is a plan view of various patterns of the phase shifter of the phase shift mask of the seventh embodiment (fence type) of the present invention, and FIG. FIG. 21B shows the bird's-eye view of the finished SN-shaped plane pattern formed.

20A, 20B and 20C, any shifter pattern may be used. Which one to use can be decided depending on the ease of processing the shifter, the ease of pattern / data processing, and the like.

In this SN shape, the peripheral length is almost double that of the conventional structure, and Cs has a value slightly less than double. In addition, FIG.
When combined with a crown structure as shown in (c), a further doubled Cs is obtained.

(Embodiment 8) FIG. 22 is a plan view of various patterns of the phase shifter of the phase shift mask of the eighth embodiment (cross shape) of the present invention, and FIG. 23A shows the case where this phase shift mask is used. FIG. 23 (b) shows a bird's-eye view of the finished SN-shaped plane pattern formed.

22 (a) (b) (c) Any shifter pattern may be used. In this SN shape, the peripheral length is only 15 to 30% up of the conventional structure, but Cs
Will increase by that amount. Further, when a crown structure as shown in FIG. 23 (c) is combined, an even more doubled Cs can be obtained.

FIG. 24A shows an H-type SN in the case of a 1/2 pitch held bit line type layout.
2 shows the layout of the SN radish 4 and the BL radish 3. FIG. 24B shows the H-type SN2 in the case of the 1/4 pitch held bit line layout.
The layouts of the SN radish 4 and the BL radish 3 are shown.

The above embodiment describes the pattern applied to the layout of the 8F ² (F: design rule) type cell, but the 6F ² type such as the open bit line system, and further the 4F ² type. It is equally applicable to layouts.

FIG. 25 is for explaining still another example (crown structure). (A) and (b) are plan views of the phase shifter of the phase shift mask, and (c) is formed using this mask. The finished SN-shaped plane pattern is shown in FIG. FIG. 25A shows a mask for a positive type resist, and FIG. 25B shows a mask for a negative type resist. The crown structure can be realized by the same number of steps as the simple SN structure.

The SN electrode in the above embodiments may be made of metal such as W or Cu other than polycrystalline silicon.
Further, it may be a single layer or a laminated layer. The capacitor insulating film may be made of any material such as NO film, Ta ₂ O ₅ film and ferroelectric film. Similarly, the material of the plate electrode does not matter.

[0059]

As described above in detail, according to the present invention, by using the corner portion of the pattern for the separation between the storage electrodes of the memory cells, the projected area of the separation distance smaller than the minimum processing dimension and the planar pattern peripheral length are obtained. To form a large storage electrode. Therefore, the capacitor capacitance required for the DRAM cell can be secured without increasing the height of the storage electrode so much that it is not difficult to make contact from the wiring above the storage electrode to the layer below the storage electrode. It is possible to realize a semiconductor memory device having a planar pattern of storage electrodes.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of a DRAM according to a first embodiment.

FIG. 2 is a sectional view taken along the line AA ′ and BB ′ of FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment.

FIG. 5 is a plan view showing a schematic configuration of a second embodiment.

6 is a sectional view taken along the line CC ′ and DD ′ of FIG.

FIG. 7 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the second embodiment.

FIG. 9 is a sectional view showing a schematic configuration of a third embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the third embodiment.

FIG. 12 is a sectional view showing a schematic configuration of a fourth embodiment.

FIG. 13 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 14 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 15 is a plan view showing a schematic configuration of a fifth embodiment.

16 is a cross-sectional view taken along the line EE ′ of FIG.

FIG. 17 is a plan view showing a shifter pattern of a phase shift mask of a sixth embodiment (H type).

18 is a view showing an SN shape pattern formed using the phase shift mask of FIG.

FIG. 19 is a characteristic diagram showing the relationship between the design rule and the storage capacity.

FIG. 20 is a plan view showing a shifter pattern of a phase shift mask of a seventh embodiment (fence type).

FIG. 21 is a diagram showing an SN shape pattern formed using the phase shift mask of FIG. 20.

FIG. 22 is a plan view showing a shifter pattern of a phase shift mask of the eighth embodiment (cross type).

23 is a diagram showing an SN shape pattern formed using the phase shift mask of FIG. 22.

FIG. 24 is a diagram showing a layout of an H-type SN, SN radish, and BL radish in the case of a held bit line type layout.

FIG. 25 is a view for explaining the phase shift mask of the ninth embodiment (crown structure).

FIG. 26 is a plan view showing a conventional DRAM structure.

27 is a cross-sectional view taken along the line FF ′ of FIG.

[Explanation of symbols]

21 (21 ₁ , 21 ₂ ...) Bit line 22 (221 ₁ , 22 ₂ ...) Storage electrode 23 (231 ₁ , 23 ₂ ...) Element region 24 (24 ₁ , 25 ₂ ...) Bit line contact 25 (25 ₁ , 25 ₂ ...) Storage electrode contact 26 ... P-type silicon substrate 27 (27 ₁ , 27 ₂ ...) Insulating film 28 ... Plate electrode 29 (29 ₁ , 29 ₂ ...) Field oxide film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Hashimoto 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute

Claims (3)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells each having a MOS transistor and a capacitor connected to one of a source and a drain of the transistor formed on a semiconductor substrate, wherein a storage electrode of the capacitor is separated. A semiconductor memory device characterized in that a storage electrode having a separation interval smaller than a minimum processing size is formed by using a corner portion of a pattern. 2. A step of forming an element region on the surface of a semiconductor substrate of one conductivity type, a word line on the substrate via an insulating film,
A step of forming a bit line, a step of forming a contact of a storage electrode on the insulating film, a step of depositing a conductive film to be a storage electrode on the entire surface, and a mask for patterning the film on the conductive film. A step of depositing a material film, a step of processing the mask material film into a cross-shaped storage electrode pattern, a step of patterning the conductive film using the processed mask material film, and a surface of the processed conductive film A method of manufacturing a semiconductor memory device, comprising: a step of forming a capacitor insulating film on the substrate, and then a step of forming a capacitor upper electrode. 3. A method of manufacturing a semiconductor memory device according to claim 2, wherein an edge-using phase shift mask is used when patterning the mask material film.