JPH06112628A - Manufacture of circuit board having wiring pattern - Google Patents

Manufacture of circuit board having wiring pattern

Info

Publication number
JPH06112628A
JPH06112628A JP27946892A JP27946892A JPH06112628A JP H06112628 A JPH06112628 A JP H06112628A JP 27946892 A JP27946892 A JP 27946892A JP 27946892 A JP27946892 A JP 27946892A JP H06112628 A JPH06112628 A JP H06112628A
Authority
JP
Japan
Prior art keywords
film
conductive film
solder
wiring pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27946892A
Other languages
Japanese (ja)
Inventor
Eisaku Miyauchi
栄作 宮内
Masayuki Yoshida
政幸 吉田
Akihiro Hotta
哲広 堀田
Genichi Watanabe
源一 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP27946892A priority Critical patent/JPH06112628A/en
Publication of JPH06112628A publication Critical patent/JPH06112628A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To form fine wiring patterns including land parts with narrow pitches and, further, form proper and highly accurate solder films for soldering of a surface mount component on the land parts of the wiring patterns. CONSTITUTION:A foundation film 2 made of active metal material and a conducting film 3 are built up on the surface of a board 1 by sputtering or vacuum deposition. A resist film 4 is applied to the conducting film 3 and exposed and developed to form through-holes having required patterns. Conducting layers 6 and metal plating films 7 such as solder films are formed in the through-holes 5. Then the resist film 4 is removed and the surplus foundation film 2 and conducting film 3 are removed from the surface of the board 1 by etching with the metal plating films 7 such as the solder films as metal masks. The metal plating films which are used as the metal masks are totally removed or the parts of the solder films 7 are left on the land parts and the other parts are removed from the surfaces of the wiring patterns 3 and 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、表面実装部品の狭ピッ
チ化,多ピン化に対応するファインな配線パターンを有
する回路基板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board having a fine wiring pattern, which is suitable for narrowing the pitch and increasing the pin count of surface mount components.

【0002】[0002]

【従来の技術】一般に、配線パターンを回路基板の板面
に形成するにはメッシュスクリーンやメタルスクリーン
を用いてペースト状の導電材料を印刷することによるス
クリーン印刷法が適用されている。然し、このスクリー
ン印刷法では導電材料の性状,スクリーンの材質,厚
み,開口部精度,印刷される基板の反り,ねじれ,印刷
機の精度,印刷するときのスピード,印刷圧等の要因を
複雑に交絡させなければファインな導電パターンを形成
することができない。特に、半導体部品の狭ピッチ化,
多ピン化の進行で0.5mmピッチから0.3mmピッチに
向けて対応するファインなランドパターンを形成するの
は困難である。
2. Description of the Related Art Generally, in order to form a wiring pattern on a plate surface of a circuit board, a screen printing method is applied by printing a paste-like conductive material using a mesh screen or a metal screen. However, in this screen printing method, factors such as the characteristics of the conductive material, the material of the screen, the thickness, the accuracy of the opening, the warp and twist of the printed substrate, the accuracy of the printing machine, the speed of printing, the printing pressure, etc. are complicated. A fine conductive pattern cannot be formed unless they are entangled. In particular, narrowing the pitch of semiconductor parts,
As the number of pins increases, it is difficult to form a fine land pattern corresponding to a pitch of 0.5 mm to 0.3 mm.

【0003】また、表面実装部品の半田付けにあたって
はクリームはんだを配線パターンのランド部に予め付着
し、そのクリームはんだに外部電極を接触させて表面実
装部品を仮止め固定後、リフロー炉に通過することによ
るリフローソルダリング等が通常適用されている。この
クリームはんだをランド部に付着するにはディスペンサ
ー塗布やスクリーン印刷が適用されているが、その塗布
にあたっても、上述した各種の要因の他にはんだ粒のメ
ッシュ,フラックス含有量,クリームはんだの粘度等の
要因を複雑に交絡させねばならないから、0.3mmピッ
チに対応するには極めて困難が伴う。殊に、クリームは
んだを用いるときにははんだボールがリフロー時に発生
し易く、そのはんだボールによる短絡等の半田付け不良
が0.3mmピッチになると増大する虞れがある。
When soldering the surface mount component, cream solder is previously attached to the land portion of the wiring pattern, external electrodes are brought into contact with the cream solder to temporarily fix the surface mount component, and then the solder paste is passed through a reflow furnace. Reflow soldering, etc. is usually applied. To apply this cream solder to the land, dispenser coating or screen printing is applied. In addition to the above-mentioned various factors, solder mesh, flux content, viscosity of cream solder, etc. Since the above factors must be complicatedly entangled, it is extremely difficult to cope with the 0.3 mm pitch. In particular, when cream solder is used, solder balls are likely to occur during reflow, and soldering defects such as short circuits due to the solder balls may increase when the pitch is 0.3 mm.

【0004】[0004]

【発明が解決しようとする課題】本発明は、狭間なピッ
チのランド部を含めて配線パターンをファインに形成す
ると共に、表面実装部品のはんだ付け用はんだ膜を配線
パターンのランド部に適正で高精度なものに形成できる
よう工夫した配線パターンを有する回路基板の製造方法
を提供することを目的とする。
SUMMARY OF THE INVENTION According to the present invention, a wiring pattern is finely formed including land portions having a narrow pitch, and a solder film for soldering surface mount components is properly and highly formed on the land portion of the wiring pattern. An object of the present invention is to provide a method for manufacturing a circuit board having a wiring pattern devised so as to be formed with high accuracy.

【0005】[0005]

【課題を解決するための手段】本発明の請求項1に係る
配線パターンを有する回路基板の製造方法においては、
セラミック基板,ポリイミド基板等の不純ガスが生じな
い板材を基板とし、その基板の板面にCr,Ti等の活
性な金属材料で下地膜と共に、該下地膜に積層させてC
u等の導電性を有する金属材料で導電膜をスパッタリン
グまたは真空蒸着で形成し、その後にレジストフィルム
を前記導電膜に被着させて露光,現象プロセスによる所
定パターンの抜き穴をフィルム面に形成し、この抜き穴
の内部に露出位置する導電膜に積層させて金属メッキ膜
を前記所定パターンの抜き穴に応じて形成し、その後に
レジストフィルムを剥離すると共に、前記金属メッキ膜
をメタルマスクとして余剰な導電膜並びに下地膜を基板
の板面からエッチング除去し、更に、残る導電膜上の金
属メッキ膜を剥離することによりファインな配線パター
ンを形成するようにされている。
In a method of manufacturing a circuit board having a wiring pattern according to claim 1 of the present invention,
A plate material that does not generate an impure gas, such as a ceramic substrate or a polyimide substrate, is used as a substrate, and an active metal material such as Cr or Ti is laminated on the plate surface of the substrate together with the underlying film to form C.
A conductive film is formed by sputtering or vacuum evaporation with a conductive metal material such as u, and then a resist film is applied to the conductive film to form a predetermined pattern of holes on the film surface by exposure and a phenomenon process. , A metal plating film is formed on the exposed conductive film inside the hole according to the hole having the predetermined pattern, and then the resist film is peeled off, and the metal plating film is used as a metal mask to make an excess. The conductive film and the base film are removed by etching from the plate surface of the substrate, and the metal plating film on the remaining conductive film is peeled off to form a fine wiring pattern.

【0006】同請求項2に係る配線パターンを有する回
路基板の製造方法においては、請求項1における抜き穴
の内部に露出位置する導電膜に積層させて、膜厚を増加
する同材質の金属材料を導電層として電解メッキで形成
するようにされている。
In the method of manufacturing a circuit board having a wiring pattern according to the second aspect of the present invention, the metal material of the same material is laminated on the conductive film exposed inside the hole of the first aspect to increase the film thickness. As a conductive layer is formed by electrolytic plating.

【0007】同請求項3に係る配線パターンを有する回
路基板の製造方法においては、セラミック基板,ポリイ
ミド基板等の不純ガスが生じない板材を基板とし、その
基板の板面にCr,Ti等の活性な金属材料で下地膜と
共に、該下地膜に積層させてCu等の導電性を有する金
属材料で導電膜をスパッタリングまたは真空蒸着で形成
し、その後にレジストフィルムを前記導電膜に被着させ
て露光,現象プロセスによる所定パターンの抜き穴をフ
ィルム面に形成し、この抜き穴の内部に露出位置する導
電膜に積層させてはんだ膜を前記所定パターンの抜き穴
に応じてメッキ処理で形成し、その後にレジストフィル
ムを剥離すると共に、前記はんだ膜をメタルマスクとし
て余剰な導電膜並びに下地膜を基板の板面からエッチン
グ除去し、更に、残る導電膜上のはんだ膜をランド部に
残存させて他の導電膜から剥離することによりはんだ膜
をランド部に備えたファインな配線パターンを形成する
ようにされている。
In the method for manufacturing a circuit board having a wiring pattern according to the third aspect, a plate material such as a ceramic substrate or a polyimide substrate which does not generate an impure gas is used as a substrate, and the plate surface of the substrate is made of an active material such as Cr or Ti. Of a metallic material together with a base film, and by laminating on the base film, a conductive film is formed by sputtering or vacuum deposition with a conductive metal material such as Cu, and then a resist film is attached to the conductive film to expose. , Punching holes with a predetermined pattern by the phenomenon process are formed on the film surface, and a solder film is formed by laminating on the conductive film exposed inside the punching holes by plating according to the holes with the predetermined pattern, and then The resist film is peeled off, and the excess conductive film and the base film are removed by etching from the plate surface of the substrate by using the solder film as a metal mask. It is adapted to form a fine wiring pattern with a solder layer on the land portion of the solder film on the conductive film is left on the land portions by peeling from the other conductive film that.

【0008】同請求項4に係る配線パターンを有する回
路基板の製造方法においては、請求項3における抜き穴
の内部に露出位置する導電膜に積層させて、膜厚を増加
する同材質の金属材料を電解メッキで形成するようにさ
れている。
According to a fourth aspect of the present invention, there is provided a method of manufacturing a circuit board having a wiring pattern, wherein the metal material of the same material is laminated on the conductive film exposed inside the hole to increase the film thickness. Is formed by electrolytic plating.

【0009】同請求項5に係る配線パターンを有する回
路基板の製造方法においては、請求項3または4におけ
る抜き穴の内部に露出位置する導電膜に積層させて、S
nPb等のはんだ膜を無電解メッキで析出形成するよう
にされている。
In the method of manufacturing a circuit board having a wiring pattern according to the fifth aspect, S is formed by stacking on the conductive film exposed inside the punched hole in the third or fourth aspect.
A solder film of nPb or the like is deposited and formed by electroless plating.

【0010】同請求項6に係る配線パターンを有する回
路基板の製造方法においては、請求項3または4におけ
る抜き穴の内部に露出位置する導電膜に積層させて、N
i等のバリア層を介し、SnPb等のはんだ膜を電解メ
ッキで析出形成するようにされている。
In the method of manufacturing a circuit board having a wiring pattern according to the sixth aspect, N is laminated on the conductive film exposed inside the punched hole in the third or fourth aspect.
A solder film of SnPb or the like is deposited by electrolytic plating through a barrier layer of i or the like.

【0011】[0011]

【作用】本発明の請求項1に係る配線パターンを有する
回路基板の製造方法では、活性な金属材料を下地膜とし
て導電膜をスパッタリングまたは真空蒸着で形成するこ
とから、当該導電膜から最終的に得られる配線パターン
を基板面に高強度に密着させて形成でき、その導電膜の
スパッタリングまたは真空蒸着の際にはセラミック基
板,ポリイミド基板等の不純ガスを生じない板材を基板
とすることから導電膜の形成に悪影響を及ぼすこともな
い。また、この導電膜による配線パターンはレジストフ
ィルムに設けられる所定パターンの抜き穴を応用し、そ
の抜き穴の内部に露出位置する導電膜に積層成形する金
属メッキ膜をメタルマスクとし、余剰の導電膜を基板の
板面から下地膜と共にエッチング除去することにより形
成するから、狭間ピッチのランド部を有する配線パター
ンでもレジストフィルムの露光,現像技術でファインな
ものに形成することができる。
In the method of manufacturing a circuit board having a wiring pattern according to the first aspect of the present invention, since the conductive film is formed by sputtering or vacuum evaporation using an active metal material as a base film, the conductive film is finally formed from the conductive film. The obtained wiring pattern can be formed by closely adhering to the substrate surface, and a plate material that does not generate an impure gas such as a ceramic substrate or a polyimide substrate when the conductive film is sputtered or vacuum-deposited is used as the substrate. There is no adverse effect on the formation of. The wiring pattern of the conductive film is formed by applying a predetermined pattern of holes formed in the resist film, and the metal plating film to be laminated and formed on the conductive film exposed inside the hole is used as a metal mask. Is formed by etching and removing from the plate surface of the substrate together with the base film. Therefore, even a wiring pattern having land portions with a narrow pitch can be formed finely by the exposure and development techniques of the resist film.

【0012】本発明の請求項2に係る配線パターンを有
する回路基板の製造方法では、スパッタリングまたは真
空蒸着で形成された導電膜の膜厚を増加することによ
り、その導電膜による配線パターンを小さな電気抵抗の
膜厚に形成することができる。
In the method of manufacturing a circuit board having a wiring pattern according to the second aspect of the present invention, the film thickness of the conductive film formed by sputtering or vacuum deposition is increased, so that the wiring pattern formed by the conductive film can be formed into a small electrical pattern. It can be formed to have a resistance film thickness.

【0013】本発明の請求項3に係る配線パターンを有
する回路基板の製造方法では、請求項1に係る方法と同
じ作用を奏することにより、表面実装部品のはんだ付け
用はんだ膜を狭間ピッチのランド部にも極めてファイン
に形成できるばかりでなく、そのはんだ膜をメッキ膜と
して形成することから平滑面に形成できてはんだボール
が生ずるのも防げる。
In the method of manufacturing a circuit board having a wiring pattern according to a third aspect of the present invention, the solder film for soldering of surface-mounted components is landed at a narrow pitch by performing the same operation as the method according to the first aspect. Not only can it be formed extremely finely on the portion, but since the solder film is formed as a plating film, it can be formed on a smooth surface and the generation of solder balls can be prevented.

【0014】本発明の請求項4に係る配線パターンを有
する回路基板の製造方法では、表面実装部品のはんだ付
け用のはんだ膜をランド部に備える配線パターンを形成
するときでも、請求項2に係る方法と同じ作用を奏する
ことにより、配線パターンを小さな電気抵抗の膜厚に形
成することができる。
In the method for manufacturing a circuit board having a wiring pattern according to a fourth aspect of the present invention, the wiring pattern having a land with a solder film for soldering surface mount components is formed according to the second aspect. By performing the same operation as the method, the wiring pattern can be formed to have a small film thickness with electric resistance.

【0015】本発明の請求項5,6に係る配線パターン
を有する回路基板の製造方法では無電解または電解メッ
キによるはんだ膜を形成するから、表面実装部品のはん
だ付け用はんだ膜を極めて平滑面に形成できてはんだボ
ールの発生も防げる。また、導電膜の膜厚を増加する工
程と一連にはんだ膜をメッキ処理で形成することから工
程を複雑化するのも避けられる。
In the method for manufacturing a circuit board having a wiring pattern according to the fifth and sixth aspects of the present invention, since a solder film is formed by electroless or electrolytic plating, the soldering solder film of the surface mount component has an extremely smooth surface. It can be formed and the generation of solder balls can be prevented. Further, since the solder film is formed by plating in series with the step of increasing the thickness of the conductive film, it is possible to avoid complicating the step.

【0016】[0016]

【実施例】以下、添付図面を参照して説明すれば、図
1,2は表面実装部品のはんだ付け用はんだ膜をランド
部に備えた配線パターンを最終工程で基板面に形成する
実施例を示す。また、図1,2ははんだ膜の形成工程で
無電解メッキ処理によるか或いは電解メッキ処理による
かで異なる実施例を示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, FIGS. 1 and 2 show an embodiment in which a wiring pattern having a solder film for soldering surface mount components on a land portion is formed on a substrate surface in a final step. Show. 1 and 2 show different embodiments depending on whether electroless plating or electrolytic plating is used in the solder film forming process.

【0017】図1は上述したはんだ膜を無電解メッキで
形成する工程を含む一連の製造工程を示すものであり、
これに基づいて配線パターンを有する回路基板の製造方
法を説明する。
FIG. 1 shows a series of manufacturing steps including a step of forming the above-mentioned solder film by electroless plating.
Based on this, a method of manufacturing a circuit board having a wiring pattern will be described.

【0018】まず、第一の工程ではアルミナ基板等のセ
ラミック基板またはフレキシブルなポリイミド基板1を
用いて、下地膜2並びに導電膜3をスパッタリングまた
は真空蒸着で形成する。そのうち、下地膜2はCr,T
i等の活性な金属材料から500〜1000Å程度の膜
厚に形成され、この下地膜2で導電膜3の基板1に対す
る密着強度を向上することができる。導電膜3はCu等
の導電性を有する金属材料から数1000Å,例えば5
000Å程度の膜厚に形成されている。この工程中でス
パッタリングまたは真空蒸着を適用しても、セラミック
基板やポリイミド基板1の如き不純ガスが生じない基板
を選択することにより、配線パターンとして最終工程で
形成される導電膜3に悪影響を与えることがない。
First, in the first step, a base film 2 and a conductive film 3 are formed by sputtering or vacuum evaporation using a ceramic substrate such as an alumina substrate or a flexible polyimide substrate 1. Among them, the base film 2 is made of Cr, T
It is formed from an active metal material such as i to a film thickness of about 500 to 1000 Å, and this base film 2 can improve the adhesion strength of the conductive film 3 to the substrate 1. The conductive film 3 is made of a conductive metal material such as Cu and has a thickness of several thousand Å, for example, 5
It is formed with a film thickness of about 000Å. Even if sputtering or vacuum deposition is applied in this step, by selecting a substrate such as a ceramic substrate or a polyimide substrate 1 which does not generate an impure gas, the conductive film 3 formed in the final step as a wiring pattern is adversely affected. Never.

【0019】次に、レジストフィルム4を導電膜3に重
ねて貼り、そのフィルム面に露光,現像プロセスを経て
所定パターンの抜き穴5を形成する。このレジストフィ
ルム4としては30〜50μ程度のフィルム厚を有する
ドライフィルムを用い、また、抜き穴5は所定の透光パ
ターンを有するフォトマスキングをレジストフィルム4
のフィルム面に被せて光線の照射処理を行うことにより
形成できる。その抜き穴5は最終工程で得られる配線パ
ターンと同じパターンに形成され、狭間ピッチのランド
部を含む配線パターンに応じても正確に形成することが
できる。この抜き穴5を形成することにより、抜き穴5
の内部には導電膜3が露出位置する。
Next, a resist film 4 is laminated on the conductive film 3, and a hole 5 having a predetermined pattern is formed on the film surface through an exposure and development process. As the resist film 4, a dry film having a film thickness of about 30 to 50 μm is used, and the holes 5 are formed by photomasking having a predetermined light transmitting pattern.
It can be formed by covering the film surface of the above with a light irradiation treatment. The punched holes 5 are formed in the same pattern as the wiring pattern obtained in the final step, and can be accurately formed even in accordance with a wiring pattern including land portions with a narrow pitch. By forming this hole 5, the hole 5
The conductive film 3 is exposed inside.

【0020】レジストフィルム4の抜き穴によるパター
ニングの後、導電膜3と同じCu等の導電性金属材料で
導電膜3の膜厚を増加する導電層6を電解メッキで形成
する。その導電層6は配線パターンの電気抵抗に鑑みて
導電膜3の厚みを30〜50μ程度の厚みで増加するも
のであり、導電膜3の膜厚のみによる電気抵抗が大きく
なければ導電層6を形成するのを省略することができ
る。この導電層6を介し、SnPb等のはんだ膜7を無
電解メッキで20μ厚み程度析出形成する。そのはんだ
膜7を含めて、導電層6を抜き穴5の内部で導電膜3に
積層させて形成する。
After patterning the resist film 4 by the punching holes, a conductive layer 6 for increasing the film thickness of the conductive film 3 is formed by electrolytic plating with the same conductive metal material as Cu such as the conductive film 3. In consideration of the electric resistance of the wiring pattern, the conductive layer 6 increases the thickness of the conductive film 3 by a thickness of approximately 30 to 50 μm. It can be omitted. A solder film 7 of SnPb or the like is deposited and formed to a thickness of about 20 μm by electroless plating via the conductive layer 6. The conductive layer 6 including the solder film 7 is formed by laminating it on the conductive film 3 inside the hole 5.

【0021】この電解メッキに代えて、はんだ膜7を形
成するには電解メッキを適用することができる。その場
合には導電膜3乃至は導電層6のはんだ喰れを防ぐべ
く、図2の実施例で示す如くはんだバリア層としてNi
等のメッキ膜8を1〜2μ以上の膜厚で形成した後、S
nPb等のはんだ膜7を電解メッキ処理で形成するとよ
い。
Instead of this electrolytic plating, electrolytic plating can be applied to form the solder film 7. In that case, in order to prevent the conductive film 3 or the conductive layer 6 from being soldered, Ni is used as a solder barrier layer as shown in the embodiment of FIG.
After forming the plating film 8 of 1 to 2 .mu.
The solder film 7 of nPb or the like may be formed by electrolytic plating.

【0022】はんだ膜7の形成後にレジストフィルム4
を剥離することにより、導電膜3に積層形成された各膜
6,7または8を基板1の板面上で外部に露出させる。
この基板1に対してははんだ膜7をメタルマスクとして
余剰な導電膜3並びに下地膜2をウエットエッチングで
基板面から除去する処理を加え、はんだ膜7に応じた配
線パターンを導電膜3,導電層6で形成する。そのはん
だ膜7は配線パターン3,6のランド部のみに残し、他
のパターン面からは剥離する。このはんだ膜7の剥離
は、レジストをランド部乃至はランド間に予め塗布した
後、ウエットエッチングを適用すれば容易に行うことが
できる。
After forming the solder film 7, the resist film 4 is formed.
By peeling off, each of the films 6, 7 or 8 laminated on the conductive film 3 is exposed to the outside on the plate surface of the substrate 1.
The substrate 1 is subjected to a process of removing the excess conductive film 3 and the base film 2 from the substrate surface by wet etching using the solder film 7 as a metal mask, and a wiring pattern corresponding to the solder film 7 is formed into the conductive film 3 and the conductive film. Formed in layer 6. The solder film 7 is left only on the land portions of the wiring patterns 3 and 6 and peeled off from the other pattern surfaces. The peeling of the solder film 7 can be easily performed by applying wet etching after applying a resist in advance between the land portions or between the lands.

【0023】このようにして配線パターン3,6を基板
1の板面上に形成すると、レジストフィルム4を用いた
露光,現象プロセスによる高精度なパターンニングで
0.3mmピッチ以下のランドパターンを有する配線パタ
ーン3,6でも極めてファインに形成できる。また、そ
の配線パターン3,6は活性な金属材料の下地膜2をベ
ースに形成されているから、高い密着強度を持って基板
1の板面上に形成することができる。
When the wiring patterns 3 and 6 are formed on the plate surface of the substrate 1 in this way, a land pattern having a pitch of 0.3 mm or less is formed by highly accurate patterning by exposure using the resist film 4 and a phenomenon process. Even the wiring patterns 3 and 6 can be formed extremely finely. Further, since the wiring patterns 3 and 6 are formed on the base film 2 of an active metal material as a base, they can be formed on the plate surface of the substrate 1 with high adhesion strength.

【0024】はんだ膜7はメッキ処理で形成されている
から、表面を凹凸のない平滑面に形成できて、表面実装
部品の端子浮き等が生ずるのを防げる。また、はんだボ
ールがリフロー時に発生することがないため、狭間ピッ
チのランド部でも電気的な短絡現象が生ずるのを防ぐこ
とができる。更に、クリームはんだの印刷によらないで
はんだ膜7を形成できるから、品種換え時に要する段取
り時間や条件設定時間等を削減できることを含めて全体
的にコストの低減を図ることができる。
Since the solder film 7 is formed by the plating process, the surface can be formed as a smooth surface having no unevenness, and it is possible to prevent terminal floating or the like of the surface mount component. Further, since solder balls are not generated during reflow, it is possible to prevent an electrical short circuit phenomenon from occurring in the land portion having a narrow pitch. Furthermore, since the solder film 7 can be formed without printing with cream solder, it is possible to reduce the overall cost, including the reduction of setup time and condition setting time required when changing the type of product.

【0025】この配線パターンを有する回路基板は、図
3で示すように配線パターン3,6のランド部に形成さ
れたはんだ膜7を覆うようフラックス9をベタ塗り或い
は印刷で付着し、そのはんだ膜7に対応位置させて表面
実装部品Eの外部端子を配置することにより仮止めした
後、リフロー炉に送り込んで表面実装部品Eをはんだ付
け固定するよう用いることができる。
On the circuit board having this wiring pattern, the flux 9 is applied by solid coating or printing so as to cover the solder film 7 formed on the lands of the wiring patterns 3 and 6 as shown in FIG. The external terminals of the surface mount component E can be temporarily fixed by arranging them at positions corresponding to 7, and then the surface mount component E can be sent to a reflow furnace and fixed by soldering.

【0026】なお、上述した実施例でははんだ膜7をラ
ンド部に備えた配線パターン3,6を基板面に形成する
場合で説明したが、この配線パターンを有する回路基板
の製造方法は配線パターンのみを形成するものとして適
用することもできる。その場合にははんだ膜7に代え
て、メタルマスクとなる適宜な金属材料を導電膜3乃至
は導電層6に積層させて形成し、このメタルマスクを最
終工程で全面剥離すればよい。
In the above-described embodiment, the wiring patterns 3 and 6 having the solder film 7 on the land portion are formed on the substrate surface. However, the method for manufacturing a circuit board having this wiring pattern is only the wiring pattern. Can also be applied to form In that case, instead of the solder film 7, an appropriate metal material serving as a metal mask may be formed by laminating it on the conductive film 3 or the conductive layer 6, and the metal mask may be entirely removed in the final step.

【0027】[0027]

【発明の効果】以上の如く、本発明に係る配線パターン
を有する回路基板の製造方法に依れば、適正な電気特性
を保って狭間ピッチのランド部を有する配線パターンで
も、また、部品実装用のはんだ膜をランド部に備える配
線パターンでもてファインなものに形成でき、そのはん
だ膜をクリームはんだに頼らないで形成することからコ
ストの低減も図ることができる。はんだ膜は平滑な表面
のはんだボールが生じないものに形成できるため、表面
実装部品を高精度にはんだ付け固定することができる。
As described above, according to the method of manufacturing a circuit board having a wiring pattern according to the present invention, even a wiring pattern having land portions with a narrow pitch while maintaining proper electrical characteristics can be used for mounting components. It is possible to form a fine soldering film with a wiring pattern provided in the land portion, and the cost can be reduced because the soldering film is formed without relying on cream solder. Since the solder film can be formed so as not to generate solder balls having a smooth surface, the surface mount component can be soldered and fixed with high accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一例に係る配線パターンを有する回路
基板の製造方法を各工程順に示す説明図である。
FIG. 1 is an explanatory diagram showing a method of manufacturing a circuit board having a wiring pattern according to an example of the present invention in order of steps.

【図2】本発明に係るはんだ膜の形成工程で一部異なる
別例の配線パターンを有する回路基板の製造方法をはん
だ膜の形成工程から順に示す説明図である。
FIG. 2 is an explanatory diagram sequentially showing a method of manufacturing a circuit board having another example of a wiring pattern which is partially different in the solder film forming step according to the present invention from the solder film forming step.

【図3】本発明に係る方法で製造された回路基板に表面
実装部品を仮止め固定して示す説明図である。
FIG. 3 is an explanatory view showing a surface mount component temporarily fixed to a circuit board manufactured by the method according to the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 下地膜 3 導電膜 4 レジストフィルム 5 抜き穴 6 導電層 7 はんだ膜 8 はんだ膜のバリア層 DESCRIPTION OF SYMBOLS 1 Substrate 2 Underlayer film 3 Conductive film 4 Resist film 5 Holes 6 Conductive layer 7 Solder film 8 Solder film barrier layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡辺 源一 東京都中央区日本橋一丁目13番1号 ティ ーディーケイ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Genichi Watanabe 1-13-1, Nihonbashi, Chuo-ku, Tokyo Inside TDC Corporation

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基板,ポリイミド基板等の不
純ガスが生じない板材を基板とし、その基板の板面にC
r,Ti等の活性な金属材料で下地膜と共に、該下地膜
に積層させてCu等の導電性を有する金属材料で導電膜
をスパッタリングまたは真空蒸着で形成し、その後にレ
ジストフィルムを前記導電膜に被着させて露光,現象プ
ロセスによる所定パターンの抜き穴をフィルム面に形成
し、この抜き穴の内部に露出位置する導電膜に積層させ
て金属メッキ膜を前記所定パターンの抜き穴に応じて形
成し、その後にレジストフィルムを剥離すると共に、前
記金属メッキ膜をメタルマスクとして余剰な導電膜並び
に下地膜を基板の板面からエッチング除去し、更に、残
る導電膜上の金属メッキ膜を剥離することによりファイ
ンな配線パターンを形成するようにしたことを特徴とす
る配線パターンを有する回路基板の製造方法。
1. A plate material, such as a ceramic substrate or a polyimide substrate, which does not generate an impure gas, is used as a substrate, and C is provided on the plate surface of the substrate.
An active metal material such as r, Ti or the like, together with a base film, is laminated on the base film to form a conductive film of a conductive metal material such as Cu by sputtering or vacuum deposition, and then a resist film is formed on the conductive film. A hole with a predetermined pattern is formed on the film surface by exposure and a phenomenon process, and a metal plating film is formed according to the hole with the predetermined pattern by laminating on a conductive film exposed inside the hole. After the formation, the resist film is peeled off, the surplus conductive film and the base film are removed by etching from the plate surface of the substrate by using the metal plating film as a metal mask, and the metal plating film on the remaining conductive film is peeled off. A method for manufacturing a circuit board having a wiring pattern, characterized in that a fine wiring pattern is thereby formed.
【請求項2】 上記抜き穴の内部に露出位置する導電膜
に積層させて、膜厚を増加する同材質の金属材料を導電
層として電解メッキで形成するようにしたことを特徴と
する請求項1の配線パターンを有する回路基板の製造方
法。
2. The conductive film exposed inside the punched hole is laminated, and a metal material of the same material that increases the film thickness is formed by electroplating as a conductive layer. 1. A method of manufacturing a circuit board having a wiring pattern of 1.
【請求項3】 セラミック基板,ポリイミド基板等の不
純ガスが生じない板材を基板とし、その基板の板面にC
r,Ti等の活性な金属材料で下地膜と共に、該下地膜
に積層させてCu等の導電性を有する金属材料で導電膜
をスパッタリングまたは真空蒸着で形成し、その後にレ
ジストフィルムを前記導電膜に被着させて露光,現象プ
ロセスによる所定パターンの抜き穴をフィルム面に形成
し、この抜き穴の内部に露出位置する導電膜に積層させ
てはんだ膜を前記所定パターンの抜き穴に応じてメッキ
処理で形成し、その後にレジストフィルムを剥離すると
共に、前記はんだ膜をメタルマスクとして余剰な導電膜
並びに下地膜を基板の板面からエッチング除去し、更
に、残る導電膜上のはんだ膜をランド部に残存させて他
の導電膜から剥離することによりはんだ膜をランド部に
備えたファインな配線パターンを形成するようにしたこ
とを特徴とする配線パターンを有する回路基板の製造方
法。
3. A plate material, such as a ceramic substrate or a polyimide substrate, which does not generate an impure gas, is used as a substrate, and C is placed on the plate surface of the substrate.
An active metal material such as r, Ti or the like, together with a base film, is laminated on the base film to form a conductive film of a conductive metal material such as Cu by sputtering or vacuum deposition, and then a resist film is formed on the conductive film. To form a hole with a predetermined pattern on the film surface by exposure and a phenomenon process, and stack it on the conductive film exposed inside the hole to plate a solder film according to the hole with the predetermined pattern. Formed by processing, and then the resist film is peeled off, the surplus conductive film and the base film are removed by etching from the plate surface of the substrate using the solder film as a metal mask, and the solder film on the remaining conductive film is landed. Wiring characterized in that a fine wiring pattern having a solder film in the land portion is formed by leaving the solder film in the land and peeling it from other conductive film. Method of manufacturing a circuit board having a turn.
【請求項4】 上記抜き穴の内部に露出位置する導電膜
に積層させて、膜厚を増加する同材質の金属材料を電解
メッキで形成するようにしたことを特徴とする請求項3
の配線パターンを有する回路基板の製造方法。
4. A metal material of the same material that increases the film thickness is formed by electroplating by laminating it on a conductive film exposed inside the punched hole.
A method for manufacturing a circuit board having a wiring pattern.
【請求項5】 上記抜き穴の内部に露出位置する導電膜
に積層させて、SnPb等のはんだ膜を無電解メッキで
析出形成するようにしたことを特徴とする請求項3また
は4の配線パターンを有する回路基板の製造方法。
5. The wiring pattern according to claim 3, wherein a solder film of SnPb or the like is deposited and formed by electroless plating by laminating it on a conductive film exposed inside the punched hole. A method of manufacturing a circuit board having a.
【請求項6】 上記抜き穴の内部に露出位置する導電膜
に積層させて、Ni等のバリア層を介し、SnPb等の
はんだ膜を電解メッキで析出形成するようにしたことを
特徴とする請求項3または4の配線パターンを有する回
路基板の製造方法。
6. The conductive film exposed inside the hole is laminated, and a solder film of SnPb or the like is deposited by electrolytic plating through a barrier layer of Ni or the like. A method of manufacturing a circuit board having the wiring pattern according to item 3 or 4.
JP27946892A 1992-09-24 1992-09-24 Manufacture of circuit board having wiring pattern Pending JPH06112628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27946892A JPH06112628A (en) 1992-09-24 1992-09-24 Manufacture of circuit board having wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27946892A JPH06112628A (en) 1992-09-24 1992-09-24 Manufacture of circuit board having wiring pattern

Publications (1)

Publication Number Publication Date
JPH06112628A true JPH06112628A (en) 1994-04-22

Family

ID=17611484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27946892A Pending JPH06112628A (en) 1992-09-24 1992-09-24 Manufacture of circuit board having wiring pattern

Country Status (1)

Country Link
JP (1) JPH06112628A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302967A (en) * 1994-04-28 1995-11-14 Hirayama Chiyoukokushiyo:Kk Formation method of bump by metal plating
JP2008159849A (en) * 2006-12-25 2008-07-10 Matsushita Electric Ind Co Ltd Electrode bonding structure and electrode bonding method
CN109156080A (en) * 2016-05-16 2019-01-04 株式会社村田制作所 Ceramic electronic parts

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302967A (en) * 1994-04-28 1995-11-14 Hirayama Chiyoukokushiyo:Kk Formation method of bump by metal plating
JP2008159849A (en) * 2006-12-25 2008-07-10 Matsushita Electric Ind Co Ltd Electrode bonding structure and electrode bonding method
CN109156080A (en) * 2016-05-16 2019-01-04 株式会社村田制作所 Ceramic electronic parts
CN109156080B (en) * 2016-05-16 2021-10-08 株式会社村田制作所 Ceramic electronic parts

Similar Documents

Publication Publication Date Title
US5118386A (en) Printed circuit board having bumps and method of forming bumps
US8124880B2 (en) Circuit board and method for manufacturing thereof
US5985521A (en) Method for forming electrically conductive layers on chip carrier substrates having through holes or via holes
JP3618997B2 (en) How to create a metal standoff on an electronic circuit
EP0127955B1 (en) Manufacture of printed circuit boards
US5922517A (en) Method of preparing a substrate surface for conformal plating
JPH06112628A (en) Manufacture of circuit board having wiring pattern
KR20020026849A (en) Wiring circuit board having bumps and method of producing same
JPH08107263A (en) Manufacturing method of printed wiring board
JPH06268355A (en) Printed wiring board and manufacture thereof
JPH0563340A (en) Manufacture of wiring board provided with functional element
JPH1117315A (en) Manufacture of flexible circuit board
US20250008645A1 (en) Printed wiring board
KR20030042873A (en) The method for manufacturing circuit pattern of printed circuit board using resist plating by pure metal
JP2002020897A (en) Manufacturing method of multi-layered circuit substrate for electronic component
JPH03225894A (en) Manufacture of printed wiring board
JP2681205B2 (en) Printed wiring board with membrane element
JP2004072027A (en) Manufacturing method of wiring board with protruding electrodes
JPH0567871A (en) Printed-wiring board and manufacture thereof
KR100642734B1 (en) Manufacturing method of double sided wiring board and double sided wiring board
JPH05251848A (en) Manufacture of printed wiring board
JPH05160572A (en) Multilayer printed circuit board
JPS62171194A (en) Matrix wiring board
JPH05335723A (en) Manufacture of printed circuit board
JPH04355994A (en) Manufacture of printed wiring board

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20030225