JPH06112833A - DA converter and DA converter - Google Patents

Abstract

(57) [Abstract] [Purpose] Expand the usable range of the switch that switches the reference voltage. [Structure] Two sets of CMOS analog switches 92 and 94 are provided for applying a reference voltage Vref ₂ or Vref ₁ to a resistance circuit 82 for each bit of an input digital signal. The signal voltage corresponding to each bit of the input digital signal by the switch control circuit 2 is inverted by the first inverter 88 (F1 to Fn), and the NMOS transistors AN1 to ANn of the analog switch 92 and the PMOS transistors BP1 to BP1 of the analog switch 94. BP
The signal applied to the gate electrode of n and inverted by the inverter 88 is again inverted by the second inverter 90 (E1 to En), and the PMOS transistors AP1 to APn of the analog switch 92 and the NMOS transistors BN1 to BN1 of the analog switch 94 are inverted. It is applied to BNn. When one of the pair of analog switches 92, 94 for each bit is turned on, either the reference voltage Vref ₁ or Vref ₂ is applied to the resistance circuit 82 in the switch for each bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA (digital / analog) converter and a DA converter, and more particularly to a voltage division R
The present invention relates to a -2R ladder resistance type DA converter and a DA converter using the DA converter, which is suitable for use in audio equipment and the like.

[0002]

2. Description of the Related Art As shown in FIG. 1, an R-2R type DA converter has an input digital signal controlled by a switch control circuit 2 in series with a 2R resistance portion of a voltage dividing R-2R ladder resistance circuit 82. A switch 83 for switching between two reference voltages (Vref ₁ , Vref ₂ ) is connected to each bit. Depending on the input digital signal, switch the corresponding bit switch 83 to Vref ₁ or V
By switching to ref ₂ (Vref ₁ > Vref ₂ ), the voltage divided by the resistance circuit 82 is obtained as an output. The terminal end of the resistance circuit 82 is connected to the low voltage side reference voltage Vref ₂ or the analog ground (AGND).

As the switch 83 of such an R-2R ladder resistance type DA converter, one using a MOS transistor as shown in FIG. 2A is used. A PMOS transistor is used as the switch 84 for connecting to the high voltage side reference voltage Vref _1, and an NMOS transistor is used as the switch 86 for connecting to the low voltage side reference voltage Vref ₂ . A high level signal or a low level signal is applied to the gate electrodes of both MOS transistors 84 and 86 according to the input digital signal Di controlled by the switch control circuit.

Further, R-2R is used as a DA converter for converting a binary code digital signal into an analog signal.
There is a ladder resistance type DA converter. In the DA converter, there is a problem that the DA conversion accuracy is lowered due to the on resistance of the switch. Therefore, as one method for solving the problem, the ratio of the on resistance of the switch elements is 1: 2 from the upper side to the lower side. : 4: 8 ... A DA converter set so that it has been proposed (Japanese Patent Laid-Open No. 61-26).
3325 gazette).

[0005]

In the switch of FIG. 2A, the PMOS transistor 84 is turned on in order to apply the high voltage side reference voltage Vref ₁ to the resistance circuit,
On the other hand, the NMOS transistor 86 is turned on to apply the low-voltage side reference voltage Vref ₂ to the resistance circuit.

If the voltage applied to the gate electrode of the switch 83 via the switch control circuit by the input digital signal is either V _DD or GND, V ref ₁
4B, the range of voltage that can be taken by the switch 84, that is, the operating range of the switch 84 is V _DD and V _TH (V _TH is MO
Threshold voltage of the S-transistor), while N
V applied to the resistance circuit via the MOS transistor 86
The voltage range that ref ₂ can take is between V _DD -V _TH and GND. Therefore, the MOS transistor of the switch may not be usable depending on the value of the reference voltage. Moreover, as the power supply voltage is lowered, the usable range of the switch is further reduced.

Further, a reference example (Japanese Patent Laid-Open No. 61-263325).
In the DA converter proposed in Japanese Patent Laid-Open Publication No. 2003-331242, since the ON resistance ratio of the switch elements is formed to be 1: 2: 4: 8 ..., the switching is performed as the number of bits of the input digital signal increases. The on-resistance ratio of the device also increases. In the cited example, the switch element is realized by a MOS transistor, but since the on resistance of the MOS transistor is inversely proportional to the channel width if the channel length is constant,
If the on-resistance is to be 1: 2: 4: 8 ..., The channel width must be 1: 1/2: 1/4: 1/8. Therefore, in order to design a DA converter having a large number of input digital signal bits, the channel width ratio must be increased.
Since the minimum value of the channel width of the MOS transistor is determined by the transistor characteristics and the like, it is necessary to use a MOS transistor having a very large channel width in a DA converter having a large number of bits of an input digital signal, and the area of the switch portion is very large. However, there is a problem in that the area of the entire semiconductor integrated circuit device including the DA converter becomes large. Therefore, the number of bits of the input digital signal that can be realized is limited.

A first object of the present invention is to extend the usable range of the switch. A second object of the present invention is a semiconductor integrated circuit device including a voltage division type R-2R ladder resistance type DA converter, which is capable of handling an input digital signal with a high bit number by reducing the area on a semiconductor chip. It is to provide a device.

[0009]

According to the present invention, a PMOS transistor is used as a switch which is connected in series to the 2R resistance portion of an R-2R ladder resistance circuit for voltage division and which switches between two reference voltages according to each bit of a digital input signal. It is assumed that analog switches including an NMOS transistor and an NMOS transistor are provided for each of the two reference voltages. In the preferred embodiment, the switch is N
Well CMOS structure and NMO of the CMOS
The back gate potential of the S transistor is set to the source potential Vss.
And the back gate potential of the CMOS PMOS transistor is set to the potential on the high voltage side of the reference voltage.

In another preferred embodiment, the switch is a double well CMOS structure and the CMO is
The back gate potential of the NMOS transistor of S is set to the source potential V _SS or the potential on the low voltage side of the reference voltage,
The back gate potential of the PMOS transistor of the CMOS is set to the potential on the high voltage side of the reference voltage.

The DA converter of the present invention divides the input digital signal into bit groups of several bits from the upper bits,
A DA converter that DA-converts a digital signal of a bit group other than the least significant bit group and a digital signal obtained by adding 1 to the least significant bit of the bit group is DA
A DA converter for converting, and a DA for converting the digital signal of the bit group to the least significant bit group
A converter is provided, and the supplied high-voltage side and low-voltage side reference voltages are supplied as two reference voltages to the DA converter of the most significant bit group, and the DA converter of the lower bit group has one higher bit. Supply the two analog output voltages of the group as reference voltage,
The DA conversion result of the digital signal of the least significant bit group is used as the final DA conversion value, and each DA converter serially connects to the 2R resistance section of the voltage dividing R-2R ladder resistance circuit, depending on each bit of the digital input signal. A switch for switching between two reference voltages of the DA converter is connected, and the switch is provided with an analog switch including a PMOS transistor and an NMOS transistor for each of the two reference voltages.

[0012]

When an analog switch is used for the switch section, the operating range of the switch is widened. When an analog switch is used for the switch section, it is general to set the back gate potential of the NMOS transistor to V _SS and the back gate potential of the PMOS transistor to V _DD . In that case, the threshold voltage V _TH increases due to the back gate effect depending on the values of the reference voltages Vref ₁ and Vref ₂ , and the on resistance of the NMOS transistor and the PMOS transistor in the analog switch portion is lost, and V _DD / The resistance value of 2 becomes large. Also, N-well CMOS
In this case, if the back gate voltage of the PMOS transistor of the analog switch is set to V _DD , there is a risk of latch-up depending on the sequence of switching on. Further, in the case of the W-well CMOS, if the back gate voltage of the PMOS transistor is set to V _DD as in the N-well CMOS, there is a risk of latch-up depending on the switching sequence. Therefore, by setting the back gate potential as in claim 2 or 3, the balance of the on-resistance is maintained and the latch-up is prevented.

[0013]

EXAMPLE FIG. 3 shows an example. 2 of resistance circuit 82
In order to switch the reference voltage according to the voltage applied from the switch control circuit 2 corresponding to each bit of the input digital signal, the reference voltage is connected in series with the R resistor section,
Two sets of CMOS analog switches 92 and 94 are connected for each bit. The analog switch 92 is an analog switch for applying the low voltage side reference voltage Vref ₂ to the resistance circuit 82, and 94 is an analog switch for applying the high voltage side reference voltage Vref ₁ to the resistance circuit 82. The signal voltage corresponding to each bit of the input digital signal by the switch control circuit 2 is the first
Are inverted by the inverter 88 (F1 to Fn) of each of the above, and the NMOS transistors AN1 to ANn of the analog switch 92 for the low voltage side reference voltage of the pair of analog switches for each bit and the PMOS of the analog switch 94 for the high voltage side reference voltage. Transistors BP1 to BPn
Is applied to the gate electrode of. A second inverter 90 (E1 to En) is provided to invert the signal voltage inverted by the inverter 88 again.
Of the analog switch 92 and the NMO of the analog switch 94.
It is applied to the S transistors BN1 to BNn.

In the embodiment of FIG. 3, the control signal from the switch control circuit 2 passes through the inverter 88 and further the inverter 90 corresponding to each bit of the input digital signal.
Is applied to a pair of analog switches 92, 94 for each bit, and one of the pair of analog switches 92, 94 for each bit is turned on, so that the switch for each bit has a reference voltage Vref ₁ or Vre.
Either f ₂ is applied to the resistance circuit 82. Switch 9
Since the analog switches are used as the circuits 2, 94, the switch operates at any voltage as long as the reference voltage is between GND and V _CC , so that the reference voltage can be freely determined.

The back gate voltage of the analog switches 92 and 94 is P by setting the back gate voltage of the PMOS transistor to the high voltage side reference voltage Vref _1.
The back gate voltage of the MOS transistor is applied and the reference voltage Vref _{1 is} applied to _one terminal of the analog switch.
Try to give at the same time. This can prevent an increase in on-resistance and prevent latch-up.

An embodiment of a DA converter having the DA converter of FIG. 3 will be described below. Input digital signal to D ₀
And to D _7, which will be described an operation for mode for performing DA conversion divided into upper bit group and (D ₄ ~D ₇₎ the lower bit group and (D ₀ ~D _3). As shown in FIG. 4, the higher-order bit groups D _{4 to} D ₇ of the input digital signal are regarded as 4-bit digital signals, and the high-voltage side reference voltage Vref ₁ and the low-voltage side reference voltage Vref ₂ are used as reference voltages. The digital signal obtained by adding 1 to the least significant bit D ₄ of the 4-bit signals D _{4 to} D ₇ is DA-converted to obtain Vrefa.
At the same time, the digital signals D _{4 to} D ₇ are transferred to Vref ₁ and Vref ₂
Is used as a reference voltage to obtain Vrefb.

Next, the lower bit group D _{0 to} D ₃ is regarded as a 4-bit signal, and DA conversion is performed by using the voltages Vrefa and Vrefb obtained by the DA conversion of the upper bit group as reference voltages to obtain Vout. This DA conversion value Vout is the DA conversion value of the 8-bit digital input signals D _{0 to} D ₇ .

FIG. 5 shows an embodiment corresponding to claim 4. The input digital signal is represented by D _{0 to} Dn (n +
1) A bit digital signal. The input digital signal is divided by the switch control circuit 2 into bit groups of several bits from the upper bits and sent to the DA converter. Digital signal Dm- _{1 to} Dn of the most significant bit group
Is input to the DA converter 8 and also input to the DA converter 6 via the +1 adder 4. The +1 adder 4 outputs ₁ to the least significant bit Dm- ₁ of the input digital signal.
Is to be added. A high voltage side voltage Vref ₁ and a low voltage side point voltage Vref ₂ are applied to the DA converters 6 and 8 as reference voltages. The outputs of the DA converters 6 and 8 are supplied as reference voltages of the DA converters 16 and 18 to which the digital signals of the next lower bit group are input via the output buffer circuits 10 and 12, respectively. D
Similarly, the digital signals Dj- _{1 to} Dm- _{2 of the} bit groups input to the A converters 16 and 18 are processed by the DA converter 18 as well.
Is also input to the DA converter 16 via the +1 adder 14. DA converters 16 and 18
Is supplied as a reference voltage of the DA converter for the digital signal of the next bit group via the output buffer circuits 20 and 22, respectively. Least significant bit group D ₀
The two output voltages obtained as a result of the DA conversion of the digital signal of the bit group one higher than that are supplied to the DA converter 24 to which ~ Di is input as reference voltages. The output of the DA converter 24 is the DA conversion output of the (n + 1) -bit input digital signals D _{0 to} Dn.

Each DA converter 6, 8, 16, 18, 2
Reference numeral 4 uses a CMOS analog switch as a switch for switching the reference voltage, as shown in FIG. The same applies to each of the following examples.

In this manner, the MSB of the input digital signal is divided into several bits, and DA conversion is sequentially performed from the upper digital signal, and the result is used as the reference voltage of the digital signal of the next lower bit group. The DA conversion output Vout is obtained by DA-converting a digital signal of several bits from the LSB and DA-converting the output analog signal obtained by DA-converting the digital signal one level above.

If the input analog signal is divided into M bit groups of several bits from the upper bits and DA-converted to obtain the output analog signal, the number of DA converters increases as M increases. The area of the entire circuit also becomes large. When actually designing a DA converter with such a circuit, it is practical to divide the input digital signal into a high-order bit group and a low-order bit group, that is, divide M = 2 for conversion.

FIG. 6 shows an 8-bit input digital signal D _0- .
₆ shows an embodiment corresponding to claim 5, in which D ₇ is divided into a 4-bit upper bit group and a 4-bit lower bit group.

FIG. 7 is a circuit diagram showing FIG. 6 at the transistor level. This is an example in which an R-2R ladder resistance type DA converter using an analog switch as shown in FIG. 3 is used as the switch 26 in the DA converters 6, 8 and 24. In particular, in order to reduce the error due to the ON resistance of the switch, As described in Japanese Patent Laid-Open No. 61-263325, each switch is composed of a CMOSFET, and the ON resistance of these switches is set from the MSB side to the LSB.
It is set to double, four times, eight times, and so on toward the side. E _{1 to} E ₅ represent the ON resistance of each switch 26. The high-order bit group and the low-order bit group are treated as 4-bit digital signals. The DA converter 6 receives the least significant bit D of the input digital signal.
_Since +1 is added to ₄ , the digital signal may have 5 bits, so a 5-bit DA converter is used. The DA converters 8 and 24 are 4-bit DA converters.

When designing a DA converter with a gate array, it is not known how many DA converters of which bits are required depending on the user's application. Therefore, in the gate array, a master chip including only one DA converter, a master chip including two DA converters, and a master chip including three DA converters are prepared. Therefore, there are many types of master chips. Therefore, an embodiment corresponding to claim 6 in which a high-bit DA converter and several low-bit DA converters are provided so that they can be switched according to an input digital signal, and the master chip is one kind. Is shown in FIG.

The characteristic of the DA converter of FIG. 8 is that there are a plurality of input digital signal sections and a plurality of output analog signal sections. High bit number (n + 1 bit) digital signal S ₁ and low bit number (i + 1 bit) as input signals
Two digital signals S ₂ and S ₃ are input. The switch control circuits 2a to 2c send the respective input signals to D
It is a control circuit for inputting to the A converter. In particular, the input digital signal S ₁ is divided by the switch control circuit 2a into upper bit groups Dm- _{1 to} Dn and lower bit groups D _{0 to} Dm- ₂ . Input digital signal S ₁
For the upper bit group Dm- ₁ as in the embodiment of FIG.
Digital signals Dn to Dn are input to the DA converter 8a via the DAC-IN control circuit 32, and the least significant bit Dm- of the digital signals of the upper bit groups Dm- _{1 to} Dn.
₁ is added to ₁ by the adder 4 and is input to the DA converter 6a via the DAC-IN control circuit 30. D
Vref ₁ and Vref ₂ are applied as reference voltages to the A converters 6a and 8a. In this case, the DAC-IN control circuits 30 and 32 are the DA converters 6a and 8a.
It is a control circuit for switching the digital signals respectively inputted to the signals S ₁ and S ₂ and S ₃ . The input digital signal S ₂ is input to the DA converter 6a via the DAC-IN control circuit 30 by the switch control circuit 2b, and the input digital signal S ₂ is input.
₃ is DAC-I by the switch control circuit 2c
It is input to the DA converter 8a via the N control circuit 32. DA converters 6a, or outputs 8a of the conversion result as the output Vout _2, Vout ₃ via respective buffers 10, 12, a digital signal of the lower bit group D ₀ ~Dm- ₂ of the input digital signal S ₁ is input DAC-OUT control circuits 34 and 36 are provided to switch whether the reference voltage of the DA converter 24 is supplied to the DA converter 24.

DAC-IN control circuits 30, 32
An example is shown in FIG. It is assumed that two signals α and β are supplied as input digital signals, each of which is a digital signal of (n + 1) bits. As many CMOS as the number of bits of the input digital signal are arranged, and each CMO is
Each bit of the input digital signal α is input to the source of the PMOS transistor of S, and each bit of the input digital signal β is input to the drain of the NMOS transistor.
The node with the source of the MOS transistor is taken out as the output of each bit. A DAC control signal is applied to the gate of each PMOS transistor and NMOS transistor. When the DAC control signal is L, the input digital signal α becomes an output signal, and when the DAC control signal is H, the input digital signal β becomes an output signal.

FIG. 10 shows an example of the TAC-OUT control circuits 34 and 36 in FIG. Buffer circuit 1
The analog output signal from 0 or 12 is applied to the transfer gates 42 and 44 of the CMOS. The DAC control signal is applied to one gate electrode of the transfer gates 42 and 44, and the DAC control signal is applied to the other gate electrode of the transfer gates 42 and 44 through an inverter. One of the transfer gates 42 and 44 is turned on and the other is turned off. In the case of FIG. 10, DAC
When the control signal is L, the analog output signal is output to the output 2, and when the DAC control signal is H, the analog output signal is output to the output 1.

Returning to FIG. 8, the operation of this embodiment will be described. First, when the signal is not sent from the DAC control terminal, the DAC-IN control circuits 30 and 3
2 selects the input digital signal S ₁ side, DAC-OUT
In the control circuits 34 and 36, the side that applies the reference voltage to the DA converter 24 is turned on. At this time, the digital signal of the upper bit group of the input digital signal S ₁ is DA-converted by the DA converters 6a and 8a to become the reference voltage of the DA converter 24, and the digital signal of the lower bit group of the input digital signal S ₁ is converted to the DA converter 2
4 is input, and is DA-converted by the new reference voltage and output as Vout ₁ . In this case, a 2-step DA conversion circuit using a high bit input digital signal is used.

When a signal is sent from the DAC control terminal, the DAC-IN control circuits 30 and 3
2 selects the input digital signals S ₂ and S _3, and the DA conversion results of those digital signals by the DA converters 6a and 8a are output as Vout ₂ and Vout ₃ by the DAC-OUT control circuits 34 and 36, respectively. In this case, the low-bit 1-step DA conversion circuit is used.

Generally, in a DA conversion circuit, an input digital signal is converted into an analog signal by a designated reference voltage. If the DA converter circuit requires output analog values with different reference voltages for input digital signals, prepare multiple DA converters with different reference voltages, or change the reference voltage with one DA converter to output Calculate the analog value. Therefore, as an embodiment corresponding to claim 7 of the present invention, 2-step DA conversion by a high bit input digital signal and low bit DA conversion capable of obtaining output analog signals having different reference voltages can be switched and executed. An example is shown in FIG.

In the embodiment of FIG. 11, the reference voltage is 2
_Two sets are provided for _one high reference voltage Vref ₁ and Vref ₂ for the high bit input digital signal S ₁ .
Step DA conversion is performed, and for the low bit input digital signal S ₂ , any reference voltage (Vref ₁ and Vr
One-step DA conversion by ef ₂ ) or (Vref ₃ and Vref ₄ ) can be performed.

The digital signal of the high-order bit group of the high-bit input digital signal S ₁ is input from the DAC-IN control circuit 32 to the DA converter 8a by the switch control circuit 2d, and the addition circuit 4 is added to the digital signal of the high-order bit group. 1 is added to the least significant bit of the DAC-IN control circuit 30 and DA
It is input to the converter 6a. On the other hand, the low bit input digital signal S ₂ is passed through the switch control circuit 2e to D
From the AC-IN control circuits 30 and 32, D
It is input to the A converters 6a and 8a. A pair of reference voltages Vref ₁ and Vref ₂ is applied to the DA converter 6a, and one of the reference voltages (Vref ₁ and Vref ₂ ) or (Vref ₃ and Vref ₃ ) is applied to the DA converter 8a by the VREF control circuits 46 and 48. Vref ₄ ) is applied. DAC-OUT control circuits 34 and 36 are DA
The outputs of the converters 6a and 6b are output as the output Vout ₂ or Vout ₃ , respectively, or are applied as the reference voltage of the DA converter 24 via the buffer circuits 10 and 12.

FIG. 12 shows an example of the VREF control circuits 46 and 48. One set of Vrefα and the other set of Vr
efβ is applied to the respective transfer gates 50 and 52, and D
Any one is selected by the AC control signal and Vref
Is output as. In this case, when the DAC control signal is at L level, Vrefα is output as Vref, and Dref
When the AC control signal is H level, Vrefβ is Vr
Output as ef.

Next, the operation of the embodiment shown in FIG. 11 will be described.
When the H level signal is supplied to the DAC control signal, the DAC-IN control circuits 30 and 32 select the input digital signal S ₂ as the input signal of the DA converters 6a and 8a. At the same time, the VREF control circuits 46 and 48 select Vref ₃ and Vref ₄ as reference voltages for the DA converter 8a. As a result, in the DA converter 6a, the input digital signal S ₂ is DA-converted by the reference voltages Vref ₁ and Vref ₂ ,
It is output as Vout ₂ via the DAC-OUT control circuit 34. On the other hand, DA converter in 8a same input digital signal S ₂ is DA converted by the reference voltage Vref ₃ and Vref _4, is outputted as Vout ₃ via the DAC-OUT control circuit 36.

On the other hand, when the DAC control signal is at L level, the DAC-IN control circuits 30, 32 are provided.
The input digital signal S ₁ is selected by the VREF control circuits 46 and 48, and the DA converter 8a is selected.
Vref ₁ and Vref ₂ are selected as the reference voltage of
The DAC-OUT control circuits 34 and 36 are selected to supply the outputs of the DA converters 6a and 8a as reference voltages to the DA converter 24 via the buffer circuits 10 and 12. At this time, the input digital signal S ₁ is DA converted in two steps and output as Vout ₁ .

In the DA conversion circuit, for example, when performing 8-bit DA conversion, an output analog value is obtained for 8-bit input digital signal. However, normally, even if the input digital signal is 8 bits, when the output value with the highest accuracy within a certain range is required, for example, the accuracy of 10 bits may be required. In such a case, a 10-bit DA converter is used to perform 10-bit conversion. Therefore, the DA converter becomes large. Therefore, FIG. 13 shows an embodiment corresponding to claim 8 in which 8-bit DA conversion is performed when 8-bit is sufficient and 10-bit conversion is performed only when 10-bit precision is required. .

Comparing FIG. 13 with FIG. 6, the comparison voltages V ₁ and V ₂ are applied to the input terminals as control signals, and the DAC-O
Input digital signal D by the UT control circuit 54
₀ If DA conversion by the upper bit group _DL-1 -Dn the M-bit digital signal in the -Dn is not in between the comparison voltage V ₁ and V ₂ and outputs the DA conversion value of the M bits, the comparison voltage The difference is that if it is between V ₁ and V ₂ , 2-step DA conversion by all input digital signals of D _{0 to} Dn is output. High precision DA conversion is required in the range between the comparison voltages V ₁ and V ₂ .

The DAC-OUT control circuit 54 is a circuit for determining whether the DA conversion result by the DA converter 8 of the upper bit group _DL-1 -Dn is between V ₁ ~V _2, for example, in FIG. 14 It has the configuration shown. The output of the DA converter 8 passing through the buffer circuit 12 is applied as an input signal to the inverting input terminal of the comparator 60 and the non-inverting input terminal of the comparator 62 of FIG. 14, and the comparison voltage V ₁ is applied to the non-inverting input terminal of the comparator 60. Then, the comparison voltage V ₂ is applied to the inverting input terminal of the comparator 62. Here, V ₁ <V ₂ . The outputs of the comparators 60 and 62 are applied to both input terminals of the AND circuit 64. On the other hand, the input signal is input to the two transfer gates 66 and 68, and the output from the AND circuit 64 outputs α or β.
Is output as. The output from the AND circuit 64 is also
It is output as the output γ.

Signals α and γ are input from the DAC-OUT control circuit 54 to the DAC-OUT control circuit 56, and the output of the DA converter 24 is output to the buffer circuit 5.
It is applied as signal δ via 8. FIG. 15 shows an example of the DAC-OUT control circuit 56 in FIG. 13. The signals α and δ are input to the transfer gates 70 and 72, and either one of them is output as the output Vout by the signal γ.

In FIG. 14, the input signal is the comparator 60,
It is checked by 62 whether it is between the comparison voltages V ₁ and V ₂ , and a signal is output to the output β if there is one, and to the output α if not. An H level signal is output to the output γ if the input signals are V ₁ and V _2, and an L level signal is output otherwise. In FIG. 15, when the input signal γ is L level, the input signal α is Vout
Output to the input signal γ when the input signal γ is at the H level.
Is output to Vout.

Next, the operation of the embodiment shown in FIG. 13 will be described.
Of the input digital signals D _{0 to} Dn, the upper bit group Dl- ₁ to
The digital signal of Dn is added to its least significant bit by 1 by the +1 adder 4 and DA-converted by the DA converter 6, while the higher-order bit group Dl-
The digital signals _{1 to} Dn are DA converted. DAC-OU
The T control circuit 54 checks whether the output value DA-converted by the DA converter 8 is between the comparison voltages V ₁ and V ₂ , and if not, the DA conversion value is output as the signal α.
Is sent to the DAC-OUT control circuit 56 as
Also, the signal (γ = L) indicating that it is not between V ₁ and V ₂ is D
It is sent to the AC-OUT control circuit 56. DAC
The -OUT control circuit 56 outputs the DA conversion value by the digital signal of the upper bit group Dl- _{1 to} Dn, which is DA converted by the DA converter 8, to Vout as an output.

When the DA conversion value in the DA converter 8 is between the comparison voltages V ₁ and V ₂ , the DAC-OUT control circuit 54 causes the DA converter 24 to output the DA value converted by the DA converter 8 to one reference. It is supplied as a voltage (β), and the DAC-OUT control circuit 5
6, the converted signal from the DA converter 8 is the comparison voltage V ₁ and V ₂
A signal (γ = H) indicating that it was in between is sent. In the DA converter 24, the digital signals of the lower bit groups D _{0 to} Di of the input digital signals D _{0 to} Dn are DA converted using the output signals of the DA converters 6 and 8 as reference voltages. The output value is sent to the DAC-OUT control circuit 56 via the buffer circuit 58, and the DAC-OUT control circuit 56 outputs the output of the DA converter 24 to Vou according to γ = H sent from the DAC-OUT control circuit 54.
Output as t. In this case, high bit DA of D _{0 to} Dn
It becomes a conversion circuit.

In FIG. 7 of the embodiment, DA converters 6, 8,
As the reference numeral 24, a switch element designed so that the ON resistance of the switch element is changed to 2 times, 4 times, 8 times ... Any of those generally used in the above may be used.

[0044]

In the DA converter of the present invention, since the CMOS analog switch is used as the switch for switching the reference voltage, the operating range of the switch is widened. At that time, by setting the back gate potential as in claim 2 or 3, the balance of the on-resistance can be maintained and the latch-up can be prevented.

According to another aspect of the DA converter of the present invention, the input digital signal is divided into a plurality of bit groups and each of them is sequentially DA converted.
Since the conversion is performed, even when the ON resistance of the switch element is changed, the number of bits of each DA converter is reduced, so that high-bit DA conversion can be performed without increasing the size of the switch element. . According to the fifth aspect, by dividing the input digital signal into two high-order and low-order bit groups, practical DA conversion can be performed. According to the sixth aspect, in the master chip of the gate array, even if the number of input bits required by the user is different, one master chip can be used.

In the seventh aspect, when analog output signals having the same input signal but different reference voltages are required, it is not necessary to change the reference voltage each time, and only the control signal can be used. According to claim 8, when high precision is not required for the analog output value, low bit DA conversion is performed by using a part of the input digital signal to quickly output, and when high precision is required, DA conversion by a plurality of steps is performed. Can output with high accuracy.
This is a conversion precision according to the purpose, such as highly accurate DA conversion in places where people can often hear or see sounds or images, and low precision in places where people cannot see or hear much. This is convenient when you want to use differently.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an R-2R ladder type DA converter.

2A and 2B are diagrams showing a conventional R-2R ladder type DA converter, in which FIG. 2A is a circuit diagram showing a main part thereof, and FIG. 2B is a diagram showing an operation range of a switch.

FIG. 3 is a circuit diagram showing a DA converter of one embodiment.

FIG. 4 is a diagram showing an operation of the present invention.

FIG. 5 is a circuit diagram showing an embodiment of a DA converter corresponding to claim 4;

FIG. 6 is a circuit diagram showing an embodiment of a DA converter corresponding to claim 5;

FIG. 7 is a circuit diagram expressing the embodiment of FIG. 6 at a transistor level.

FIG. 8 is a circuit diagram of an embodiment of a DA converter corresponding to claim 6;

FIG. 9 is a circuit diagram showing an example of DAC-IN control circuits 30 and 32.

FIG. 10 shows DAC-OUT control circuits 34 and 36.
It is a circuit diagram which shows an example.

FIG. 11 is a circuit diagram of an embodiment of a DA converter corresponding to claim 7;

FIG. 12 is a circuit diagram showing an example of VREF control circuits 46 and 48.

FIG. 13 is a circuit diagram of an embodiment of a DA converter corresponding to claim 8.

FIG. 14 is a circuit diagram showing an example of a DAC-OUT control circuit 54.

FIG. 15 is a circuit diagram showing an example of a DAC-OUT control circuit 56.

[Explanation of symbols]

4 adder 6,8,16,18,24 DA converter 30,32 DAC-IN control circuit 34,36,54,56 DAC-OUT control circuit 46,48 VREF control circuit 92,94 Analog switch

Claims (8)

[Claims] 1. A R-2R ladder resistor circuit for voltage division 2
In a DA converter in which a switch for switching between two reference voltages according to each bit of a digital input signal is connected in series with an R resistor unit, the switch is PM
A DA converter characterized in that an analog switch including an OS transistor and an NMOS transistor is provided for each of two reference voltages. 2. The switch has an N-well CMOS structure, the back gate potential of the NMOS transistor of the CMOS is set to the source potential Vss, and the back gate potential of the PMOS transistor of the CMOS is set to a potential on the high voltage side of the reference voltage. The DA converter according to claim 1. 3. The switch has a double-well CMOS structure, and the back gate potential of the NMOS transistor of the CMOS is set to the source potential V _SS or the potential on the low voltage side of the reference voltage, and the back gate potential of the PMOS transistor of the CMOS is set. The DA converter according to claim 1, wherein is a potential on the high voltage side of the reference voltage. 4. A DA converter that divides an input digital signal into bit groups of several bits from the upper bit and DA-converts a digital signal of the bit group other than the least significant bit group and a maximum of the bit group. 1 in lower bit
Is provided to the DA converter of the most significant bit group, and the DA converter of the least significant bit group is provided to the DA converter of the most significant bit group. The reference voltage on the high voltage side and the reference voltage on the low voltage side are supplied as two reference voltages, and the DA converter of the lower bit group is supplied with the two analog output voltages of the upper one bit group as the reference voltage. The DA conversion result of the digital signal of the lower bit group is used as a final DA conversion value, and each DA converter serially connects the 2R resistor section of the R-2R ladder resistor circuit for voltage division with each bit of the digital input signal. A switch for switching between two reference voltages of the DA converter is connected, and the switch is a PMO. DA, wherein the analog switch includes a transistor and a NMOS transistor are respectively provided for the two reference voltages that
Converter. 5. A DA conversion by dividing an input digital signal into a high-order bit group and a low-order bit group, and a digital signal of the high-order bit group and a digital signal obtained by adding 1 to the least significant bit of a given reference voltage. The DA converter according to claim 4, wherein the resulting output voltage is used as a reference voltage to perform DA conversion of the digital signal of the lower bit group. 6. An input section for inputting a high-bit-number input digital signal and a plurality of lower-bit-number input digital signals, wherein the input digital signal is higher-order bits than the high-bit-number input digital signal. To a bit group of several bits, and a DA converter that performs DA conversion of the digital signal of the bit group other than the least significant bit group and a digital signal obtained by adding 1 to the least significant bit of the bit group And a DA converter for converting the digital signal of the bit group to the least significant bit group.
Equipped with a DA converter for conversion, the DA of the most significant bit group
The converter is supplied with the applied high-voltage side and low-voltage side reference voltages as two reference voltages, and the DA converter of the lower bit group is supplied with the two analog output voltages of the one higher bit group as the reference voltage. As a digital signal of the least significant bit group
A high bit DA converter that takes the conversion result as the final DA converted value, and a D bit once for an input digital signal with a low bit number.
It has a low bit DA converter that performs A conversion to obtain an output voltage, and both DA converters share the DA converter, and both DA converters are switched by a control signal.
In the converter, 2 of R-2R ladder resistance circuit for voltage division is used.
A switch that switches between two reference voltages of the DA converter according to each bit of the digital input signal is connected in series with the R resistor section, and the switch is a PMO.
A DA converter characterized in that an analog switch including an S transistor and an NMOS transistor is provided for each of the two reference voltages. 7. An input unit for inputting a high-bit-number input digital signal and a plurality of lower-bit-number input digital signals, wherein the input digital signal is higher-order bits than the high-bit-number input digital signal. To a bit group of several bits, and a DA converter that performs DA conversion of the digital signal of the bit group other than the least significant bit group and a digital signal obtained by adding 1 to the least significant bit of the bit group And a DA converter for converting the digital signal of the bit group to the least significant bit group.
Equipped with a DA converter for conversion, the DA of the most significant bit group
The converter is supplied with the applied high-voltage side and low-voltage side reference voltages as two reference voltages, and the DA converter of the lower bit group is supplied with the two analog output voltages of the one higher bit group as the reference voltage. As a digital signal of the least significant bit group
A high bit DA converter that takes the conversion result as the final DA converted value, and a D bit once for an input digital signal with a low bit number.
A low-bit DA converter that performs A conversion to obtain an output voltage, both DA converters share the DA converter, and both DA converters can be switched by a control signal. The input digital signal is input to two DA converters, and the reference voltages of the DA converters can be different from each other. The output voltages of the DA converters can be switched and output, and the voltage of each DA converter can be changed. In accordance with each bit of the digital input signal, 2 of the DA converter is serially connected to the 2R resistance part of the R-2R ladder resistance circuit for division.
A switch for switching between two reference voltages is connected, and the switch is a PMOS transistor and an NMO.
A DA converter, wherein an analog switch including an S transistor is provided for each of the two reference voltages. 8. An input digital signal is divided into an upper bit group and a lower bit group, and the upper bit group digital signal is D
A DA converter that performs A conversion and a DA converter that DA converts a digital signal obtained by adding 1 to the least significant bit of the bit group, and a DA converter that DA converts the digital signal of the bit group to the lower bit group is provided. Prepare,
If the analog voltage value obtained by DA converting the digital signal of the upper bit group with respect to the given reference voltage is outside the predetermined range, the DA converted value is output, and if the analog voltage value is within the predetermined range, Using the analog voltage value and the DA converted value at the reference voltage by the digital signal obtained by adding 1 to the least significant bit of the digital signal of the upper bit group as a reference voltage, the digital signal of the lower bit group is DA converted to obtain an output. At the same time, in each DA converter, a switch that switches between two reference voltages of the DA converter according to each bit of the digital input signal is connected in series to the 2R resistance portion of the voltage dividing R-2R ladder resistance circuit. Two analog switches that include a PMOS transistor and an NMOS transistor DA converter, characterized in that provided respectively for the reference voltage.