JPH0611526Y2 - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH0611526Y2 JPH0611526Y2 JP1988089673U JP8967388U JPH0611526Y2 JP H0611526 Y2 JPH0611526 Y2 JP H0611526Y2 JP 1988089673 U JP1988089673 U JP 1988089673U JP 8967388 U JP8967388 U JP 8967388U JP H0611526 Y2 JPH0611526 Y2 JP H0611526Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- substrate
- ceramic substrate
- resistor
- lead pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 43
- 239000000919 ceramic Substances 0.000 claims description 36
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000003973 paint Substances 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 7
- 238000010304 firing Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004927 clay Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 この考案は、セラミック基板の表面に回路パターンが印
刷形成された回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a circuit board having a circuit pattern printed on the surface of a ceramic substrate.
一般にセラミックスは硬度が高く耐環境性が良いため、
絶縁基板としても良好な材料であり、特に過酷な環境で
使用される回路基板に適している。Generally, since ceramics have high hardness and good environmental resistance,
It is also a good material as an insulating substrate, and is particularly suitable for circuit boards used in harsh environments.
ここで、セラミックスの基板表面に回路パターンを交差
させて配設する必要がある場合、単に絶縁被膜を介して
回路パターンを交差させているだけであり、交差部分が
凸になっていた。Here, when it is necessary to dispose the circuit patterns on the surface of the ceramic substrate so as to intersect with each other, the circuit patterns are simply intersected with each other through the insulating film, and the intersecting portions are convex.
上記従来の技術の場合、回路基板を可変抵抗器等に用い
た場合、回路パターンの交差部分の凸部で摺動子が強く
当り、回路パターンや摺動子の摩耗及び摺動特性の悪化
を招き、さらにこの凸部での出力特性も悪くなりノイズ
やドロップアウトが生じたりする。In the case of the above-mentioned conventional technique, when the circuit board is used for a variable resistor or the like, the slider hits strongly at the convex portion at the intersection of the circuit patterns, which causes wear of the circuit pattern or the slider and deterioration of the sliding characteristics. In addition, the output characteristics of the convex portion are deteriorated, and noise or dropout occurs.
また、これを避けるためにリードパターン等をセラミッ
ク基板の裏面に設け、基板に導電スルーホール等を形成
したものもあるが、加工工数や導体の印刷焼成回数が増
加しコストが上昇してしまうという欠点がある。In order to avoid this, there is a case where a lead pattern or the like is provided on the back surface of the ceramic substrate and a conductive through hole or the like is formed in the substrate, but the number of processing steps and the number of times the conductor is printed and fired increases, which leads to an increase in cost. There are drawbacks.
さらに、セラミックスは脆性材料であり、焼成後にセラ
ミック基板に孔や溝を形成するのは強度上好ましくな
く、加工も難しい。Further, ceramics is a brittle material, and it is not preferable in terms of strength to form holes or grooves in the ceramic substrate after firing, and processing is difficult.
また、可変抵抗器の場合、抵抗体端部に接続するリード
パターンを回路基板と抵抗体との間に設けるので、抵抗
体端部に段差部が形成され、そのため、摺動子がこの段
差部を摺動する際、接触圧や接触面積の変化等の理由に
よって、抵抗値がその箇所で局部的に増大する、いわゆ
るポップオフ現象が発生するという問題点もある。Further, in the case of the variable resistor, since the lead pattern connected to the end of the resistor is provided between the circuit board and the resistor, a step is formed at the end of the resistor. There is also a problem that a so-called pop-off phenomenon occurs in which the resistance value locally increases at the location when sliding on the slide due to a change in contact pressure or contact area.
この考案は上記従来の技術に鑑みて成されたもので、耐
環境性が良く摺動子の摺接部に凹凸がなく強度も高い回
路基板を提供することを目的とする。The present invention has been made in view of the above-mentioned conventional technique, and an object thereof is to provide a circuit board having good environment resistance and no unevenness in a sliding contact portion of a slider and high strength.
この考案は、セラミック基板の中央部に電極を備え、該
電極を囲む状態で絶縁被膜をリング状に印刷形成し、更
に該絶縁被膜上に一方に切れ目を有するリング状の抵抗
体を印刷形成してあり、中央部の電極及び前記抵抗体の
各端部とリードパターンを介して接続されている電極
が、該基板の端縁部にそれぞれ設けてある回路基板にお
いて、前記リードパターンは、前記セラミック基板の表
面に基板形成と同時に設けられた断面が円弧状又は角部
を形成せずに組合せた直線と曲線から成る溝を導電塗料
で基板面とほぼ面一となるように埋めて焼成してある回
路基板である。In this invention, an electrode is provided in the center of a ceramic substrate, an insulating coating is printed in a ring shape so as to surround the electrode, and a ring-shaped resistor having a cut on one side is printed on the insulating coating. In the circuit board, in which the central electrode and the electrodes connected to the respective end portions of the resistor via the lead pattern are respectively provided at the edge portions of the substrate, the lead pattern is the ceramic The cross section provided on the surface of the substrate at the same time as the substrate was formed was filled with conductive paint so that the groove formed by a combination of straight lines and curved lines without forming arcs or corners was flush with the substrate surface and baked. It is a certain circuit board.
また、この考案はセラミック基板上に一方に切れ目を有
するリング状の抵抗体を印刷形成し、該抵抗体の各端部
と接続するリードパターンをそれぞれ設けてある回路基
板において、前記リードパターンは、前記セラミック基
板の表面に基板形成と同時に設けられた断面が円弧状又
は角部を形成せずに組合せた直線と曲線から成る溝を導
電塗料で基板面とほぼ面一となるように埋めて焼成して
ある回路基板である。Further, according to the present invention, in a circuit board in which a ring-shaped resistor having a cut on one side is formed by printing on a ceramic substrate and a lead pattern for connecting to each end of the resistor is provided, the lead pattern is The ceramic substrate is formed on the surface of the ceramic substrate at the same time as the substrate is formed, and the groove formed by combining straight lines and curved lines without forming arcs or corners is filled with conductive paint so as to be substantially flush with the substrate surface and baked. It is a printed circuit board.
この考案の回路基板は、セラミックスの基板に成形時よ
り溝を設けておき、この溝にリードパターンを配設し
て、回路基板表面の凹凸を少くしたものである。The circuit board of the present invention is one in which a groove is provided in a ceramic substrate from the time of molding and a lead pattern is arranged in this groove to reduce irregularities on the surface of the circuit board.
以下、この考案の一実施例について図面に基づいて説明
する。An embodiment of the present invention will be described below with reference to the drawings.
この実施例の回路基板は、セラミック基板１の表面に焼
成時に既に形成され断面が円弧状の溝２が設けられ、こ
の溝２は、セラミック基板１の一方の端縁近傍から中央
部付近に向って直線的に形成されている。この溝２は、
10〜20μｍ程度に形成され、AgPdペースト等の導体ペー
ストが印刷され焼成されてリードパターン３を形成して
いる。このリードパターン３は、セラミック基板１の一
方の端縁部に形成された電極４に接続しているととも
に、セラミック基板１の中央部の電極５にも他端が接続
している。このリードパターン３の表面は、焼成により
セラミック基板１の表面とほぼ同一平面上に位置してい
る。In the circuit board of this embodiment, a groove 2 having an arc-shaped cross section which is already formed at the time of firing is provided on the surface of the ceramic substrate 1. The groove 2 extends from the vicinity of one edge of the ceramic substrate 1 toward the vicinity of the central portion. Are formed linearly. This groove 2
The lead pattern 3 is formed by forming a conductive paste such as an AgPd paste, which is formed to have a thickness of about 10 to 20 μm, and is baked. The lead pattern 3 is connected to an electrode 4 formed on one edge of the ceramic substrate 1, and the other end is also connected to an electrode 5 at the center of the ceramic substrate 1. The surface of the lead pattern 3 is located on the substantially same plane as the surface of the ceramic substrate 1 by firing.
セラミック基板１の表面には、さらに、リング状にリー
ドパターン３と交差して中央の電極５を囲むように絶縁
被膜６が形成されている。さらに、この絶縁被膜６の上
に、カーボンペースト等の抵抗体７が12±３μｍ程度の
厚さで印刷形成されている。この抵抗体７の両端は、リ
ードパターン８，９に各々接続し、このリードパターン
８，９は各々電極10,11に接続している。An insulating coating 6 is further formed on the surface of the ceramic substrate 1 so as to cross the lead pattern 3 in a ring shape and surround the central electrode 5. Further, a resistor 7 such as a carbon paste is printed and formed on the insulating coating 6 with a thickness of about 12 ± 3 μm. Both ends of the resistor 7 are connected to lead patterns 8 and 9, respectively, and the lead patterns 8 and 9 are connected to electrodes 10 and 11, respectively.
この回路基板の製造方法は、まずセラミック基板１を焼
成する。この方法には、セラミックスの基材を粘土状に
して、軟い状態で成形し、この成形時に溝２をパンチ金
型により形成した後焼成する方法と、セラミックスの基
材のパウダーを乾燥状態で金型でプレスして固め、この
時同時に溝２も形成し、このプレスしたものを焼成して
セラミックスの基材を得る方法とがある。In this circuit board manufacturing method, first, the ceramic substrate 1 is fired. In this method, a ceramic base material is made into a clay shape, molded in a soft state, and at the time of molding, the groove 2 is formed by a punch die, followed by firing, and a ceramic base material powder in a dry state. There is a method in which a die is pressed and solidified, and at the same time, the groove 2 is also formed, and the pressed material is fired to obtain a ceramic base material.
この後、焼成されたセラミック基板１の溝２にメタルグ
レーズペーストを塗布する。この際電極４，５，10,11
と他のリードパターン８，９も同時に印刷し、660〜800
℃程度の温度で焼成する。Then, the metal glaze paste is applied to the grooves 2 of the fired ceramic substrate 1. At this time, electrodes 4, 5, 10, 11
And other lead patterns 8 and 9 are printed at the same time, and 660 to 800
Bake at a temperature of about ℃.
次に絶縁被膜６を印刷し、硬化させる。その際、リード
パターン８，９上を絶縁被膜６で覆わないようにする。
そして、この上にカーボン又はメタルグレーズの抵抗体
７を印刷し硬化させる。この硬化は加熱又は紫外線によ
り行う。Next, the insulating coating 6 is printed and cured. At this time, the insulating patterns 6 are not covered on the lead patterns 8 and 9.
Then, a carbon or metal glaze resistor 7 is printed and cured on this. This curing is performed by heating or ultraviolet rays.
この回路基板は、抵抗体７に摺動子を摺接させて通常の
可変抵抗器に用いられる他、ポテンショメータ、ロータ
リーエンコーダ等にも用いることができるものである。This circuit board can be used not only for a normal variable resistor by sliding a slider on the resistor 7 but also for a potentiometer, a rotary encoder, or the like.
尚、この考案の回路基板は、上記実施例の様に抵抗体の
下にリードパターンを通す場合だけでなく、第１図の電
極４，５及び絶縁被膜６、リードパターン３がないもの
で、単に抵抗体パターンの終端部からリードパターンを
取り出す場合にもそのロードパターンの下に溝を設けて
応用可能である。The circuit board of the present invention is not limited to the case where the lead pattern is passed under the resistor as in the above-mentioned embodiment, but the circuit board without the electrodes 4, 5 and the insulating coating 6 and the lead pattern 3 of FIG. Even when the lead pattern is simply taken out from the end portion of the resistor pattern, the groove can be provided below the load pattern to be applied.
また、この考案のセラミック基板上に形成された溝は、
コ字型の溝の角を曲線上に形成してセラミック基板上に
設けたものでも良い。Also, the groove formed on the ceramic substrate of the present invention,
The corner of the U-shaped groove may be formed on a curve and provided on the ceramic substrate.
この考案の回路基板は、セラミックスの基材に溝を予め
形成した状態でセラミック基板を焼成し、この溝を埋め
るようにリードパターンを設け、このリードパターンの
表面がセラミック基板の表面とほぼ同一平面になるよう
に形成したので、その上に形成された抵抗体に段差がで
きることがなく、その表面に摺接する摺動子の摺動性を
極めて良好なものとすることができる。The circuit board of the present invention is such that a ceramic substrate is fired in a state where a groove is formed in advance on a ceramic substrate, and a lead pattern is provided so as to fill the groove, and the surface of the lead pattern is substantially flush with the surface of the ceramic substrate. Since the resistor is formed so as to have a step, a step is not formed on the resistor formed on the resistor, and the slidability of the slider that is in sliding contact with the surface can be made extremely excellent.
また、抵抗体とその両端のリードパターンとの段差もな
くすことができ、この部分での摺動制も良好なものとす
ることができる。Further, it is possible to eliminate the step between the resistor and the lead pattern at both ends thereof, and it is possible to improve the sliding control at this portion.
又、終端部に応用した場合、抵抗値変化特性の始端と終
端でのホップオフ現象を押えることができる。Further, when applied to the terminal end, it is possible to suppress the hop-off phenomenon at the start and end of the resistance value change characteristic.
しかも、この溝は、セラミック基板の焼成前に形成さ
れ、焼成によって硬化させられているので後の機械加工
で溝を作るのと異なり基板の他の部分にクラックや残留
応力等の悪影響を残すことがなく、脆性材料であるセラ
ミックスの強度を溝によって著しく低下させることがな
い。特に断面が円弧状に形成されている場合は、Ｖ字溝
のように応力集中がなく、溝の部分で割れやすいという
ことがなく、メタルグレーズの充填性も良い。Moreover, this groove is formed before firing the ceramic substrate and is hardened by firing, so unlike the case where the groove is formed by subsequent machining, it does not leave adverse effects such as cracks and residual stress on other parts of the substrate. Therefore, the strength of ceramics, which is a brittle material, is not significantly reduced by the grooves. In particular, when the cross section is formed in an arc shape, there is no stress concentration unlike the V-shaped groove, it is not easy to break in the groove portion, and the metal glaze filling property is good.
また、セラミック基板であることから、耐環境性が良
く、耐熱性が高いのでメタルグレーズペーストのリード
パターンを形成することができる。Further, since it is a ceramic substrate, it has good environment resistance and high heat resistance, so that a lead pattern of a metal glaze paste can be formed.
第１図はこの考案の回路基板の一実施例の正面図、第２
図は第１図Ａ−Ａ線の部分拡大断面図である。 １……セラミック基板、２……溝、３，８，９……リー
ドパターン、４，５，10,11……電極、６……絶縁被
膜、７……抵抗体FIG. 1 is a front view of an embodiment of the circuit board of the present invention, and FIG.
The drawing is a partially enlarged sectional view taken along the line AA in FIG. 1 ... ceramic substrate, 2 ... groove, 3,8,9 ... lead pattern, 4,5,10,11 ... electrode, 6 ... insulating film, 7 ... resistor
Claims (2)
電極を囲む状態で絶縁被膜をリング状に印刷形成し、更
に該絶縁被膜上に一方に切れ目を有するリング状の抵抗
体を印刷形成してあり、中央部の電極及び前記抵抗体の
各端部とリードパターンを介して接続されている電極
が、該基板の端縁部にそれぞれ設けてある回路基板にお
いて、前記リードパターンは、前記セラミック基板の表
面に基板形成と同時に設けられた断面が円弧状又は角部
を形成せずに組合せた直線と曲線から成る溝を導電塗料
で基板面とほぼ面一となるように埋めて焼成してあるこ
とを特徴とする回路基板1. A ceramic substrate is provided with an electrode at a central portion thereof, an insulating coating is printed in a ring shape in a state of surrounding the electrode, and a ring-shaped resistor having a cut on one side is printed on the insulating coating. In the circuit board in which the central electrode and the electrode connected to each end of the resistor through the lead pattern are respectively provided at the edge portions of the substrate, the lead pattern is A groove formed by a straight line and a curved line, which was formed on the surface of the ceramic substrate at the same time as the substrate was formed, was formed by arc-shaped or no corners, and was filled with conductive paint so that it was almost flush with the substrate surface and baked. Circuit board characterized by
リング状の抵抗体を印刷形成し、該抵抗体の各端部と接
続するリードパターンをそれぞれ設けてある回路基板に
おいて、前記リードパターンは、前記セラミック基板の
表面に基板形成と同時に設けられた断面が円弧状又は角
部を形成せずに組合せた直線と曲線から成る溝を導電塗
料で基板面とほぼ面一となるように埋めて焼成してある
ことを特徴とする回路基板2. A circuit board, wherein a ring-shaped resistor having a cut on one side is formed by printing on a ceramic substrate, and a lead pattern for connecting to each end of the resistor is provided. The groove formed by a straight line and a curved line which is provided on the surface of the ceramic substrate at the same time as the substrate is formed and which has a circular arc shape or no corner is combined is filled with a conductive paint so as to be substantially flush with the substrate surface and fired. Circuit board characterized by having
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089673U JPH0611526Y2 (en) | 1988-07-05 | 1988-07-05 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089673U JPH0611526Y2 (en) | 1988-07-05 | 1988-07-05 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0211374U JPH0211374U (en) | 1990-01-24 |
| JPH0611526Y2 true JPH0611526Y2 (en) | 1994-03-23 |
Family
ID=31314219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988089673U Expired - Lifetime JPH0611526Y2 (en) | 1988-07-05 | 1988-07-05 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611526Y2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53106465A (en) * | 1977-02-28 | 1978-09-16 | Akai Electric | Buried printed circuit substrate |
| JPS6039272U (en) * | 1983-08-25 | 1985-03-19 | 日本ビクター株式会社 | thick film circuit board |
-
1988
- 1988-07-05 JP JP1988089673U patent/JPH0611526Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0211374U (en) | 1990-01-24 |
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