JPH06120224A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the dead space of wiring which is to be caused by through holes arranged in the outer periphery of a macroblock, and reduce chip size. CONSTITUTION:In a semiconductor integrated circuit provided with a macroblock 1 and multilayere interconnection connected with the macroblock, a first wiring layer 2 connected with the macroblock 1 and a second wiring layer 3 to be connected with the first wiring layer 2 are mutually electrically connected via a through hole 5 formed in the macroblock. Thereby the dead space where other wiring detours around a through hole in the vicinity of the outer periphery of the macroblock is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a multilayer wiring structure in which element regions are formed as macro blocks.

[0002]

2. Description of the Related Art Conventionally, FIG. 2 shows an example of a semiconductor integrated circuit having an element region formed as a macroblock and having a multilayer structure, for example, a two-layer aluminum wiring structure, as a wiring structure connected to the macroblock. 2A is a partial plan view, and FIG. 2B is a cross-sectional view taken along the line BB. In these figures, reference numeral 1 is a macroblock which constitutes an element, and a power supply wiring 21 and a GND wiring 22 which are electrically connected to the macroblock 1 are constituted by a single aluminum wiring layer 2. In addition, the macro block 1 is connected to the power supply wiring 21 and the GND wiring 22 to connect the macro block 1 to an external power supply and
The power supply wiring 31 and the GND wiring 32 connected to D are mainly composed of the two-layer aluminum wiring layer 3. The first-layer aluminum wiring layer 2 and the second-layer aluminum wiring layer 3 are connected by a through hole 5 provided in a wiring region outside the macroblock 1. In addition, 6 is a semiconductor substrate, 7
Is an insulating film.

[0003]

In such a conventional semiconductor integrated circuit, in order to connect the one-layer aluminum wiring layer 2 in the macroblock 1 and the two-layer aluminum wiring layer 3 outside the macroblock 1, It is necessary to provide the through hole 5 in the wiring area outside the macro block. Therefore, the through hole 5 may prevent passage of the other wiring 4 formed of the one-layer aluminum wiring layer 2 and the two-layer aluminum wiring layer 3, and the other wiring 4 needs to be detoured at this portion. This portion becomes a dead space, which is an obstacle to increasing the density of the semiconductor integrated circuit and impairs the reduction in chip size. The purpose of the present invention is to
It is an object of the present invention to provide a semiconductor integrated circuit that eliminates dead space and can reduce the chip size.

[Means for Solving the Problems] The present invention is
A first wiring layer connected to the macroblock, and the first wiring layer
The second wiring layer connected to the second wiring layer is electrically connected to each other through a through hole provided in the macroblock.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and FIG.
Is a plan view of a main part, and FIG. 1B is a sectional view taken along line AA. In these figures, reference numeral 1 is a macroblock formed on a semiconductor substrate 6, on which an internal power supply wiring 21 and a GND wiring 22 formed by a one-layer aluminum wiring layer 2 are extended. The two-layer aluminum wiring layer 3 formed on the one-layer aluminum wiring layer 2 with the insulating film 7 interposed therebetween provides a power source external to the macroblock 1 and a G
A power supply wiring 31 and a GND wiring 32 connected to the ND are formed, and a part of the power supply wiring 31 and the GND wiring 32 are extended to the inside of the macro block 1 to be formed as lead portions 31a and 32a.

Through-holes 5 are provided in the extended portions 31a and 32a extended in the macroblock 1, and the through-holes 5 allow the first-layer aluminum wiring layer 2 and the second-layer aluminum wiring layer 3, that is, the power source. The wirings 21 and 31 and the GND wirings 22 and 32 are electrically connected to each other. By arranging the through hole 5 in the macro block 1 in this way, the through hole 5 does not exist at a position outside the macro block 1 and close to the outer edge of the macro block 1, whereby the macro block 1 is formed. The other wirings extending to the outside, especially the other wirings arranged in the vicinity of the outer edge of the macro block 1 are not bypassed by the through holes 5, and the dead space is eliminated. Therefore, the wiring density can be increased, and the chip size of the semiconductor integrated circuit can be reduced.

[0007]

As described above, according to the present invention, the first wiring layer connected to the macro block and the second wiring layer connected to the macro block are mutually connected by the through holes provided in the macro block. Since it is electrically connected to, it is not necessary to provide a through hole in the wiring area outside the macroblock to prevent the passage of other wiring, eliminating the dead space for bypassing other wiring and reducing the pellet size. There is an effect that can be.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, (a) is a plan view,
(B) is the AA line sectional view.

2A and 2B show a conventional example, FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line BB.

[Explanation of symbols]

1 macroblock 2 1 layer aluminum wiring layer (21 power wiring, 22
GND wiring) 3 Two-layer aluminum wiring layer (31 power wiring, 32
GND wiring) 4 Other wiring 5 Through hole

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a macroblock and comprising a plurality of wiring layers electrically connected to the macroblock, the first wiring layer being connected to the macroblock, and the first wiring layer being connected to the macroblock. A semiconductor integrated circuit characterized in that a second wiring layer connected to one wiring layer is electrically connected to each other through a through hole provided in the macroblock.