JPH06120812A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The objective is to obtain an accurate logic output for any phase relationship between two clock signals. [Structure] The phase detector 7 detects the phase difference between the clocks T1 and T2, and when this is smaller than a predetermined value by the comparator 8, the switch circuit 10 is controlled using the circuit output, and the delay circuit 9 is used. A clock T whose phase is delayed by a predetermined amount
2 is supplied to the clock input terminal T of DFF2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a configuration in which each logic circuit is driven by an asynchronous clock, and more particularly to a semiconductor integrated circuit provided with a malfunction prevention circuit for preventing malfunction thereof. Is.

[0002]

2. Description of the Related Art FIG. 8 shows a semiconductor integrated circuit including a logic circuit having two clock inputs. In the figure, reference numeral 1 denotes a front-stage D (Delayed) flip-flop in which a signal input terminal IN5 is connected to a data input terminal D thereof. Circuit (hereinafter, DFF).
Reference numeral 2 is a rear-stage DFF which receives the output of the output terminal Q of the DFF 1 as a data input, and its output terminal Q is the output terminal O of the circuit.
It is connected to the UT6. This type of flip-flop outputs Q when the pulse is input to the clock input T when the input D is at the H level, and outputs Q when the pulse is input at the input T when the input D is at the L level. Has a logical function of L level. Reference numerals 3 and 4 are clock input terminals to which the clocks T1 and T2 are input.

Next, the operation will be described. In the semiconductor integrated circuit of FIG. 8, for example, when signals each having a waveform as shown in FIG. 9 are input, for example, when both clock T1 and clock T2 are synchronized by an internal signal (indicated by a solid line in the figure). At the rising edge (1) of the clock T1 of the DFF1, the L level signal input to the input terminal IN5 is output to the output terminal Q of the DFF1 and the H level signal is output to the output terminal Q at the next rising edge (2). Output to. At this time, since there is a time required for signal processing in DFF1,
The output signal a changes with a slight delay from the rising timing of the clock T1.

Next, the time when the output signal a of DFF1 which is the input of the subsequent DFF2 is inverted and becomes H level is the reference point.
As (3), if the clock T2 rises before the hold time of the DFF2, that is, before the time required for the DFF2 to judge the signal level input to its input terminal D (4), the output terminal Q of the DFF2 is L level is output to the output terminal OUT6 connected to
(3) When the clock T2 rises after the setup time of the DFF2, that is, after the time required for the DFF2 to judge the level of the signal a input to the input terminal D by the rise of the clock T2 (5) H level is output to the output terminal OUT6.

Next, for example, when the clock T1 is an external signal and the clock T2 is an internal signal and is asynchronous (shown by a broken line in the drawing), the operation of the DFF1 is the same, but in the DFF2, the hold time setup is particularly performed. Since the clock T2 rises (6) within the time, the level of the signal a input to the input terminal D cannot be correctly determined and the output terminal OUT6 becomes indefinite.

[0006]

The conventional semiconductor integrated circuit is constructed as described above. For example, when the clock T1 is an external signal and the clock T2 is an internal signal and is not synchronized, a flip-flop in the subsequent stage is used. The input signal and the clock T2 for driving it may have the same timing, and the output of the flip-flop receiving these two signals becomes unstable (indefinite state) and outputs an accurate logical result. There was a problem that I could not do it.

The present invention has been made to solve the above problems, and an accurate logical result output can be obtained regardless of the phase relationship of the clock signals driving each flip-flop. The purpose is to obtain a semiconductor integrated circuit.

[0008]

A semiconductor integrated circuit according to the present invention detects a phase of a clock signal input to each flip-flop, and when the phase difference is a predetermined value or less, the semiconductor integrated circuit is input to a subsequent stage side. A phase difference that delays the phase of the clock signal or the output signal of the front-stage flip-flop by a predetermined amount to give a predetermined phase difference between the clock signal input to the rear-stage flip-flop and the output signal of the front-stage flip-flop. It is provided with setting means.

[0009]

In the present invention, the phase difference setting means is provided,
The phase relationship of the clock signals that drive each flip-flop is always detected, and when it is detected that this phase relationship is the timing at which the subsequent flip-flop malfunctions, the phase is changed so that the circuit does not malfunction. By doing so, the correct logical result is always obtained.

[0010]

EXAMPLES Example 1. Examples of the present invention will be described below. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention, in which the same reference numerals as those in FIG. 8 designate the same or corresponding parts, and 7 denotes an input terminal 3 of a clock T1 and an input terminal 4 of a clock T2. , A phase detector that detects the phase of each clock and outputs the phase difference signal,
8 is a comparator with hysteresis which receives the output signal c of the phase detector 7, 9 is a delay circuit (DL) for delaying the clock T2 input to the input terminal 4, and 10 is a clock signal T2 of the input terminal 4 A switch circuit for selecting the output signal of the delay circuit 9 and outputting either of the signals, 11
Is a constant voltage source that determines the threshold value of the comparator 8 by the voltage Vr.

Next, the operation will be described with reference to FIG. Since the operation of the DFF1 is the same as the conventional one,
Here, the operation of the DFF 2 will be mainly described.

In the phase detector 7, as shown in FIG. 2 (a),
A voltage Vb proportional to the phase error amount | φT1−φT2 | between the phase φT1 of the clock T1 and the phase φT2 of the clock T2 is output, and the output Vb is input to the hysteresis comparator 8 to be shown in FIG. You will get output like this:
That is, when the phase error amount | φT1−φT2 |> φA, the output c of the comparator 8 becomes “H”, and | φT1−φT2 |
When φ <B, it becomes'L '. In the delay circuit 9, the phase of the clock T2 is always delayed by a predetermined amount .DELTA..phi.Td2.

The switch circuit 10 receives this output c, and when the output c is'H '(| φT1−φT2 |> φA),
A clock T2 with no delay is selected and its output is φc =
φT2. On the other hand, when the output c of the comparator 8 is'L '(| φT1−φT2 | <φB), the output of the delay circuit 9 which is the delay signal of the clock T2 is selected and its output is φc.
= ΦT2d. Then, any one of the selected signals φc is input to the clock input terminal T of the DFF 2 in the subsequent stage. However, the delay amount of the delay circuit 9 ΔφT2d = φT2d−
φT2).

In the above configuration, 2 × φB + φ (tHold) <ΔφT2d <2π-2 × φA + φ (tSetup) (tHold; DFF2 hold time, tSetup; DFF
2 setup time)
As shown in, when the phase difference between the clocks T1 and T2 is small and a malfunction may occur (| φT1−φT2 |
For <φB), the switch circuit 10 selects a clock having a phase difference of ΔφT2d, which is the output of the delay circuit 9,
It is input to the clock input terminal T of DFF2.

On the other hand, as shown in FIG. 4, when the phase difference between the clocks T1 and T2 is large (| φT1−φT2 |> φA),
Since there is little possibility of malfunction, the switch circuit 10 selects the input of the clock terminal 4 and the clock T2 having no delay is input to the clock input terminal T of the DFF2.

As described above, according to this embodiment, the clock T input to the DFF1 and DFF2 by providing the phase detector 8 is provided.
When the phases of 1 and T2 are detected, the phase difference signal Vb is created, this is compared with a predetermined value in the comparator 8, and when it is determined that the value is smaller than the predetermined value in which malfunction may occur. Controls the switch circuit 10 by its output signal c, delays the phase of the clock T2 by a predetermined amount by the delay circuit 9 and inputs this to the clock input terminal T of the DFF2. During the hold time, signals having the same phase are not input to the clock input terminal T and the signal input terminal D, and the correct logical result is always output regardless of the phase relationship of the clocks driving the DFF1 and DFF2.
Can be obtained in UT6.

Example 2. Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to FIG. As shown in the figure, in this embodiment, the delay circuit 9 is provided in the subsequent stage of the DFF1, and the output of the delay circuit 9 and the output of the DFF1 are switched by the switch circuit 10 to be output to the subsequent stage DFF2.

Next, the operation will be described. Phase detector 7
If the phase difference between the clock T1 and the clock T2 is small and there is a high possibility that a malfunction will occur, as shown in FIG. 6, a signal obtained by delaying the phase of the signal a by ΔφT2d by the delay circuit 9 is generated by the switch circuit 10 as shown in FIG. It is selected and input to the signal input terminal D of the DFF 2 in the subsequent stage.

On the other hand, in the phase detector 7, the clock T1
When the phase difference between the clock signal T2 and the clock T2 is large and the possibility of malfunction is low, as shown in FIG.
At 0, the output of DFF1 in the previous stage is the same as that of DFF2 in the subsequent stage.
The selection is performed so that the signal is input to the signal terminal D of the. With this configuration, the same effect as that of the above-described embodiment can be obtained.

In the above embodiment, the DF is used as the logic circuit.
Although description has been made using F, other logic circuits such as an RS flip-flop may be used, and the number of connection stages is not limited to two, and three or more stages can be provided by providing a similar circuit between each flip-flop. The same effect can be obtained by being applicable to a plurality of DFFs connected.

[0021]

As described above, according to the semiconductor integrated circuit of the present invention, the phase relation of the clock signals for driving the respective flip-flops is always detected, and this phase relation causes the latter-stage flip-flop to malfunction. In the case of timing, since the phase is changed so that the circuit does not malfunction, there is no need to consider the phase relationship between the clocks input to each flip-flop. Even when it is used, there is an effect that a normal signal can be obtained at the output.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing characteristics of a hysteresis comparator used in the semiconductor integrated circuit.

FIG. 3 is a diagram showing a timing chart of the semiconductor integrated circuit when there is a phase change.

FIG. 4 is a diagram showing a timing chart of the semiconductor integrated circuit when there is no phase change.

FIG. 5 is a circuit configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a timing chart of the semiconductor integrated circuit when there is a phase change.

FIG. 7 is a diagram showing a timing chart of the semiconductor integrated circuit when there is no phase change.

FIG. 8 is a circuit configuration diagram of a conventional semiconductor integrated circuit.

FIG. 9 is a diagram showing a timing chart for explaining the operation of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 2 D flip-flop 3, 4, 5 input terminal 6 output terminal 7 phase detector 8 hysteresis comparator 9 delay device (Delay Line) 10 switch circuit 11 constant voltage source

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which an output of a front-stage flip-flop is used as an input signal of a rear-stage flip-flop and each flip-flop is driven by an asynchronous clock signal, the phase of the clock signal input to each flip-flop is detected. If the phase difference is less than or equal to a predetermined value, the phase of the clock signal input to the rear stage side or the output signal of the front stage side flip-flop is delayed by a predetermined amount and the clock input to the rear stage side flip-flop is delayed. A semiconductor integrated circuit comprising phase difference setting means for providing a predetermined phase difference between a signal and an output signal of the preceding flip-flop.