JPH06124257A - Serial I / O control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] When serial transfer between a plurality of devices, for example, when a timer microcomputer uses an external clock as a transfer clock, it enables communication with other devices after the serial transfer is completed. [Configuration] Output terminal SO for serial I / O control register
A bit is provided to switch the UT to high impedance or active. Furthermore, when the external clock changes from "H" to "L" is detected, the output terminal SO is automatically
Bit control means for returning the UT to the active state is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial input / output control circuit, and more particularly to a serial input / output control circuit that enables communication between other devices in serial transfer between a plurality of devices.

[0002]

2. Description of the Related Art A serial input / output control circuit (hereinafter referred to as a serial I / O control circuit) is provided between a plurality of devices, for example,
As shown in FIG. 5, a timer microcomputer 51, a system controller 52, an on-screen display 53, or an electrically writable RO (not shown)
It is a device necessary for serial transfer between M (hereinafter referred to as EPROM) and the like. An internal clock or an external clock can be used as the transfer clock of the serial I / O control circuit.

FIG. 6 is a timing chart showing the operation of this conventional serial I / O control circuit. When using the internal clock as the transfer clock,
When counting the number of times, the transfer clock is stopped in the state of "H", and the serial I / O ends the transfer of 1 byte for both input and output. After that, at the ninth fall of the internal clock, the serial I / O output (hereinafter referred to as SOUT)
The terminal is in the high impedance state. When an external clock is used as the transfer clock, when the transfer clock is counted 8 times, the transfer clock stops in the “H” state and ends the transfer of 1 byte, but the transfer clock and the internal clock are not synchronized, so the output pin SOUT is not in a high impedance state.

When a plurality of devices (timer microcomputer, system controller, on-screen display, EPROM, etc.) communicate with each other, the timer microcomputer outputs data to the other devices so that the other devices can communicate with each other. It is necessary to make SOUT high impedance. When the timer microcomputer communicates using the external clock as the transfer clock, the output terminal SOUT does not become high impedance after the transfer is completed. Therefore, the timer microcomputer cannot communicate using the external clock as the transfer clock.

[0005]

[Problems to be Solved by the Invention] Conventional serial I / O
When the external clock is used as the serial I / O transfer clock, the control circuit outputs the output terminal SO after the data transfer is completed.
The UT does not enter the high impedance state. Therefore, between multiple devices (timer microcomputer, system controller, on-screen display, EPRO
If the timer microcomputer uses an external clock as a transfer clock in (M, etc.), communication between other devices cannot be performed after data transfer.

The present invention has been made in order to solve the above-mentioned problems, and in serial transfer between a plurality of devices, the output terminal of the serial I / O is set to high impedance or active, so that another An object is to provide a serial I / O control circuit that enables communication between devices. Another object of the present invention is to provide a serial I / O control circuit that can activate the output terminal of the serial I / O for the next transfer request after the transfer is completed.

[0007]

A serial I / O control circuit according to a first aspect of the present invention is a serial I / O output terminal S.
The serial I / O control register 7 for setting a bit for switching OUT to high impedance or active is provided.

A serial I / O control circuit according to a second aspect of the present invention includes a serial I / O control register 7 for setting a bit for switching the output terminal SOUT of the serial I / O to high impedance or active, and the serial I / O control register 7. A high impedance / active switching circuit 6 that makes the output terminal SOUT of the serial I / O high impedance or active by the output of the I / O control register 7, and the serial I / O control register that detects a level change of an external clock. The bit control means 21 is provided for changing the 7th bit and returning the output terminal SOUT of the serial I / O to the active state.

[0009]

In the invention of claim 1, the serial I / O control register 7 sets a bit for switching the output terminal SOUT of the serial I / O to high impedance or active.

In the second aspect of the invention, the serial I / O control register 7 sets a bit for switching the output terminal SOUT of the serial I / O to high impedance or active, and the high impedance / active switching circuit 6 uses the serial I / O. The output of the O control register 7 makes the output terminal SOUT of the serial I / O high impedance or active. The bit control means 21 detects the level change of the external clock and changes the bit of the serial I / O control register 7 to return the output terminal SOUT of the serial I / O to the active state.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a serial I according to an embodiment of the invention.
It is a block diagram which shows the structure of the / O control circuit. In FIG. 1, 1 is a frequency divider that divides the internal clock input, 2 is a clock switching circuit that switches the output clock of the frequency divider 1 and external clock input, and 3 is a serial that counts the transfer clock from the clock switching circuit 3. I / O counter, 4 is a serial I / O shift register that sets and shifts serial I / O input, and 5 is port input / output and output terminal S
Port input / output / SOUT switching circuit for switching OUT,
Reference numeral 6 is a high impedance / active switching circuit that switches the output terminal SOUT of the serial I / O to high impedance or active, and 7 is a serial I / O control register that sets a bit for switching the output terminal SOUT to high impedance or active. . Reference numeral 21 is a bit control means for detecting a level change of the external clock and changing the bit of the serial I / O control register 7 to return the output terminal SOUT of the serial I / O to the active state.

FIG. 2 is a timing chart showing the operation of the serial I / O control circuit of FIG. The operation of this embodiment will be described with reference to FIGS. The transfer clock can be selected by the clock switching circuit 2 from either the internal clock divided by the frequency divider 1 or the external clock. When the bit SM3 of the serial I / O control register 7 is set to "1", it can be set to the SOUT port, and when the bit SM3 is set to "0", it can be set to the input / output port.
Hereinafter, when the bit SM3 is “1”, that is, SOUT
The following describes when the port is set. When the transfer clock is counted eight times by the serial I / O counter 3, the transfer clock stops in the "H" state. As for the output of the serial I / O, the transfer clock is counted eight times by the serial I / O counter 3 to end the transfer of 1 byte, and the serial I / O input is also input to the serial I / O shift register 4.
When the transfer clock is counted 8 times, the reception of 1-byte data is completed.

When the transfer clock is an external clock, the serial transfer interrupt request is received at the eighth rise of the transfer clock from "L" to "H". Then, the interrupt handler in the bit control means 21 is activated and the serial I / O
The bit SM7 of the O control register 7 is set to "1". The output terminal SOUT can be set to high impedance by setting the bit SM7 to "1". When it is detected that the external clock has fallen from "H" to "L", "1" set in the bit SM7 is cleared to "0" to make it active.

FIG. 3 is a circuit diagram of one bit of the serial I / O control register 7. The operation of one bit of the serial I / O control register 7 will be described. When writing data to the 7th bit SM7 of the serial I / O control register 7, the WR signal is "H" and the RD signal is "L".
Is. Conversely, when reading data, the WR signal is "L" and the RD signal is "H". After resetting, RESET = “L”, WR = “L”, RD =
It becomes "L" and SM7 becomes "0". During operation, RE
SET = “H”. After the transfer of 1-byte data,
The transfer clock stops in the "H" state. WR =
“H”, RD = “L”, SM7 = “0”, when an “H” signal is input from the data bus, the output of the NAND gate 31 becomes “H” and the output of the NAND gate 32 becomes “L”.
7 = “1”. SM with WR = "L" and RD = "H"
7 = “1” data becomes the data bus, and SOUT becomes high impedance. Next, WR = “H”, RD =
“L”, RESET = “H”, transfer clock is “L”,
When an "L" signal is input from the data bus, SM7 becomes "1".
Therefore, the output of the NAND gate 31 is "H", NAN
The output of the D gate 32 becomes "H" and SM7 becomes "0". When WR = “L” and RD = “H”, SM7 = “0” data is transferred to the data bus, and the output terminal SOUT is activated.

FIG. 4 shows a control circuit for the serial I / O output and SOUT. It is assumed that the point A in FIG. 4 is "H" and the point B is "H". Serial I / O control register 7
The third bit SM3 of "1" is "1" because the port is set to the SOUT port. When SM7 becomes "H", both the P-channel transistor 41 and the N-channel transistor 42 are turned off and become high impedance. When SM7 = "0", it becomes active and the serial I / O output SOUT outputs "H" if the transmission data from the serial I / O shift register is "H" and outputs "L" if it is "L". To be done.

As described above, according to the above embodiment, since the serial I / O control register is provided with the bit for switching the output terminal SOUT to the high impedance (Hi-Z) or active, the serial transfer is completed when the serial transfer is completed. In response to an interrupt request, the above bit can be set in the interrupt processing routine to make it high impedance. Further, it is possible to detect that the external clock has fallen from "H" to "L" in response to the next transfer request, clear the above bits, and make the output terminal SOUT active. This enables communication with other devices in serial transfer between a plurality of devices.

[0017]

As described above, according to the invention of claim 1,
Since the serial input / output control register for setting the bit for switching the serial input / output output terminal to high impedance or active is provided, the serial I / O output terminal can be set to high impedance or active. With this, it is possible to obtain an effect that communication between other devices becomes possible.

According to the invention of claim 2, a serial input / output control register for setting a bit for switching the output terminal of the serial input / output to high impedance or active, and the serial input / output control register by the output of the serial input / output control register. A high-impedance / active switching circuit that makes the output terminal of the output high impedance or active, and changes the level of the external clock to change the bit of the serial input / output control register and return the output terminal of the input / output to the active state. Since the bit control means is provided, the same effect as the above effect can be obtained, and the effect that the output terminal of the input / output can be returned to the active state by detecting the level change of the external clock is obtained. To be

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial I / O control circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of this embodiment.

FIG. 3 is a circuit diagram of a control circuit related to the 7th bit of the serial I / O control register in FIG.

FIG. 4 shows the serial I / O output and S in this embodiment.
It is a circuit diagram of a control circuit of OUT.

FIG. 5 is a block diagram showing a configuration of a serial transfer communication system.

FIG. 6 is a timing chart showing an operation of a conventional serial I / O control circuit.

[Explanation of symbols]

 6 high impedance / active switching circuit 7 serial I / O control register 21 bit control means

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[Procedure amendment]

[Submission date] December 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a serial I according to an embodiment of the present invention.
It is a block diagram which shows the structure of the / O control circuit. In FIG. 1, 1 is a frequency divider that divides the internal clock input, 2 is a clock switching circuit that switches the output clock of the frequency divider 1 and external clock input, and 3 is a serial that counts the transfer clock from the clock switching circuit 2. I / O counter, 4 is a serial I / O shift register that sets and shifts serial I / O input, and 5 is port input / output and output terminal S
Port input / output / SOUT switching circuit for switching OUT,
Reference numeral 6 is a high impedance / active switching circuit that switches the output terminal SOUT of the serial I / O to high impedance or active, and 7 is a serial I / O control register that sets a bit for switching the output terminal SOUT to high impedance or active. . Reference numeral 21 is a bit control means for detecting a level change of the external clock and changing the bit of the serial I / O control register 7 to return the output terminal SOUT of the serial I / O to the active state.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

When the transfer clock is an external clock, the serial transfer interrupt request is received at the eighth rise of the transfer clock from "L" to "H". Then, the interrupt handler in the bit control means 21 is activated and the serial I / O
The bit SM7 of the O control register 7 is set to "1". The output terminal SOUT can be set to high impedance by setting the bit SM7 to "1". Next
External clock from "H" to "L" in response to the transfer request of
It is detected that the signal has fallen to 0, and the "1" set in the bit SM7 is cleared to "0" to activate it.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (2)

[Claims] 1. A serial input / output control circuit for controlling serial transfer of data between a plurality of devices, comprising a serial input / output control register for setting a bit for switching an output terminal of serial input / output to high impedance or active. A serial input / output control circuit characterized by being provided. 2. A serial input / output control circuit for controlling serial transfer of data between a plurality of devices, and a serial input / output control register for setting a bit for switching an output terminal of serial input / output to high impedance or active. , A high impedance / active switching circuit that makes the output terminal of the serial input / output high impedance or active by the output of the serial input / output control register, and detects the level change of the external clock to set the bit of the serial input / output control register. A serial input / output control circuit provided with bit control means for changing the output terminal of the input / output to the active state.