JPH06125033A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH06125033A
JPH06125033A JP4272631A JP27263192A JPH06125033A JP H06125033 A JPH06125033 A JP H06125033A JP 4272631 A JP4272631 A JP 4272631A JP 27263192 A JP27263192 A JP 27263192A JP H06125033 A JPH06125033 A JP H06125033A
Authority
JP
Japan
Prior art keywords
semiconductor element
tab
frame
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4272631A
Other languages
Japanese (ja)
Inventor
Tadayoshi Tanaka
直敬 田中
Asao Nishimura
朝雄 西村
Akihiro Yaguchi
昭弘 矢口
Ryuji Kono
竜治 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4272631A priority Critical patent/JPH06125033A/en
Publication of JPH06125033A publication Critical patent/JPH06125033A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a thin semiconductor device which has excellent resistance against the reflow of solder. CONSTITUTION:Slopes are formed on inner edges of a frame tub 2 supporting a semiconductor element 1 that has corresponding slant sides on which it is bonded to the tub 2 with a bonding agent 6. Since side faces of the element 1 are supported on the slopes of the tub 2, the element 1 can be easily mounted on the tub 2 in a highly stable state. Therefore, the problem encountered when the element is mounted by the conventional technique can be solved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、樹脂封止型半導体装置
の構造に係り、特に、薄型化かつ耐はんだリフロー性に
優れた半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a resin-encapsulated semiconductor device, and more particularly to a semiconductor device which is thin and has excellent solder reflow resistance.

【0002】[0002]

【従来の技術】半導体装置の薄型化及び耐はんだリフロ
ー性向上に最も効果的であると考えられる方法の一つと
して、図3の半導体装置側面断面図で示すように、半導
体素子1と封止樹脂5の接着性がタブ2と封止樹脂5の
それに比べかなり良いことを利用して、タブ2を枠状タ
ブにし、そこに半導体素子1をはめ込み、素子下面と樹
脂を接着させて接着界面を強化させる方法があり、例え
ば、特開昭58−52852 号,特開平2−119255 号公報によ
り知られている。
2. Description of the Related Art As one of the most effective methods for thinning a semiconductor device and improving solder reflow resistance, as shown in a side sectional view of a semiconductor device in FIG. Utilizing the fact that the adhesiveness of the resin 5 is considerably better than that of the tab 2 and the sealing resin 5, the tab 2 is formed into a frame-like tab, the semiconductor element 1 is fitted therein, and the resin is adhered to the lower surface of the element to form an adhesive interface. There is a method for strengthening the above-mentioned structure, which is known, for example, from Japanese Patent Laid-Open Nos. 58-52852 and 2-119255.

【0003】[0003]

【発明が解決しようとする課題】上記従来技術のうち、
特開昭58−53852 号公報記載の技術では、半導体素子側
面と枠タブ内側側面の互いの鉛直面で保持するため、接
着剤を介して保持する場合、接着剤が硬化するまで素子
を加熱雰囲気中で支持しなければならず、支持方法が適
切でないと枠タブからの素子の抜け落ちや両者のはめ合
い寸法差から生じるがたにより素子が枠タブに対して曲
がって固定される恐れがある。また、支持を不必要にす
るために枠タブ内側側面に突起を設けると、枠タブ内側
側面で素子を保持することは可能だが、従来の吸着支持
では素子のはめ込みが困難となり実用上不都合な問題と
なる。
Of the above-mentioned conventional techniques,
In the technique described in Japanese Patent Laid-Open No. 58-53852, since the semiconductor element side surface and the frame tab inner side surface are held on the vertical planes of each other, when they are held via an adhesive, the element is heated in a heated atmosphere until the adhesive is cured. If the support method is not proper, the element may be bent and fixed to the frame tab due to the dropout of the element from the frame tab or the looseness caused by the fitting size difference between the two. Also, if a protrusion is provided on the inner side surface of the frame tab to make support unnecessary, it is possible to hold the element on the inner side surface of the frame tab, but it is difficult to fit the element with the conventional suction support, which is a practical problem. Becomes

【0004】また、特開平2−119255 号公報に記載の技
術では、枠タブと素子の線膨張差を利用して、焼ばめ的
に枠タブ側面と素子側面を固定するというものである
が、固定するためには加熱雰囲気中で素子を枠タブ中に
装着しなければならず、かつ室温に冷えるまでの間素子
を支持しておく必要がある。さらに焼ばめによって過大
な負荷を素子に与えることになる。
Further, in the technique disclosed in Japanese Patent Laid-Open No. 2-119255, the side of the frame tab and the side of the element are fixed by shrink fitting by utilizing the difference in linear expansion between the frame tab and the element. In order to fix, it is necessary to mount the element in the frame tab in a heating atmosphere, and it is necessary to support the element until it cools to room temperature. Furthermore, the shrink fit will apply an excessive load to the device.

【0005】本発明の目的はこれら従来技術における半
導体素子装着時の問題を解決でき、薄型化及び耐リフロ
ー性に優れたパッケージ構造を提供することにある。
An object of the present invention is to provide a package structure which can solve the problems when mounting a semiconductor element in these conventional techniques and which is thin and excellent in reflow resistance.

【0006】[0006]

【課題を解決するための手段】上記目的は、半導体素子
側面と枠タブ内側側面をはめ合わせる際、厚さ方向に対
してはめ合い面を斜めにして側面保持することにより達
成される。
The above object is achieved by holding the side surface of the semiconductor element side face and the inner side face of the frame tab in a slanting manner with respect to the thickness direction when the side face is fitted.

【0007】本発明の半導体装置は、半導体素子と、こ
の半導体素子を支持するタブと、リードフレームと、こ
のリードフレームと半導体素子を電気的に接続するワイ
ヤを備え、半導体素子とタブ及びリードの一部並びにワ
イヤを樹脂の封止体にてパッケージングした半導体装置
において、前記半導体素子側面を枠状タブ内側側面の斜
めの部分に形成する。
The semiconductor device of the present invention comprises a semiconductor element, a tab for supporting the semiconductor element, a lead frame, and a wire for electrically connecting the lead frame and the semiconductor element. In a semiconductor device in which a part and wires are packaged in a resin sealing body, the side surface of the semiconductor element is formed at an oblique portion of the inner side surface of the frame-shaped tab.

【0008】[0008]

【作用】本発明の半導体装置では、半導体素子側面を枠
状タブ内側側面の斜めの部分で支持するため、従来に比
べ素子−タブ間の装着が容易になり、かつ、装着安定性
が向上する。
In the semiconductor device of the present invention, since the side surface of the semiconductor element is supported by the oblique portion of the inner side surface of the frame-shaped tab, the mounting between the element and the tab becomes easier and the mounting stability is improved as compared with the conventional case. .

【0009】[0009]

【実施例】図1はこの発明の第1実施例による半導体素
子と枠タブの部分斜視図とその部分断面図である。
1 is a partial perspective view of a semiconductor element and a frame tab according to a first embodiment of the present invention and a partial sectional view thereof.

【0010】図1において、半導体素子1は対向する側
面をそれぞれテーパ状に切断し、内側側面を厚さ方向に
対して全体にテーパ状に加工した枠タブ2と互いのテー
パ面ではめ合わせ接着剤6を介して固定する。接着剤6
を枠タブ2の内側側面に塗布する際、はめ合い面外に漏
れ出さない程度に部分塗布し、吸着支持により半導体素
子1を枠タブ2の内側側面はめ合わせて圧着する。
In FIG. 1, the semiconductor element 1 is formed by cutting the opposite side surfaces into taper shapes, and the inner side surfaces of the frame tabs 2 which are entirely tapered in the thickness direction are fitted and adhered to each other at their taper surfaces. Fix through agent 6. Adhesive 6
Is applied to the inner side surface of the frame tab 2 so that it does not leak out of the fitting surface, and the semiconductor element 1 is press-fitted to the inner side surface of the frame tab 2 by suction support.

【0011】図4は半導体素子側面をテーパ状にする方
法を示した断面図で、シリコンウェハ8下面(集積回路
の無い側)を切断上面部として、ウェハ8を吸着支持で
きる吸着台10を用いて固定する。その際、ウェハ8上
面(集積回路側)を保護する保護体9を介して固定す
る。そして、先端をテーパ状とした刃でウェハ8を切断
することで半導体素子側面をテーパ状にする。さらに、
枠タブ2側面全体をテーパ状に加工するには、エッチン
グもしくは打ち抜きで行う。エッチングの場合にはタブ
の上面と下面のマスク領域の大きさを変えることで達成
できる。打ち抜きで行う場合には、図5に示すような打
ち抜き型11を用いて打ち抜き後、テーパ状にプレス
し、枠タブ側面をテーパ状にする。
FIG. 4 is a cross-sectional view showing a method of tapering the side surface of the semiconductor element. A suction table 10 capable of suction-supporting the wafer 8 is used with the lower surface of the silicon wafer 8 (the side having no integrated circuit) as the cutting upper surface. To fix. At that time, the wafer 8 is fixed via a protective body 9 that protects the upper surface (on the integrated circuit side). Then, the side surface of the semiconductor element is tapered by cutting the wafer 8 with a blade having a tapered tip. further,
To process the entire side surface of the frame tab 2 into a tapered shape, etching or punching is performed. In the case of etching, it can be achieved by changing the sizes of the mask regions on the upper surface and the lower surface of the tab. In the case of punching, a punching die 11 as shown in FIG. 5 is used for punching, followed by pressing into a taper shape so that the side surface of the frame tab is tapered.

【0012】図2は図1を用いた半導体装置の断面図で
ある。図2において、図1の構成で枠タブ2に固定され
た半導体素子1とリード3は金属ワイヤ5で電気的に接
続される。そしてトランスファーモールドにより封止樹
脂5で封止され、半導体素子等を外部環境から保護す
る。また、タブを枠状にすることによる剛性低下を防ぐ
ため、素子の厚さを越えない範囲でタブを厚くできる。
FIG. 2 is a sectional view of the semiconductor device shown in FIG. In FIG. 2, the semiconductor element 1 fixed to the frame tab 2 in the configuration of FIG. 1 and the lead 3 are electrically connected by the metal wire 5. Then, it is sealed with a sealing resin 5 by transfer molding to protect the semiconductor element and the like from the external environment. Further, in order to prevent the rigidity from being reduced by forming the tab into a frame shape, the tab can be thickened within a range not exceeding the thickness of the element.

【0013】図6は第1実施例に係る半導体素子と枠タ
ブのはめ合わせ部の断面図で、半導体素子1の側面を第
1実施例における枠タブ2の内側側面とはめ合わせる部
分だけテーパ状にして、互いのテーパ面ではめ合わせ接
着剤6を介して固定する。この場合の半導体素子1の側
面形状は、図4と同様の構成で、先端をテーパ状とした
刃で必要な厚みだけまず面取りを行い、その後、同じ位
置を従来の方法で切断することで達成できる。
FIG. 6 is a cross-sectional view of the fitting portion of the semiconductor element and the frame tab according to the first embodiment, in which only the portion where the side surface of the semiconductor element 1 is fitted to the inner side surface of the frame tab 2 in the first embodiment is tapered. Then, the taper surfaces are fixed to each other via a fitting adhesive 6. The side surface shape of the semiconductor element 1 in this case is the same as that of FIG. 4, and is achieved by first chamfering with a blade having a tapered tip to a required thickness, and then cutting the same position by a conventional method. it can.

【0014】図7も第1実施例に係る半導体素子と枠タ
ブのはめ合わせ部の側面断面図で、枠タブ2の内側側面
を厚さ方向の途中からテーパ状に打ち抜き、半導体素子
1の側面もその枠タブ2の内側側面とはめ合わせる部分
だけテーパ状にして、互いのテーパ面ではめ合わせ接着
剤6を介して固定する。
FIG. 7 is also a side cross-sectional view of the fitting portion of the semiconductor element and the frame tab according to the first embodiment. The inner side surface of the frame tab 2 is punched out in a taper shape from the middle in the thickness direction to form a side surface of the semiconductor element 1. Also, only the portion to be fitted to the inner side surface of the frame tab 2 is tapered, and the taper surfaces are fixed to each other via the fitting adhesive 6.

【0015】図8,図9は本発明における第2実施例の
半導体素子と枠タブはめ合わせ部の断面図である。図8
において、内側側面を厚さ方向に対して全体にテーパ状
とした枠タブ2と従来の方法で側面を鉛直方向に切断し
た半導体素子1を互いの側面で接着剤6を介して固定す
る。この際、内側側面がテーパ部分の枠タブ2内径の最
小値が半導体素子1外径寸法より小さくなるように設定
する。図9では、枠タブ2の内側側面を厚さ方向の途中
からテーパ状に打ち抜き、半導体素子1の下面をそのテ
ーパ面で保持し、互いの鉛直側面を接着剤6を介して固
定する。従って、この場合も枠タブ1内径の最小値が半
導体素子1外径寸法より小さくなるように設定する。実
施例における枠タブ内側側面及び半導体素子側面のテー
パ角度は、各実施例とも70〜80度とする。
FIGS. 8 and 9 are sectional views of the semiconductor element and the frame tab fitting portion of the second embodiment of the present invention. Figure 8
In, the frame tab 2 whose inner side surface is entirely tapered with respect to the thickness direction and the semiconductor element 1 whose side surface is vertically cut by the conventional method are fixed to each other with an adhesive 6 between them. At this time, the minimum value of the inner diameter of the frame tab 2 whose inner side surface is a tapered portion is set to be smaller than the outer diameter dimension of the semiconductor element 1. In FIG. 9, the inner side surface of the frame tab 2 is punched out in the middle in the thickness direction in a taper shape, the lower surface of the semiconductor element 1 is held by the taper surface, and the vertical side surfaces thereof are fixed with an adhesive 6. Therefore, also in this case, the minimum value of the inner diameter of the frame tab 1 is set to be smaller than the outer diameter dimension of the semiconductor element 1. The taper angles of the inner side surface of the frame tab and the side surface of the semiconductor element in the embodiments are 70 to 80 degrees in each embodiment.

【0016】[0016]

【発明の効果】本発明によれば、樹脂封止型半導体装置
において、半導体素子側面を枠状タブ内側側面の斜めの
面で保持するため、素子タブ間の装着が容易になり、か
つ装着安定性が向上し、従来技術における素子装着時の
問題が解決される。
According to the present invention, in the resin-sealed semiconductor device, the side surface of the semiconductor element is held by the oblique surface of the inner side surface of the frame-shaped tab, so that the element tabs can be easily mounted and the mounting stability can be improved. The property is improved, and the problem when mounting the element in the prior art is solved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例による半導体素子と枠タブ
の部分斜視図。
FIG. 1 is a partial perspective view of a semiconductor device and a frame tab according to a first embodiment of the present invention.

【図2】図1を用いた半導体装置の断面図。2 is a cross-sectional view of a semiconductor device using FIG.

【図3】従来技術おける半導体装置の断面図。FIG. 3 is a sectional view of a semiconductor device according to a conventional technique.

【図4】半導体素子側面をテーパ状にするための方法を
示した断面図。
FIG. 4 is a cross-sectional view showing a method for tapering the side surface of a semiconductor element.

【図5】タブ側面をテーパ状に加工するための打ち抜き
型の断面図。
FIG. 5 is a cross-sectional view of a punching die for processing the tab side surface into a tapered shape.

【図6】本発明の第1実施例に係る半導体素子と枠タブ
の断面図。
FIG. 6 is a cross-sectional view of the semiconductor device and the frame tab according to the first embodiment of the present invention.

【図7】本発明の第1実施例に係る半導体素子と枠タブ
の断面図。
FIG. 7 is a cross-sectional view of the semiconductor device and the frame tab according to the first embodiment of the present invention.

【図8】本発明の第2実施例による半導体素子と枠タブ
の断面図。
FIG. 8 is a sectional view of a semiconductor device and a frame tab according to a second embodiment of the present invention.

【図9】本発明の第2実施例に係る半導体素子と枠タブ
の断面図。
FIG. 9 is a sectional view of a semiconductor device and a frame tab according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体素子、2…枠タブ、3…リード、4…金属ワ
イヤ、5…封止樹脂、6…接着剤、7…吊リード、8…
シリコンウェハ、9…ウェハ保護体、10…吸着台、1
1…打ち抜き型。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Frame tab, 3 ... Lead, 4 ... Metal wire, 5 ... Sealing resin, 6 ... Adhesive agent, 7 ... Suspension lead, 8 ...
Silicon wafer, 9 ... Wafer protector, 10 ... Suction table, 1
1 ... Punching die.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 河野 竜治 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryuji Kono 502 Jinmachi-cho, Tsuchiura-shi, Ibaraki Pref.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体素子と、前記半導体素子を支持する
タブと、リードフレームと、前記半導体素子及び前記リ
ードフレームを電気的に接続する部材を備え、前記リー
ドフレームの一部及び前記半導体素子及び前記半導体素
子を支持するタブ及び接続部材を樹脂により封止して、
パッケージを形成する樹脂封止型半導体装置において、
前記半導体素子を支持するタブを枠状とし、また、枠タ
ブ内側側面の少なくとも一方向の対向する面に厚さ方向
に対して斜めの部分をもち、半導体素子の少なくとも一
方向の対向する側面に厚さ方向に対して斜めの部分を有
し、互いの斜めの部分ではめ合わせてあることを特徴と
する樹脂封止型半導体装置。
1. A semiconductor element, a tab for supporting the semiconductor element, a lead frame, a member for electrically connecting the semiconductor element and the lead frame, and a part of the lead frame and the semiconductor element, The tab and the connection member supporting the semiconductor element are sealed with resin,
In a resin-sealed semiconductor device that forms a package,
The tab supporting the semiconductor element is formed in a frame shape, and at least one direction of the frame tab inner side surface has a portion oblique to the thickness direction, and the side surface of the semiconductor element is opposed to at least one direction. A resin-encapsulated semiconductor device, characterized in that it has diagonal portions with respect to the thickness direction, and the diagonal portions are fitted together.
JP4272631A 1992-10-12 1992-10-12 Resin-sealed semiconductor device Pending JPH06125033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4272631A JPH06125033A (en) 1992-10-12 1992-10-12 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4272631A JPH06125033A (en) 1992-10-12 1992-10-12 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH06125033A true JPH06125033A (en) 1994-05-06

Family

ID=17516626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4272631A Pending JPH06125033A (en) 1992-10-12 1992-10-12 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH06125033A (en)

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