JPH0612628B2 - Memory circuit device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a memory circuit device using a flip-flop as a memory element.

(Prior Art) Conventionally, a circuit for setting the flip-flop in the AND condition between the two signals (but one signal that is common) the flip-flop F ₁ as if there are multiple shown in Figure 1
The same number of AND circuits A _{1 to} A _n are provided in the preceding stage of the to F _n , and the outputs of the AND circuits A _{1 to} A _n are applied to the set terminal S of each flip-flop.

Therefore, when the common terminal X of the AND circuits A _{1 to} A _n is at the high level and any one of the terminals 1 to n becomes the high level, an output is output from the AND circuit and the flip-flop is set.

By the way, since the circuit requires the same number of AND circuits as the flip-flops, the device of this type is large and expensive, but as an improvement, for example, a JK flip-flop is used, and two signals are One is added to the J terminal, and the other one is added to the clock pulse terminal CK.
It is conceivable to store them under the AND condition of two signals.

(Problems to be solved by the invention) However, with this method, since the edge trigger type operates only at the rising edge of the signal to which the CK terminal is applied, as shown in FIG. The AND condition is satisfied when the CK terminal goes high, but when the J terminal goes high while the CK terminal is high as shown in FIG. The condition is not met.

The present invention has been made in view of the above points, and provides a memory circuit device that can be surely stored under an AND condition by omitting an AND circuit and using a memory element such as a JK flip-flop. With the goal.

(Means for Solving the Problems) The present invention is a pulse signal in which a signal applied to an input terminal (for example, J terminal) is applied to another terminal (for example, clock pulse CK terminal) like a JK flip-flop. A plurality of so-called edge-triggered storage elements for storing at the rising or falling edges of the signal, and a converter for converting the input pulse signal into a pulse having a sufficiently small cycle and pulse width. The converter output pulse should be smaller than both the input signal of the memory element and the converter input signal in both its cycle and width, and this pulse should be commonly applied to another terminal (CK: edge trigger terminal) of all the memory elements. It is configured in.

(Operation) With such a configuration, the pulse signal applied to the converter is converted (pulse division) into a plurality of pulses having a sufficiently small cycle and width during the period.

Therefore, if the AND condition is satisfied between the input signal of the storage element and the input signal of the converter, the rising (or falling) portion of the output pulse of the converter must be present during the period when the input signal of the storage element is high level. Since it arrives, the storage element input signal can be stored under the AND condition of two signals without using a separate AND circuit.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS.

In FIG. 5, F _{1 to} F _n are JK flip-flops similar to those in FIG. 1, and O is a converter (oscillation circuit) controlled by the input X.

The present invention repeats the input signal X into a pulse whose width and period are sufficiently smaller than any of the high level periods of the input signal to J and X, and which are each JK.
Clock pulse input terminal C of the flip-flops F _{1 to} F _n
It is commonly supplied to K.

In other words, in other words, the signal X is divided into a plurality of short pulses.

With this configuration, the relationship of the J signal X signal shown in FIG. 4 which cannot be set conventionally, that is, the signal J (that is, one or more of J _{1 to} J _n ) is maintained during the high level period of the signal X. Even when it becomes high level, the third pulse of the pulse applied to the CK terminal of each of the J-K flip-flops F _{1 to} F _n rises during the high level period of J, so that Q becomes high level and is set accordingly. It

In this way, the common input signal X is repeated for the duration of X, converted into a pulse whose width and period are sufficiently smaller than both the high level period of the input signal to J and X (pulse division), and this is converted to CK. Since any of the short pulses rises during the period in which J is at the high level, it becomes possible to reliably set it.

In this embodiment, the K, R, and S terminals of the JK flip-flop are not connected at all, but this shows that there is no input, and in order to simplify the explanation of the circuit operation. It is omitted.

In practice, the non-input terminals are generally kept at a high level or a low level at all times. In the JK flip-flop of this embodiment, the K, R and S terminals are at a low level (usually ground). Potential).

In the above description, the JK flip-flop is set. However, when the reset operation is performed, the K terminal may be used instead of J. At this time, the J terminal is set to the low level. Of course.

(Effect of the Invention) As described above, according to the present invention, a plurality of edge-triggered storage elements and one converter are used, and for each storage element, one of the two pulse signals is used as the first storage element. In addition to one input terminal, the other is applied to the converter as a common signal, and the converter output signal obtained by dividing the input pulse into a pulse signal having a small cycle and width is applied to each edge trigger terminal of the plurality of storage elements. Therefore, it is possible to surely store signals in two AND conditions without using the same number of AND circuits as in the conventional flip-flop, and to have a simple circuit configuration and to reduce the size and weight. Produce an effect.

Further, the effect of miniaturization by omitting the AND circuit becomes greater as the number of storage elements increases.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a conventional example of a memory circuit device, FIG.
FIG. 3 is a time chart of a memory circuit device using a JK flip-flop, FIG. 4 is a time chart showing the operation of the memory circuit device of the present invention, and FIG. 5 is a connection diagram showing an embodiment of the present invention. Is. F _{1 to} F _n 4 ... JK flip-flop O ... Converter

Claims (1)

[Claims] 1. A plurality of storage elements for storing a pulse signal applied to a first input terminal at either a rising edge or a falling edge of a pulse signal applied to a second input terminal, and a pulse to the input terminal. When a signal is applied, the pulse signal is repeated for the duration of the pulse signal and is converted into a pulse signal whose width and period are smaller than this pulse signal and outputs the pulse signal to an output terminal. For each storage element of the storage element, one of the two pulse signals is applied to the first input terminal of the storage element, and the other of the two pulse signals is used as a common signal for conversion. In addition to the input terminal of the device, the output pulse signal of the conversion device is converted so that the width and the period of the output pulse signal are smaller than either of the two pulse signals. It said scan signal a plurality of memory circuit being characterized in that as applied to the common to a second input terminal of the storage element.