JPH06140416A - Heterojunction bipolar transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] An InP-based hetero that can improve the maximum oscillation frequency fmax by reducing the base-collector capacitance and flatten the transistor structure by separating elements by ion implantation and taking the collector electrode out of the substrate surface. A junction bipolar transistor is provided. [Structure] First collector layers 3a, n made of n-type InP
Type _{(In 0.53 Ga 0.47 As) 0} .5 (In0.52Al 0.48 As) the second collector layer 3b, p-type consisting of _{0.5 (In 0.53 Ga 0.47 As)} 0.5
A base layer 4 made of (In0.52Al _0.48 As) _0.5 and an emitter made of an n-type InP layer 5 are formed, and an insulating film is formed by selectively removing the second collector layer by etching. The n-type InGaAs layer is regrown using the mask to form a contact layer for the collector electrode.

Description

Detailed Description of the Invention

[0001]

This invention relates to heterojunction bipolar transistors.

[0002]

2. Description of the Related Art Heterojunction bipolar transistor (HB
T) is attracting attention as a next-generation ultra-high speed device that has both high current drive capability and excellent high frequency characteristics. AlGaAs / GaAs HBTs have already been reported to have a cutoff frequency ft exceeding 100 GHz as the highest speed of a single element.
On the other hand, its high speed is being demonstrated in applications to digital circuits such as 1/4 frequency dividers and MUX / DMUX. In addition, in order to apply HBT to micro band and millimeter wave band analog IC and to reduce delay time of digital circuit, maximum oscillation frequency fmax
Is being considered. The on-voltage of the AlGaAs / GaAs HBT base-emitter diode is approximately 0.8V in the case of Si bipolar, but is 1.35 to 1.50V, which is approximately 70 to 80%, which is a large power consumption increase. It has a problem of causing A first heterojunction bipolar transistor has been proposed in order to realize a first problem, that is, a heterojunction bipolar transistor having a high maximum oscillation frequency fmax, and an example will be described below with reference to the drawings.

FIG. 4 is a cross-sectional view of an element of a first conventional heterojunction bipolar transistor. On a semi-insulating semi-insulating GaAs substrate 21, a first contact layer 22 made of high-concentration n-type GaAs, a collector layer 23 made of n-type GaAs, a base layer 24 made of high-concentration p-type GaAs, and n-type AlGaAs. Has an epitaxial structure in which a first contact layer 26a made of high-concentration n-type GaAs and a second contact layer 26b made of high-concentration n-type InGaAs are sequentially formed. Using the emitter electrode 7 made of WSi as a mask, the first and second contact layers 26a and 26b corresponding to the external base region and the emitter layer 25 are removed by etching, and the emitter electrode 7 is used as a mask to inject protons to the outside. The donor concentration of the collector layer 23a below the base region is reduced so that the collector layer 23a can operate during transistor operation.
a is completely depleted. Therefore, since the base-collector capacitance C _BC is reduced, a heterojunction bipolar transistor having a high maximum oscillation frequency fmax can be realized.

FIG. 5 is a device sectional view and energy band diagram of a second conventional heterojunction bipolar transistor. On the semi-insulating InP substrate 1, a first contact layer 32 made of high-concentration n-type InGaAs, a collector layer 33 made of n-type InGaAs, a base layer 34 made of high-concentration p-type InGaAs, an n-type
InP emitter layer 35, and high-concentration n-type InGaAs
It has an epitaxial structure in which a second contact layer 36 is sequentially formed. An emitter mesa, a base mesa, and a collector mesa are sequentially formed by wet etching. After forming the emitter electrode, the base electrode, and the collector electrode, planarization is performed using polyimide. The base and collector are made of InGaAs, and its mobility is about 1.5 times that of GaAs, and the energy difference between the Γ and L valleys is large, so a velocity overshoot over a long distance easily occurs in the collector depletion layer. As a result, a cutoff frequency ft = 165 GHz has been obtained, and excellent high frequency characteristics have been demonstrated. InGaAs has a band gap of 0.76
Since it is smaller than eV and GaAs or Si, the turn-on voltage due to the bandgap of the material of the base layer is low, which is advantageous for low power consumption. In addition, the thermal conductivity of the InP substrate is improved by 50% compared to GaAs (I-I-I-Electron Device Device Letters, IEEE Electron Device Lett. Vol.
10, pp. 267-269, 1989).

[0005]

However, in the HBT of the first conventional example, since the base resistance R _B increases due to damage due to the proton injection through the external base layer, the reduction amount of the base-collector capacitance C _BC and the base resistance R _B are increased. _{B It} is necessary to optimize the amount of increase. GaAs has a relative permittivity of about 1
Since it is as large as 3.0, it is necessary to increase the thickness of the collector layer in order to effectively reduce the base-collector capacitance by proton injection.

In the second conventional example, the collector layer and the collector contact layer are made of InGa having a small energy band gap.
Since As is used, it is difficult to separate elements by ion implantation of protons and oxygen. A step occurs due to mesa etching for element isolation, which is a major problem in integrating HBTs.

In view of the above problems, the present invention improves the maximum oscillation frequency fmax by reducing the base-collector capacitance C _BC without increasing the base resistance, lowering the power consumption by low on-voltage and ion implantation. The present invention provides a heterojunction bipolar transistor capable of high integration by a planarization process using element isolation by.

[0008]

In order to solve the above problems, the heterojunction bipolar transistor of the present invention is
A first collector layer made of at least n-type InP on the P substrate, and an n-type In _x (lattice-matched with the InP substrate and having a composition ratio that hardly causes a conduction band offset (ΔEc) with InP ( Ga _y Al _1-y ) _1-x As second collector layer, p-type In _x (Ga _y Al _1-y ) lattice-matched with InP substrate
_1-x base layer made of As, the emitter layer made of InP with n-type impurities are introduced InP substrate and lattice-matched is constituted by an epitaxial layer structure which are sequentially formed, n-type in the external base region an In _x ( The second collector layer made of Ga _y Al _1-y ) _{1 -x} As has a structure in which an insulating film is formed at a portion selectively removed by etching.

A second type of n-type In _x (Ga _y Al _1-y ) _1-x As
The collector electrode contact layer is formed by regrowth of the n-type InP or n-type In _x Ga _1-x As layer using the insulating film as a mask at the location where the collector layer of FIG. It is a thing.

[0010]

The operation of the above-described heterojunction bipolar transistor of the present invention is as follows. (1) Figure 6 shows In _0.53 Ga _0.47 As, I lattice-matched to InP substrate.
n _0.52 Al _0.48 As, InP and (In _0.53 Ga _0.47 As) _x (In0.52Al
_0.48 As) _1-x (0 ≦ x ≦ 1) flat band diagram is shown, which does not generate conduction band offset (ΔEc) with InP (In _0.53 Ga _0.47 As) _x (In
The composition ratio x of _0.52 Al _0.48 As) _1- x is 0.5. The second collector layer is n-type (In _0.53 Ga _0.47 As) _0.5 (In _0.52 Al _0.48 A
s) When formed from _0.5, no barrier occurs in the conduction band, even though the collector is made up of two material systems. n-type (In _0.53 Ga _0.47 As) _0.5 (In _0.52 Al
The second collector layer made of _0.48 As) _0.5 can be selectively etched away with respect to the first collector layer.
An insulating film corresponding to the film thickness of the removed second collector layer can be uniformly formed on the collector layer in the plane. (2) The emitter is n-type InP and the base is p-type (In _0.53 Ga
_0.47 As) _0.5 (In0.52Al _0.48 As) _{0.5 When} composed of 0.25 eV valence band offset (△
Ev) can sufficiently prevent injection of holes from the base to the emitter. Also, the built-in potential of the base and emitter is about 1.0 eV, which is higher than that of the GaAs / AlGaAs system.
A low on-voltage can be achieved at 60%. (3) After selectively removing the second collector layer, n-type In
High concentration n-type In _x Ga _1-x As on the first collector layer made of P
Layer or n-type InP layer regrowth layer for collector electrode formation and flattening process using element isolation by ion implantation of collector layer with large energy band gap enables high integration Becomes

[0011]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a main cross-sectional view of one embodiment of the first heterojunction bipolar transistor of the present invention. The structure of this embodiment is different from the structure of the first conventional example shown in FIG. 4 in that it is an InP-based material system and the collector layer is an n-type InP layer.
N-type (In _0.53 Ga _0.47 As) _0.5 (In0.52Al _{0.4 8} A that does not generate conduction band offset (△ Ec) with InP
s) It is composed of _0.5 layers and the base is p-type (In _0.53 Ga _0.47
As) _0.5 (In0.52Al _{0.4 8} As) _0.5 layer, emitter is n-type InP
The point is that it is composed of layers. In addition, an insulating film is provided immediately below the external base region, and the collector electrode contact layer is composed of a regrown film.

Next, referring to the manufacturing process diagram of the element shown in FIG.
Of the heterojunction bipolar transistor according to the embodiment
The method will be described. Molecular epitaxy on semi-insulating InP substrate 1
2x10 by Kissie¹⁶/CM³Thickness of 20 including n-type impurities
First first collector layers 3a, 2x made of 0 nm n-type InP
Ten¹⁶/CM³300nm thick n-type (In
_0.53Ga_0.47As)_0.5(In0.52Al_0.48As) second
Collector layer 3b, 4x10¹⁹/CM³Thickness containing p-type impurities
100 nm p-type (In_0.53Ga_0.47As)_0.5(In0.52Al _0.48A
s) base layer 4, 5x10¹⁷/CM³Containing n-type impurities
Emitter layer 5 made of n-type InP having a thickness of 30 nm, 4x10
¹⁹/CM³N-type In with a thickness of 100 nm containing n-type impurities_0.53
Ga_0.47The contact layer 6 made of As is sequentially stacked to form a sputter
Deposition and reactive ion etching (RIE)
By patterning the emitter electrode 7 made of WSi
Formed, and using this as a mask, the base layer serves as a stopper
Contact layer 6 and emitter in the external base region
Form emitter mesa by selective etching away of layer 5
To achieve. SiO on the entire surface₂After forming the film 8, the photoresist is
Suku and SiO₂The film 8, the base layer 4, and the second collector layer
It is selectively etched away to form a base mesa.
(Fig. 2A) Thickness on the second collector layer consisting of n-type InP layer
300 nm SiO₂Forming an insulating film 9 made of
The insulating film 8 at the location where the electrode electrode is formed, and the insulating film 9 is removed.
N-type In by MOCVD using as a mask_0.53Ga_{0. 47}From As
Then, the collector electrode contact layer 2 is formed. (Fig. 2
B) Element isolation region 10 is provided by proton ion implantation.
The emitter extraction electrode 11, the collector electrode 12 and the base
Of the heterojunction bipolar transistor
The manufacturing process of the transistor is completed.

FIG. 3 is a main sectional view of a second embodiment of the heterojunction bipolar transistor of the present invention. The structure of this embodiment is different from the structure of the first embodiment shown in FIG. 1 in that the first collector layer 3a whose collector layer is an n-type InP layer and the n-type (In _0.53 Ga _0.47 As) _0.5 ( In0.52Al _0.48 A
s) It has a three-layer structure composed of a second collector layer 3b composed of _0.5 layers and a first collector layer 3c composed of an n-type InP layer. A third method utilizing selective etching between the base layer 4 made of p-type (In _0.53 Ga _0.47 As) _0.5 (In0.52Al _0.48 As) _0.5 layer and the third collector layer made of n-type InP when forming the base mesa. Since the area of the collector region can be reduced to the same extent as the upper emitter region by side etching the collector layer of, the base-collector capacitance can be further reduced.

[0015]

As described above, according to the present invention, the base-collector capacitance can be reduced and the maximum oscillation frequency fmax can be improved by providing an insulating film having a relative dielectric constant directly below the external base region without increasing the base resistance. be able to.
InP-based heterojunction bipolar with a collector electrode contact layer composed of re-grown InGaAs layer formed on the surface of the substrate and element isolation by proton ion implantation into the collector composed of InP, which is a wider gap material than InGaAs The transistor structure can be flattened, and high integration can be facilitated. In addition, the emitter / base diode has a lower on-voltage than the GaAs / AlGaAs HBTs, which can provide low power consumption.

[Brief description of drawings]

FIG. 1 is a main cross-sectional view of a heterojunction bipolar transistor that is a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a main sectional view of a heterojunction bipolar transistor according to a second embodiment.

FIG. 4 is a main cross-sectional view of a first conventional heterojunction bipolar transistor.

5A is a main cross-sectional view of a second conventional heterojunction bipolar transistor, and FIG. 5B is an energy band diagram.

FIG. 6 In _0.53 Ga _0.47 As, In0.5 lattice-matched to InP substrate
2Al _0.48 As, InP and _{(In 0.53 Ga 0. 47 As)} x (In0.52Al 0.48 A
s) Diagram showing _1-x (0 ≤ x ≤ 1) flat band diagram

[Explanation of symbols]

1 Semi-insulating InP substrate 2 Contact layer for regrown collector electrode (high concentration n-type In
GaAs) 3a First collector layer (n-type InP) 3b Second collector layer (n-type (In _0.53 Ga _0.47 As) _0.5
(In0.52Al _0.48 As) _0.5 ) 4 Base layer (high concentration p-type (In _0.53 Ga _0.47 As) _0.5 (In
0.52Al _0.48 As) _0.5 ) 5 Emitter layer (n-type InP) 6 Contact layer (high concentration n-type InGaAs) 7 Emitter electrode (WSi) 8 Insulating film (SiO ₂ ) 9 Insulating film (SiO ₂ ) 10 Isolation region (Proton injection region) 11 Emitter extraction electrode 12 Collector electrode 11 Base electrode

Claims (7)

[Claims] 1. A first collector layer made of at least n-type InP on an InP substrate, and n-type In _x (Ga _y Al) lattice-matched with the InP substrate.
_1-y ) A second collector layer made of _1-x As, a base layer lattice-matched with the InP substrate doped with p-type impurities, and an emitter layer lattice-matched with the InP substrate doped with n-type impurities are sequentially formed. Heterojunction bipolar transistor, characterized in that the heterojunction bipolar transistor is constituted by a controlled epitaxial layer structure. 2. An n-type In forming a second collector layer
_{x (Ga y Al 1-y} ) 1-x As heterojunction bipolar according to claim 1, characterized in that it has a conduction band offset (△ Ec) a little raises the composition ratio of InP Transistor. 3. A p-type In _x having a base layer lattice-matched with an InP substrate.
The heterojunction bipolar transistor according to claim 1, wherein the heterojunction bipolar transistor is composed of (Ga _y Al _1-y ) _1-x As. 4. An n-type In _x (Ga _y Al) outside the internal base region
2. The heterojunction bipolar transistor according to claim 1, wherein the second collector layer made of _1-y ) _1-x As is selectively removed by etching, and an insulating film is formed at a portion removed by the etching. 5. An n-type In _x (Ga _y Al) outside the internal base region
_1-y ) The second collector layer made of _1-x As is selectively removed by etching, and an n-type InP layer or an n-type In _x Ga _1-x As layer is formed by using the insulating film as a mask at the removed etching portion. The heterojunction bipolar transistor according to claim 1, wherein the heterojunction bipolar transistor is formed. 6. A first collector layer made of at least n-type InP on an InP substrate, and n-type In _x (Ga _y Al) lattice-matched with the InP substrate.
_1-y ) 2nd collector layer made of _1-x As, 3rd collector layer made of n-type InP, p-type In _x (Ga _y
The patterned base is composed of an epitaxial layer structure in which a base layer made of Al _1-y ) _1-x As and an emitter layer made of InP lattice-matched with an InP substrate having an n-type impurity introduced are sequentially formed. A heterojunction bipolar transistor characterized in that an insulating film is formed at a portion where the second collector is removed by etching using the layer as a mask. 7. The n-type InP layer or the n-type In _x Ga _1-x As after selectively removing the first collector layer or the first and second collector layers by etching using the insulating film as a mask. The heterojunction bipolar transistor according to claim 6, wherein the layer is regrown to form a collector electrode contact layer.