JPH06140421A - Manufacture of thin film transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] A photoresist film can be formed at an accurate position with respect to a gate electrode, and offset gate regions are formed to have a uniform size on the left and right sides. [Structure] The first gate insulating film 1 is formed on the polysilicon layer 11.
2, the second gate insulating formation film 20, and the gate electrode formation film 21 are deposited, and the gate electrode formation film 21 of the portion corresponding to the channel region 11a of the polysilicon layer 11 is deposited.
A photoresist film 22 is patterned on top. Then, dry etching is performed using this photoresist film 22 as a mask to leave the first gate insulating film 12 and leave the second gate insulating forming film 20 as the second gate insulating film 13 having the same shape as the photoresist film 22. And the gate electrode forming film 21 is formed on the gate electrode 14 having a shape side-etched to be narrower than the second gate insulating film 13. After that, the photoresist film 22 is removed and ions are implanted using the gate electrode 14 and the second gate insulating film 13 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor having an offset structure.

[0002]

2. Description of the Related Art Among thin film transistors, there is an element called an offset gate structure as an element for reducing leakage current. In such a thin film transistor, the width of the gate electrode is made smaller than the width of the channel region of the semiconductor layer made of polysilicon or the like, so that the channel regions on both sides of the gate electrode serve as offset gate regions. This thin film transistor is conventionally manufactured as shown in FIG. That is,
First, a polysilicon layer 2 is patterned on the upper surface of an insulating substrate 1 made of ceramic, glass, or the like, and the polysilicon layer 2 is covered with a gate insulating film 3. Next, the gate insulating film 3 in the portion corresponding to the channel region 2a of the polysilicon layer 2
A gate electrode 4 narrower than the channel region 2a is patterned on the upper surface of the gate electrode 4. Next, the gate electrode 4 is covered with a photoresist film 5, and this photoresist film 5 is formed in a shape corresponding to the channel region 2a. After that, by performing ion implantation using the photoresist film 5 as a mask,
Source / drain regions 2b are formed in the polysilicon layer 2 on both sides of the photoresist film 5. After that, the photoresist film 5 is removed and activated to diffuse the ions. As a result, a thin film transistor in which the offset gate regions 2c are formed in the channel regions 2a on both sides of the gate electrode 4 is obtained.

[0003]

However, in the conventional method for manufacturing such a thin film transistor, since the gate electrode forming step and the photoresist film forming step are separate, the photoresist film 5 is formed on the gate electrode 4. It is difficult to perform accurate alignment, and if the photoresist film 5 is displaced with respect to the gate electrode 4, there is a problem that the length L of the offset gate region 2c is different between left and right. An object of the present invention is to provide a method of manufacturing a thin film transistor capable of forming an etching resist film such as a photoresist at an accurate position with respect to a gate electrode and forming offset gate regions in a laterally uniform size. is there.

[0004]

According to the present invention, a first gate insulating film, a second gate insulating forming film, and a gate electrode forming film made of a semiconductor layer are deposited on a semiconductor layer, and a channel of the semiconductor layer is formed. An etching resist film is formed on the portion of the gate electrode forming film corresponding to the region, and dry etching is performed using this etching resist film as a mask, leaving the first gate insulating film and leaving the second gate insulating forming film. Is formed on the second gate insulating film having a shape corresponding to the etching resist film, and the gate electrode forming film is formed on the gate electrode having a shape side-etched narrower than the second gate insulating film. The etching resist film is removed, and ion implantation is performed using the gate electrode and the second gate insulating film as a mask.

[0005]

According to the present invention, the dry etching is performed by using the etching resist film as a mask, so that the second
Since the gate insulating film and the gate electrode can be continuously formed at once, an etching resist film such as a photoresist can be formed at an accurate position with respect to the gate electrode,
Further, when the second gate insulating film is formed into a shape corresponding to the etching resist film by dry etching, the gate electrode is side-etched uniformly, so that the gate electrode has a width narrower than that of the second gate insulating film. By performing ion implantation using the gate electrode and the second gate insulating film as a mask, the side-etched portion of the gate electrode can be directly used as an offset gate region, so that the offset gate region is evenly distributed on the left and right sides. It can be formed in a size.

[0006]

First, FIG. 4 shows the structure of a thin film transistor according to an embodiment of the present invention. In this thin film transistor, a polysilicon layer (semiconductor layer) 11 is provided on an upper surface of an insulating substrate 10 made of ceramic or glass, and a first gate insulating film 12 made of silicon oxide is provided so as to cover the polysilicon layer 11. A second gate insulating film 13 made of silicon nitride is provided on the upper surface of the first gate insulating film 12 in a portion of the polysilicon layer 11 corresponding to the channel region 11a, and the central portion of the upper surface of the second gate insulating film 13 (on both sides The gate electrode 1 made of polysilicon or the like is provided in a portion other than the portion that becomes the offset gate region 11c).
4 are provided, and the source / drain regions 11 are formed on both sides of the offset gate region 11c of the polysilicon layer 11.
b is formed, and the interlayer insulating film 15, the contact hole 16, and the source / drain electrode 17 are further provided.

Next, a case of manufacturing a thin film transistor having such a structure will be described with reference to FIGS. First, as shown in FIG. 1, a polysilicon layer 11 is patterned on the upper surface of an insulating substrate 10 made of ceramic, glass or the like. Next, a first gate insulating film 12 made of silicon oxide, a second gate insulating forming film 20 made of silicon nitride, and an amorphous silicon film (gate electrode forming film) 21 containing phosphorus at a high concentration are formed on the entire surface. Stack. Next, a predetermined portion of the upper surface of the amorphous silicon film 21 (that is, the channel region 11a of the polysilicon layer 11).
A photoresist film (etching resist film) 22 is formed in a pattern on the portion corresponding to.

Next, as shown in FIG. 2, the amorphous silicon film 21 and the second gate insulating formation film 20 are continuously dry-etched using the photoresist film 22 as a mask. Dry etching at this time, for example, the etching gas is a mixed gas of CF ₄ and 5% O ₂ , the pressure is 0.8 Torr,
The condition is that the RF power density is 0.37 W / cm ² and the electrode interval is 55 mm. When dry etching is performed under these conditions, after the amorphous silicon film 21 is etched, the amorphous silicon film 21 is side-etched when the second gate insulating formation film 20 is etched. As a result, the portion of the first gate insulating film 1 corresponding to the photoresist film 22 (that is, the portion corresponding to the channel region 11a) is formed.
The second gate insulating formation film 20 remains in the same shape as the photoresist film 22 on the upper surface of 2, and the remaining second gate insulating formation film 20 forms the second gate insulating film 13. Further, the amorphous silicon film 21 has a shape narrower than that of the second gate insulating film 13 in the central portion of the second gate insulating film 13 (that is, the portions corresponding to the channel regions 11a except the portions to be the offset gate regions 11c on both sides). Thus, the amorphous silicon film 21 remains, and the remaining amorphous silicon film 21 forms the gate electrode 14. Moreover, in such a dry etching, the etching selection ratio of the second gate insulating film 20 of silicon nitride to the first gate insulating film 12 of silicon oxide is as large as 30 or more. Since the insulating film 12 serves as an etching stopper, the polysilicon layer 11 is not damaged and the second gate insulating forming film 20 can be easily etched and removed.

Next, as shown in FIG. 3, after removing the photoresist film 22, ion implantation is performed using the gate electrode 14 and the second gate insulating film 13 as a mask. This ion implantation uses phosphorus ions as impurities and
Implant with an acceleration energy of about 20 KeV. Under this condition, if the thickness of the first gate insulating film 12 is about 20 nm and the thickness of the second gate insulating film 13 is about 160 nm,
Although phosphorus ions can pass through the first gate insulating film 12, they cannot pass through the second gate insulating film 13. As a result, the source / drain regions 11b are formed in the polysilicon layer 11 on both sides of the second gate insulating film 13, and the channel regions 11a on both sides of the gate electrode 14 become offset gate regions 11c. Then, an excimer laser is irradiated to activate the impurities implanted in the source / drain regions 11b. At this time, since the gate electrode 14 is made of the amorphous silicon film 21 containing phosphorus at a high concentration, the amorphous silicon film 2 is polycrystallized by the irradiation of the excimer laser and becomes the gate electrode 14 made of low resistance polysilicon. .

Next, as shown in FIG. 4, an interlayer insulating film 15 made of silicon nitride or the like is formed on the entire surface. next,
The interlayer insulating film 15 and the first gate insulating film 12 are etched to form a contact hole 16 in a portion corresponding to the source / drain region 11b. Next, a source / drain electrode 17 made of aluminum and connected to the source / drain region 11b through the contact hole 16 is formed on the upper surface of the interlayer insulating film 15. Thus, a thin film transistor having an offset gate structure is manufactured.

In the thin film transistor thus manufactured, the gate electrode 14 and the second gate insulating film 13 can be continuously formed at one time by performing dry etching using the photoresist film 22 as a mask. , Photoresist film 22 for gate electrode 14
Of the second gate insulating film 13 can be formed at an accurate position.
Since it is not necessary to pattern or remove the photoresist film as a dedicated mask for forming
The number of manufacturing steps can be reduced accordingly. Further, when the second gate insulating film 13 is formed in a shape corresponding to the photoresist film 22 by dry etching, the gate electrode 14 is side-etched narrower and more uniformly than the second gate insulating film 13, so that the channel is formed. Area 1
The gate electrode 14 can be formed in a shape narrower than 1a, and the side-etched portion of the gate electrode 14 can be directly used as the offset gate region 11c. Therefore, the length L of the offset gate region 11c
It is possible to obtain a thin film transistor having an even size on the left and right sides.

In the above embodiments, the case where the present invention is applied to the TFT (thin film transistor) using the semiconductor thin film has been described, but the present invention is not limited to this, and the present invention is applied to the thin film transistor star using the single crystal semiconductor substrate. You can also Further, not only the coplanar type but also the stagger type can be applied.

[0013]

As described above, according to the present invention, the second gate insulating film and the gate electrode can be continuously formed at once by performing dry etching using the etching resist film as a mask. Therefore, an etching resist film such as a photoresist can be formed at an accurate position with respect to the gate electrode, and when the second gate insulating film is formed into a shape corresponding to the etching resist film by dry etching, the gate electrode is evenly formed. Side etching, the gate electrode can be formed in a shape narrower than the second gate insulating film, and the etching resist film is removed to perform ion implantation using the gate electrode and the second gate insulating film as a mask. By doing so, the side etching part of the gate electrode is directly used as the offset gate region. Rukoto can, therefore it is possible to form the offset gate region in the lateral equal size.

[Brief description of drawings]

FIG. 1 is a view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention, in which a polysilicon layer is formed on an upper surface of an insulating substrate, and a first gate insulating film, a second gate insulating forming film, and FIG. 3 is a cross-sectional view of a state in which a gate electrode forming film is deposited and a photoresist film is patterned on the gate electrode forming film.

FIG. 2 is a plan view showing a method of manufacturing the same thin film transistor, wherein the gate electrode forming film and the second gate insulating forming film are dry-etched using the photoresist film as a mask, and the second gate insulating film and the gate electrode are formed on the first gate insulating film. FIG.

FIG. 3 is a cross-sectional view of a state in which the photoresist film is removed and ions are implanted using the gate electrode and the second gate insulating film as a mask in manufacturing the same thin film transistor.

FIG. 4 is a cross-sectional view showing a state in which an interlayer insulating film, contact holes, and source / drain electrodes are formed in manufacturing the same thin film transistor.

FIG. 5 is a cross-sectional view showing a state in which a gate electrode is patterned on a gate insulating film and ions are implanted using a patterned photoresist as a mask to cover the gate electrode in the manufacturing of a conventional thin film transistor.

[Explanation of symbols]

 10 Insulating Substrate 11 Polysilicon Layer (Semiconductor Layer) 11a Channel Region 11b Source / Drain Region 11c Offset Gate Region 12 First Gate Insulating Film 13 Second Gate Insulating Film 14 Gate Electrode 20 Second Gate Insulation Forming Film 21 Gate Electrode Formation Film 22 Photoresist film

Claims (1)

[Claims] 1. A first gate insulating film, a second gate insulating forming film, and a gate electrode forming film made of a semiconductor layer are deposited on the semiconductor layer, and a portion of the semiconductor layer corresponding to a channel region is formed. An etching resist film is formed on the gate electrode forming film, and dry etching is performed using the etching resist film as a mask to leave the first gate insulating film and to remove the second gate insulating forming film from the etching resist. The gate electrode forming film is formed on the second gate insulating film having a shape corresponding to the film, and the gate electrode forming film is formed on the gate electrode having a shape side-etched to be narrower than the second gate insulating film. The etching resist film is removed, and ion implantation is performed using the gate electrode and the second gate insulating film as a mask. Method for manufacturing transistor.