JPH06141013A - Method and circuit for switching transmission line without interruption - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] When the transmission line has a redundant configuration, it switches from the active to the standby without interruption. [Structure] A memory 1-1 for indicating a frame phase of N multiplexed low-speed signals by a pointer and storing the low-speed signals, and a write control circuit 2-for instructing a write address.
1 and a read control circuit 3-1 for designating a read address,
An active frame phase conversion circuit 31 including a phase comparator 4-1 for comparing both addresses to determine the necessity of stuffing, a spare frame phase conversion circuit 32 having the same configuration, and an input side from the active to the spare frame phase conversion circuit. It comprises a means 17-1 for notifying the phase of a frame, a stuffing execution decision circuit 19 for comparing the frame phases to decide stuffing execution, and a selector 10 for selecting one from both frame phase conversion circuit outputs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit for time-division-multiplexing a plurality of signals having a frame structure and transmitting them in a redundant configuration of a transmission line from an active to a standby without interruption.

[0002]

2. Description of the Related Art In a conventional transmission apparatus, in order to absorb delay fluctuations that occur in the transmission line, P210 to 2 of Research and Practical Report Vol.
Provide the frame aligner described in 14. The frame aligner includes an elastic store memory and a control circuit for the elastic store memory. The frame aligner absorbs a delay variation generated in a transmission path by writing a received frame in the elastic store memory and then reading the received frame. Also, by the above operation, the frame phases of a plurality of received frames transmitted via different routes can be matched with the unique frame phase of the device, so that processing such as cross-connect for each received frame can be performed. It is possible to improve convenience when performing.

Since the transmission device and the transmission line normally have a redundant configuration, the above frame aligners are provided on both the transmission line interface on the receiving side and the transmission side on the receiving side. As described above, the frame aligner can match the frame phase of the received frame with the unique frame phase of the device, so that the frame phase of the received frame transmitted via the working transmission path and the backup transmission path are passed. It is possible to forcefully match the frame phases of the received frames transmitted in this way. Therefore, when switching from the active mode to the backup mode, there will be no momentary interruption due to the frame phase shift.

[0004]

Since the above-mentioned conventional technique uses the frame aligner, the output of the frame aligner is always the same for the working and the spare. However, since the frame aligner uses a large capacity memory (for one frame), the signal delay is large.

On the other hand, CCITT Recommendation G. 707, G.I. 7
08, G.I. In 709, a multiplexing format is used in which a pointer indicates the frame phase of N (where N is a positive integer) low-speed signals to be multiplexed with a high-speed signal. This pointer indicates the position in the high speed signal of the low speed signal having the frame structure. In addition, a signal having this frame structure has a function of stuff. With this function, the stuff bytes can absorb the wander generated by the temperature change of the transmission line when transmitting the frame. When the frame according to the CCITT recommendation is relayed by the transmission device, the wander is absorbed by the stuff in the frame phase conversion circuit, so the signal delay is small. However, since the transmission line is generally duplicated, the frame phase conversion circuit also has a redundant configuration. In this case, since the wander absorption by the staff is performed independently for the working and the backup, in the output frame of the frame phase conversion circuit, the phase of the low speed signal inside the high speed signal generally does not match between the working and the protection. That is, the output frames of the active and standby frame phase conversion circuits generally do not match. Therefore, there is a possibility that a momentary interruption occurs when switching from the working to the backup.

It is an object of the present invention to output the output frames of the working and spare frame phase conversion circuits having the frame structure passing through the same transmission line at the time of frame phase conversion even in the method of absorbing the wander by the stuffing by the pointer. An object of the present invention is to provide a method and a circuit for switching from active to standby without interruption by matching them.

[0007]

The above object has a frame structure of a multiplexing type in which a pointer indicates the frame phase of N (where N is a positive integer) low speed signals multiplexed into a high speed signal. When the frame phase conversion circuit that converts the frame phase of a signal has a redundant configuration, communication is performed between the active frame phase conversion circuit and the spare frame phase conversion circuit, and both the active frame phase conversion circuit and the spare frame phase conversion circuit are stuffed. This is achieved by simultaneously performing stuffing in the working and backup frame phase conversion circuits and by matching the output frames of the working and backup frame phase conversion circuits by waiting until the state becomes ready for execution.

[0008] Alternatively, the above-mentioned object is to carry out stuffing in the spare or active frame phase conversion circuit when the output frames of the active and standby frame phase conversion circuits do not match when switching from the active to the standby, This is achieved by matching the spare output frames.

Alternatively, the above object is to execute the stuff by forcibly instructing the stuff from the outside when the output frames of the current and the spare frame phase conversion circuits do not match when switching from the active to the spare. , By matching the output frames of both.

[0010]

In order to switch transmission lines without interruption, it is necessary that the output frames of the active frame phase conversion circuit and the backup frame phase conversion circuit match when switching. In order to match the output frames, a method of making the active frame phase conversion circuit and the spare frame phase conversion circuit always perform the same operation, and monitoring both output frames,
If the output frames of both do not match, there is a method of matching the output frames by forcibly executing the stuffing in the spare or working frame phase conversion circuit.

In the method in which the active frame phase conversion circuit and the backup frame phase conversion circuit always perform the same operation, when the active frame phase conversion circuit performs the stuffing, the backup frame phase conversion circuit also performs the stuffing. There must be. Therefore, when the stuff preparation is completed in the working frame phase conversion circuit, a stuff preparation completion signal is sent to the preliminary frame phase conversion circuit. Also,
Even when the stuff preparation is completed in the preliminary frame phase conversion circuit, the stuff preparation completion signal is sent to the working frame phase conversion circuit. A stuffing execution determination circuit is provided in each of the working and spare frame phase conversion circuits. Each stuff execution determination circuit executes stuff only when it receives a stuff ready signal from both the working and spare frame phase conversion circuits. With the above operation, it is possible to wait until both the working and the spare are ready to stuff. As a result, if the stuffing is executed at the same time as the working frame and the spare frame, the working frame phase converting circuit and the spare frame phase converting circuit always perform the same operation. Therefore, when switching from the working mode to the backup mode, switching is performed between frames having the same frame phase, so that no instantaneous interruption occurs.

Alternatively, if either the working or the spare executes the stuff at the same time by instructing the staff to execute the stuff at the same time, the working frame phase conversion circuit and the protection frame phase conversion circuit always perform the same operation. Therefore, it becomes possible to match the output frames. As a result, it is possible to switch from the working to the backup without any interruption.

On the other hand, in the method of monitoring the output frame phase and forcibly executing the stuffing in the spare or working frame phase conversion circuit if the frame phases do not match to match the output frames of both A circuit for monitoring the output frame of the frame phase conversion circuit is provided. When the monitoring circuit detects that the two output frames are different, the monitoring circuit commands the spare frame phase conversion circuit to execute stuff. As a result, the frame phase of the output frame of the preliminary frame phase conversion circuit is matched with the frame phase of the output frame of the active frame phase conversion circuit. By the above operation, switching is performed between frames having the same frame phase, so that no instantaneous interruption occurs.

Alternatively, the phase difference between the input frame and the output frame in the active frame phase conversion circuit is counted by the counter and the value is sent to the preliminary frame phase conversion circuit.
Further, also in the preliminary frame phase conversion circuit, the phase difference between the input frame and the output frame is counted by the counter.
Then, in the spare frame phase conversion circuit, by comparing the values of the counters of the working and spare frame phase conversion circuits, it is determined whether the output frames of the two match, and if they do not match, the spare frame By executing the stuffing in the phase conversion circuit, the output frame of the active frame phase conversion circuit and the output frame of the backup frame phase conversion circuit are matched. As a result, since switching is performed between frames having the same frame phase, no instantaneous interruption occurs.

Alternatively, by sending the frame phase information of the input frame in the active frame phase conversion circuit to the spare frame phase conversion circuit and comparing it with the frame phase information of the input frame in the spare frame phase conversion circuit,
It is determined whether or not the output frames match, and if they do not match, stuffing is executed to match the output frame of the current frame phase conversion circuit with the output frame of the backup frame phase conversion circuit. As a result, since switching is performed between frames having the same frame phase, no instantaneous interruption occurs.

Alternatively, by sending the frame phase information of the output frame in the active frame phase conversion circuit to the spare frame phase conversion circuit and comparing it with the frame phase information of the output frame in the spare frame phase conversion circuit,
It is determined whether or not the output frames match, and if they do not match, stuffing is executed to match the output frame of the current frame phase conversion circuit with the output frame of the backup frame phase conversion circuit. As a result, since switching is performed between frames having the same frame phase, no instantaneous interruption occurs.

[0017]

EXAMPLE A first example of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 14-1 and the frame phase of the signal on the spare input highway 11-2 is converted. And the selector 10 for selecting one of the signal on the output highway 14-1 and the signal on the output highway 14-2.
Composed of and. The active frame phase conversion circuit 31
A buffer 1-1 that stores a signal multiplexed in bytes on the highway 11-1, and a write that indicates an address when writing a signal to the buffer 1-1 according to a reception clock (hereinafter referred to as CLK1-1). Control unit 2-1
From the buffer 1-1 to the device clock (hereinafter, CLK2
Called. ), A read control unit 3-1 that indicates an address for reading a signal and a write address and a read address that are given to the buffer 1-1 are compared to detect the approach between the two. A phase comparator 4-1 for instructing the read controller 3-1 to execute reading or skipping, and a buffer 1-1.
5-1 for storing a part of the output frame of the
A write controller 6-1 for instructing an address when writing a signal to the buffer 5-1 according to CLK2; and a read controller 7-1 for instructing an address for reading a signal from the buffer 5-1 according to CLK2. Buffer 5
If a write address and a read address given to -1 are compared to detect the approach between the two, a phase comparison instructing the read control unit 7-1 to execute justification by reading twice or skipping the buffer 5-1. The section 8-1 and the selector 9-1 for inserting the pointer generated by the read control section 7-1 into the signal on the highway 13-1. On the other hand, the preliminary frame phase conversion circuit 32 includes a buffer 1-2 that stores a signal multiplexed in bytes on the highway 11-2,
A write control unit 2-2 for instructing an address when writing a signal to the buffer 1-2 according to a reception clock (hereinafter, referred to as CLK1-2), and a buffer 1-2 to CL.
When the read control unit 3-2 that indicates an address when reading a signal according to K2 and the write address and the read address that are given to the buffer 1-2 are compared to detect the approach of the two, it is detected twice for the buffer 1-2. Phase comparison unit 4-2 for determining reading or skipping
A buffer 5-2 for storing only a part of the output frame of the buffer 1-2, a write control unit 6-2 for instructing an address when writing a signal to the buffer 5-2 according to CLK2, and a buffer 5- 2 to CLK2, the read control unit 7-2 which indicates an address when reading a signal, and the write address and the read address given to the buffer 5-2 are compared to detect the approach between the two, the buffer 5-2 is detected. Insert the pointer generated by the read control unit 7-2 into the signal on the highway 13-2 and the phase comparison unit 8-2 that instructs the read control unit 7-2 to execute the justification by double reading or skipping. Selector 9-2, and the received frame phase signal 17-1 sent from the active frame phase conversion circuit 31 Checks whether the output frame of the frame phase conversion circuit of the working and the spare by comparing the received frame phase signal 17-2 of the frame phase conversion circuit 32 is coincident, if they do not coincide buffer 5
-2 is configured by a justification execution determination unit 19 that issues a double reading or skipping instruction to the read control unit 7-2. Further, the system comprises a selector 10 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

Before explaining the operation of the above embodiment, the format of a signal to be processed will be described with reference to FIG. The signal to be processed in this embodiment is recommended by the International Telegraph and Telephone Consultative Committee (CCITT) G. 707, 708, 70
Synchronous transfer module level 1 defined in 9
(Hereinafter referred to as STM-1) frame. The type of pointer used is an administrative unit level 4 pointer (hereinafter referred to as AU-4 pointer). Virtual in the STM-1 frame
A container level 4 (hereinafter referred to as VC-4) is accommodated, and an AU-4 pointer indicates the position of the VC-4 within the STM-1 frame.

Returning to FIG. 1, the active frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The write control unit 2-1 operates according to CLK1-1, and instructs a write address when writing the STM-1 frame into the buffer 1-1. Read control unit 3
-1 operates according to CLK2 and indicates a read address when reading the STM-1 frame from the buffer 1-1. Here, there is a phase variation due to the speed difference between CLK1-1 and CLK2, and the variation is buffer 1-
Absorb by reading twice or skipping one. That is, when the phase comparison unit 4-1 compares the write address with the read address and detects the approach between the two, the double reading or skipping of the buffer 1-1 is executed by S
The read controller 3 at a specific position of the TM-1 frame
Command -1. FIG. 3 shows a frame structure for double reading and skipping. The buffer 5-1 stores only VC-4 in the output STM-1 frame of the buffer 1-1. The write control unit 6-1 instructs a write address to the buffer 5-1 according to CLK2. The read control unit 7-1 gives a read address to the buffer 5-1 according to CLK2. As mentioned earlier, CLK1-
When the difference in speed between 1 and CLK2 is absorbed by double reading or skipping of the buffer 1-1, the phase comparison unit 4-1 is used.
Instructs the write control unit 6-1 as follows. That is, in the case of double reading, the write control unit 6-1 is prohibited from writing, and in the case of skipping reading, the write control unit 6-.
Command 1 to write. By these processes and the AU justification included in the input signal,
When the write address and the read address for the buffer 5-1 approach or exceed a predetermined standard,
The phase comparison unit 8-1 instructs the read control unit 7-2 to execute justification by double reading or skipping of the buffer 5-1. Further, the read control unit 7-1 reads the VC-4 from the buffer 5-1 so as to accommodate the VC-4 read from the buffer 5-1 in the STM-1 frame, and further reads the STM-1 on the read side.
Calculate the AU-4 pointer for the frame, STM-
The selector 9-1 is instructed to insert the calculated AU-4 pointer in one frame. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. Also,
When such a frame phase conversion circuit has a redundant configuration, the selector 10 selects one of the signals on the output highway 14-1 of the active frame phase conversion circuit 31 and the signal on the output highway 14-2 of the backup frame phase conversion circuit 32. , Choose one or the other.

In order to switch from the active frame to the standby frame with no interruption using the selector 10, the active frame phase conversion circuit 3 is used.
The signal on the output highway 14-1 of 1 and the signal on the output highway 14-2 of the spare frame phase conversion circuit 32 must be the same. That is, VC-4 in the STM-1 frame output from the active frame phase conversion circuit 31
Position and ST output from the preliminary frame phase conversion circuit 32
The position of the VC-4 within the M-1 frame must be the same. Therefore, the active frame phase conversion circuit 31 stores the signal 16-1 indicating the received frame phase in the buffer 1-1 and reads it out by CLK2, thereby changing the clock of the signal indicating the received frame phase and outputting the signal. The signal 17-1 is transferred to the spare frame phase conversion circuit 32.
Send to. Similarly, the spare frame phase conversion circuit 32 also performs clock shifting on the signal 16-2 indicating the received frame phase. Then, the justification execution determination unit 19 compares the output signal 17-2 and the output signal 17-1. If there is a difference between the two, it is determined that there is a difference between the working output frame and the spare output frame, and the reading is performed. Control unit 7-
Execute justification by instructing 2 to read or skip the buffer 5-2 twice,
The position of the VC-4 in the output STM-1 frame of the spare frame phase conversion circuit 32 is shifted to match the position of the VC-4 in the output STM-1 frame of the working frame phase conversion circuit 31.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

A second embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 14-1 and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 1 for selecting one from the signal on the output highway 14-1 and the signal on the output highway 14-1 to output to the output highway 14-2.
It consists of 0 and. Further, the current frame phase conversion circuit 31 includes a buffer 1-1 for storing a signal multiplexed in bytes on the highway 11-1 and a buffer 1-1.
And a write control section 2-1 for instructing an address when writing a signal according to a reception clock (hereinafter, referred to as CLK1-1), and a signal is read from the buffer 1-1 according to a device clock (hereinafter, referred to as CLK2). When the approach between the read control unit 3-1 which indicates the address at the time of reading and the read address given to the buffer 1-1 is detected by comparing the write address and the read address with each other, the reading or skipping is performed twice for the buffer 1-1. Phase comparator 4-1 for instructing read controller 3-1 to execute
A buffer 5-1 for storing a part of the output frame of the buffer 1-1, a write controller 6-1 for instructing an address when writing a signal to the buffer 5-1 according to CLK2, and a buffer 5-1. Read control section 7 for instructing an address when reading a signal according to CLK2 from
1 and the write address and the read address given to the buffer 5-1 are compared to detect the approach of the two, the just-execution of the justification by double reading or skipping is performed on the buffer 5-1. 1, a phase comparison unit 8-1 for instructing 1; a selector 9-1 for inserting a pointer generated by the read control unit 7-1 into a signal on the highway 13-1; a frame phase of a received frame and a frame phase of the device. A counter 20-1 that counts the difference between On the other hand, the spare frame phase conversion circuit 32 follows a buffer 1-2 that stores a signal multiplexed in bytes on the highway 11-2, and a receive clock (hereinafter, referred to as CLK1-2) to the buffer 1-2. Write control unit 2-2 for instructing an address when writing a signal and CLK from buffer 1-2
When the approach is detected by comparing the write address and the read address given to the buffer 1-2 with the read control unit 3-2 that instructs the address when reading the signal according to 2, the buffer is read twice with respect to the buffer 1-2. A phase comparison unit 4-2 that determines whether to read or skip.
A buffer 5-2 that stores a part of the output frame of the buffer 1-2, and a write control unit 6 that instructs an address when writing a signal to the buffer 5-2 according to CLK2.
-2 and a read control unit 7-2 for instructing an address when reading a signal from the buffer 5-2 according to CLK2.
When the approach between the write address and the read address given to the buffer 5-2 is detected by comparing the write address and the read address, the read control unit 7-2 executes the justification by reading twice or skipping the buffer 5-2. Phase comparator 8-2 and highway 1
A selector 9-2 that inserts a pointer generated by the read control unit 7-2 into the signal on 3-2, a counter 20-2 that counts the difference between the frame phase of the received frame and the frame phase of the device, The output 22-1 of the counter 20-1 and the output 22-2 of the counter 20-2 sent from the frame phase conversion circuit 31 are compared, and a justification instruction by double reading or skipping is given to the buffer 5-2. Is performed by the justification execution determination unit 19 which performs the read control unit 7-2. The system also includes a selector 10 for selecting one of the outputs from the above-mentioned working and spare frame phase conversion circuits.
Consists of.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 4, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The write control unit 2-1 operates according to CLK1-1, and instructs a write address when writing the STM-1 frame into the buffer 1-1. Read control unit 3
-1 operates according to CLK2 and indicates a read address when reading the STM-1 frame from the buffer 1-1. Here, there is a phase variation due to the speed difference between CLK1-1 and CLK2, and the variation is buffer 1-
Absorb by reading twice or skipping one. That is, the phase comparison unit 4-1 compares the write address and the read address, detects the approach of both, and outputs the buffer 1
-1 is read twice or skipped, STM-1
The read control unit 3-1 is instructed at a specific position of the frame. FIG. 3 shows a frame structure for double reading and skipping. The buffer 5-1 stores only VC-4 in the output frame of the buffer 1-1. Write control unit 6
-1 indicates a write address to the buffer 5-1 according to CLK2. The read control unit 7-1 gives a read address to the buffer 5-1 according to CLK2. As described above, when the difference between the speeds of CLK1-1 and CLK2 is absorbed by the double reading or skipping of the buffer 1-1, the phase comparison unit 4-1 includes the write control unit 6
Instruct -1 as follows. That is, in the case of double reading, the write control unit 6-1 is prohibited from writing, and in the case of skipping reading, the write control unit 6-1 is instructed to write. AU included in these processing and input signals
When the write address and the read address with respect to the buffer 5-1 approach or exceed a predetermined reference due to justification, the phase comparison unit 8-1 instructs the read control unit 7-2 twice the buffer 5-1. Instruct to perform justification by reading or skipping. Further, the read control unit 7-1 reads the VC-4 from the buffer 5-1 so as to accommodate the VC-4 read from the buffer 5-1 in the STM-1 frame, and further reads the STM-1 frame on the read side. A
The U-4 pointer is calculated, and an instruction is issued to the selector 9-1 to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the ST according to the frame phase of the VC-4 in the received STM-1 frame is held by the device.
Change to M-1 frame. The preliminary frame phase conversion circuit 32 also performs the same operation. When such a frame phase conversion circuit has a redundant configuration, the selector 10 outputs the output highway 14-1 of the active frame phase conversion circuit 31.
One of the above signal and the signal on the output highway 14-2 of the preliminary frame phase conversion circuit 32 is selected.

To use the selector 10 to switch from the active frame to the standby frame without interruption, the active frame phase conversion circuit 3 is used.
The signal on the output highway 14-1 of 1 and the signal on the output highway 14-2 of the spare frame phase conversion circuit 32 must be the same. That is, VC-4 in the STM-1 frame output from the active frame phase conversion circuit 31
Position and ST output from the preliminary frame phase conversion circuit 32
The position of the VC-4 within the M-1 frame must be the same. Therefore, the current frame phase conversion circuit 31 stores the signal 16-1 indicating the received frame phase in the buffer 1-1 and reads it by CLK2 to change the clock to the signal 16-1 indicating the received frame phase. The counter 20-1 counts the difference between the output signal 17-1 and the frame phase 21-1 of the apparatus, and outputs the output 22-1 to the preliminary frame phase conversion circuit 32. Similarly, the spare frame phase conversion circuit also changes the clock for the signal 16-2 indicating the received frame phase. Then, the difference between the output signal 17-2 and the frame phase 21-2 of the apparatus is counted by the counter 20-2. The justification execution determination unit 19 compares the output 22-1 of the counter 20-1 with the output 22-2 of the counter 20-2. If there is a difference between the two, the outputs of the working and standby frame phase conversion circuits It is determined that there is a difference between the two, and the justification is executed by instructing the read control unit 7-2 to read or skip the double reading of the buffer 5-1.
The position of the VC-4 in the output STM-1 frame is shifted to match the position of the VC-4 in the output STM-1 frame of the working frame phase conversion circuit 31.

Through the above processing, the output frames of the active frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 are made to coincide with each other, and the active frame and the standby frame are switched without interruption.

A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach of the two, the read control unit 3-1 is instructed to execute the justification by reading twice or skipping the buffer 1-1. Phase comparator 4-1 and highway 11
Phase detector 5-1 which reads the AU-4 pointer of the received STM-1 frame on -1 and generates a signal indicating the frame phase of VC-4 in the STM-1 frame
And a read control unit 3-for the signal on the highway 12-1.
1 and a selector 6-1 for inserting the pointer generated in 1. On the other hand, the spare frame phase conversion circuit 32
Is a buffer 1-2 for storing a signal multiplexed in bytes on the highway 11-2, and a write for instructing an address when a part of the signal is written in the buffer 1-2 according to the reception clock (CLK1-2). The control unit 2-2, the read control unit 3-2 which indicates an address when reading a signal from the buffer 1-2 according to CLK2, and the write address and the read address given to the buffer 1-2 are compared to approach each other. If it is detected, the phase comparison unit 4-2 instructing the read control unit 3-2 to execute justification by double reading or skipping the buffer 1-2, and the reception STM-1 on the highway 11-2. The frame AU-4 pointer is read to generate a signal indicating the VC-4 frame phase in the STM-1 frame. When the difference between the active and standby output frame phases is detected by comparing the received frame phase of the active frame phase conversion circuit 31 with the received frame phase of the active frame phase conversion circuit 31, The justification execution determination unit 19 that instructs the read control unit 3-2 to execute the justification, and the selector 6-2 that inserts the pointer generated by the read control unit 3-2 into the signal on the highway 12-2.
Composed of and. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 5, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase fluctuation due to the speed difference between -1 and CLK2, and the fluctuation is absorbed by the double reading or skipping of the buffer 1-1. That is, when the phase comparison unit 4-1 compares the write address and the read address given to the buffer 1-1 and detects the approach of both, the justification by the double reading or the skip of the buffer 1-1 is performed. The execution is instructed to the read control unit 3-1 at the specific position of the STM-1 frame. Further, the read control unit 3-1 reads the VC-4 from the buffer 1-1 so as to accommodate the VC-4 read from the buffer 1-1 in the STM-1 frame, and further reads the STM-1 frame on the read side. The AU-4 pointer is calculated, and an instruction is issued to the selector 6-1 to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 causes the signal on the output highway 13-1 of the active frame phase conversion circuit 31 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32. Select one of them.

In order to switch from the active frame to the standby frame with no interruption by using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, the frame phase detection unit 5-1 of the active frame phase conversion circuit 31 detects V in the received STM-1 frame.
The frame phase of C-4 is detected by reading the AU-4 pointer, the signal 16-1 indicating the frame phase of the VC-4 is stored in the buffer 1-1, and is read by CLK2 to receive VC-4. The clock 16 is changed to the signal 16-1 indicating the frame phase, and the output signal 17-1 is sent to the preliminary frame phase conversion circuit 32. Similarly, the spare frame phase conversion circuit 32 receives the received VC.
The clock re-arrangement is performed on the signal 16-2 indicating the frame phase of -4. Then, the output signal 17-2
And the output signal 17-1 are compared by the justification execution determination unit 19, and if there is a difference between them, it is determined that there is a difference between the output frames of the active and standby frame phase conversion circuits, and the read control unit 3- Justification is executed by instructing 2 to read twice or skip the buffer 1-2, shift the position of VC-4 in the output STM-1 frame of the preliminary frame phase conversion circuit 32, and change the current frame phase. Output STM-1 of conversion circuit 31
Align with the position of VC-4 in the frame.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

A fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach of the two, the read control unit 3-1 is instructed to execute the justification by reading twice or skipping the buffer 1-1. Phase comparator 4-1 and highway 11
Phase detector 5-1 which reads the AU-4 pointer of the received STM-1 frame on -1 and generates a signal indicating the frame phase of VC-4 in the STM-1 frame
, A counter 20-1 for counting the difference between the received frame phase and the frame phase of the device, and a selector 6-1 for inserting the pointer generated by the read control unit 3-1 into the signal on the highway 12-1. Composed. On the other hand, the spare frame phase conversion circuit 32 includes a buffer 1-2 that stores a signal multiplexed on the highway 11-2 in byte units.
And a write control unit 2-2 for instructing an address when a part of the signal is written to the buffer 1-2 according to the reception clock (CLK1-2), and an address for reading a signal from the buffer 1-2 according to CLK2. If the read control unit 3-2 that performs the read operation and the write address and the read address given to the buffer 1-2 are detected to approach each other, the justification is performed by double reading or skipping the read operation of the buffer 1-2. Phase comparison unit 4-2 for instructing the read control unit 3-2
Then, the AU-4 pointer of the received STM-1 frame on the highway 11-2 is read and V in the STM-1 frame is read.
A frame phase detector 5-2 that generates a signal indicating the frame phase of C-4, a counter 20-2 that counts the difference between the received frame phase and the frame phase of the device, and the counter 20 of the active frame phase conversion circuit 31. -1 is compared with the output of the counter 20-2 of the spare frame phase conversion circuit 32, and if a difference between the working and spare output frame phases is detected, the read control unit 3-2 executes justification. The justification execution determination unit 19 that gives an instruction and the selector 6-2 that inserts the pointer generated by the read control unit 3-2 into the signal on the highway 12-2. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 6, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase variation due to a speed difference between -1 and CLK2, and the variation is absorbed by the double reading or skipping justification of the buffer 1-1. That is, when the phase comparison unit 4-1 compares the write address and the read address given to the buffer 1-1 and detects the approach of both, the STM is executed to read twice or skip the reading of the buffer 1-1. -At the specific position of -1 frame, the read control unit 3-1 is instructed. Further, the read control unit 3-1 uses the VC read from the buffer 1-1.
Buffer 1 to accommodate -4 in the STM-1 frame
Read VC-4 from -1 and ST on the read side
Calculate the AU-4 pointer added to the M-1 frame,
The selector 6-1 is instructed to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 operates in the active frame phase conversion circuit 3
One of the signal on the output highway 13-1 of No. 1 and the signal on the output highway 13-2 of the preliminary frame phase conversion circuit 32 is selected.

In order to switch from the active frame to the standby frame without interruption using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, the frame phase detection unit 5-1 of the active frame phase conversion circuit 31 detects V in the received STM-1 frame.
The frame phase of C-4 is detected by reading the AU-4 pointer, the signal 16-1 indicating the frame phase of the VC-4 is stored in the buffer 1-1, and is read by CLK2 to receive VC-4. The clock 16 is changed for the signal 16-1 indicating the frame phase of. Further, the output signal 17-1 and the device frame phase 21-
The counter 20-1 counts the difference of 1 and outputs 22-1.
To the preliminary frame phase conversion circuit 32. Similarly, the spare frame phase conversion circuit 32 also performs clock shifting on the signal 16-2 indicating the frame phase of the reception VC-4. Then, the counter 20-2 counts the difference between the output signal 17-2 and the device frame phase 21-2, and the justification execution determination unit 19 compares the output 22-2 and the above-mentioned 22-1 with each other. If there is a difference, it is determined that there is a difference between the current output frame and the spare output frame, and the justification is executed by instructing the read control unit 3-2 to read twice or skip the read of the buffer 1-2, and to perform the spare operation. The position of the VC-4 in the output STM-1 frame of the frame phase conversion circuit 32 is shifted to match the position of the VC-4 in the output STM-1 frame of the active frame phase conversion circuit 31.

Through the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active frame is switched to the standby frame without interruption.

A fifth embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach between the two, the read control unit 3-1 is instructed to execute the justification by reading twice or skipping the buffer 1-1. Phase comparator 4-1 and highway 12
-1 and a selector 6-1 which inserts a pointer generated by the read control unit 3-1 into the signal above -1.

On the other hand, the spare frame phase conversion circuit 32 is
A buffer 1-2 that stores a signal multiplexed in bytes on the highway 11-2, and a write control unit that instructs an address when a part of the signal is written to the buffer 1-2 according to a reception clock (CLK1-2). 2-2, a read control unit 3-2 for instructing an address when reading a signal from the buffer 1-2 according to CLK2, and a buffer 1-
If the approach of the two is detected by comparing the write address and the read address given to 2, the buffer 1
-2, a phase comparison unit 4-2 for instructing the read control unit 3-2 to execute justification by double reading or skipping, and an active frame phase conversion circuit 3
When the difference between the active and standby output frame phases is detected by comparing the AU-4 pointer value of the first output frame and the AU-4 pointer value of the output frame of the backup frame phase conversion circuit 32, the read control unit 3- 2 includes a justification execution determination unit 19 for instructing execution of justification, and a selector 6-2 for inserting a pointer generated by the read control unit 3-2 into a signal on the highway 12-2. .

Further, the system comprises a selector 7 for selecting one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 6, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase variation due to a speed difference between -1 and CLK2, and the variation is absorbed by the double reading or skipping justification of the buffer 1-1. That is, when the phase comparison unit 4-1 compares the write address and the read address given to the buffer 1-1 and detects the approach of both, the STM is executed to read twice or skip the reading of the buffer 1-1. -At the specific position of -1 frame, the read control unit 3-1 is instructed. Further, the read control unit 3-1 uses the VC read from the buffer 1-1.
Buffer 1 to accommodate -4 in the STM-1 frame
Read VC-4 from -1 and ST on the read side
Calculate the AU-4 pointer added to the M-1 frame,
The selector 6-1 is instructed to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 operates in the active frame phase conversion circuit 3
One of the signal on the output highway 13-1 of No. 1 and the signal on the output highway 13-2 of the preliminary frame phase conversion circuit 32 is selected.

In order to switch from the active frame to the standby frame with no interruption using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, the frame phase detection unit 5-1 of the active frame phase conversion circuit 31 detects V in the received STM-1 frame.
The frame phase of C-4 is detected by reading the AU-4 pointer, the signal 16-1 indicating the frame phase of the VC-4 is stored in the buffer 1-1, and is read by CLK2 to receive VC-4. The clock 16 is changed for the signal 16-1 indicating the frame phase of. Further, the output signal 17-1 and the device frame phase 21-
The counter 20-1 counts the difference of 1 and outputs 22-1.
To the preliminary frame phase conversion circuit 32. Similarly, the spare frame phase conversion circuit 32 also performs clock shifting on the signal 16-2 indicating the frame phase of the reception VC-4. Then, the counter 20-2 counts the difference between the output signal 17-2 and the device frame phase 21-2, and the justification execution determination unit 19 compares the output 22-2 and the above-mentioned 22-1 with each other. If there is a difference, it is determined that there is a difference between the current output frame and the spare output frame, and the justification is executed by instructing the read control unit 3-2 to read twice or skip the read of the buffer 1-2, and to perform the spare operation. The position of the VC-4 in the output STM-1 frame of the frame phase conversion circuit 32 is shifted to match the position of the VC-4 in the output STM-1 frame of the active frame phase conversion circuit 31.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

A fifth embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach between the two, the read control unit 3-1 is instructed to execute the justification by reading twice or skipping the buffer 1-1. Phase comparator 4-1 and highway 12
-1 and a selector 6-1 which inserts a pointer generated by the read control unit 3-1 into the signal above -1. On the other hand, the spare frame phase conversion circuit 32 uses the highway 11
-2, a buffer 1-2 for storing signals multiplexed in byte units, and a buffer 1-2 for receiving a reception clock (CLK1
-2), a write control unit 2-2 for instructing an address when writing a part of the signal, and buffers 1-2 to C
When the approach between the read control unit 3-2 for instructing the address when reading the signal according to LK2 and the write address and the read address given to the buffer 1-2 is detected, 2 for the buffer 1-2 is detected.
A phase comparison unit 4-2 for instructing the read control unit 3-2 to execute justification by re-reading or skipping, an AU-4 pointer value of the output frame of the active frame phase conversion circuit 31, and a preliminary frame phase conversion circuit. Three
If the difference between the phases of the output frame of the working frame and the output frame of the spare frame is detected by comparing the AU-4 pointer values of the output frames of No. 2 and No. 2, the justification execution determination unit for instructing the read control unit 3-2 to execute justification. 19 and a selector 6-2 for inserting the pointer generated by the read control unit 3-2 into the signal on the highway 12-2.
Composed of and. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 7, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase variation due to a speed difference between -1 and CLK2, and the variation is absorbed by the double reading or skipping justification of the buffer 1-1. That is, when the phase comparison unit 4-1 compares the write address and the read address given to the buffer 1-1 and detects the approach of both, the justification by the double reading or the skip of the buffer 1-1 is performed. Run,
The read control unit 3-1 is instructed at a specific position of the STM-1 frame. Further, the read control unit 3-1 reads the VC-4 from the buffer 1-1 so as to accommodate the VC-4 read from the buffer 1-1 in the STM-1 frame, and further reads the STM-1 frame on the read side. The selector 6-1 calculates the AU-4 pointer and inserts the calculated AU-4 pointer into the STM-1 frame.
Give instructions to. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. When such a frame phase conversion circuit has a redundant configuration, the selector 7 outputs the output highway 13- of the active frame phase conversion circuit 31.
Either the signal on 1 or the signal on the output highway 13-2 of the preliminary frame phase conversion circuit 32 is selected.

In order to switch from the active frame to the standby frame with no interruption using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, the current frame phase conversion circuit 31 sends to the backup frame phase conversion circuit 32 an AU-4 pointer indicating the frame phase of VC-4 in the output STM-1 frame. In the preliminary frame phase conversion circuit 32, the AU-4 pointer value sent from the active frame phase conversion circuit 31 and the AU of the output frame of the preliminary frame phase conversion circuit 32.
The -4 pointer value is compared by the justification execution determination unit 19, and if they are different, it is determined that there is a difference between the current output frame and the spare output frame, and the read control unit 3
-2 by ordering justification by reading twice or skipping the buffer 1-2,
The position of the VC-4 in the output STM-1 frame of the spare frame phase conversion circuit 32 is shifted to match the position of the VC-4 in the output STM-1 frame of the working frame phase conversion circuit 31.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 are made to coincide with each other, and the active frame is switched to the spare without any interruption.

The sixth embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach between the two, the phase comparison unit 4 which issues a justification request by double reading or skipping to the buffer 1-1.
-1 and the justification request signals 23-1 and 23-2 of the active and standby frame phase conversion circuits are both received and read control is performed on the justification by double reading or skipping for the buffer 1-1. The justification execution determination unit 19-1 for instructing the unit 3-1 and the selector 6-1 for inserting the pointer generated by the read control unit 3-1 into the signal on the highway 12-1. R. On the other hand, the spare frame phase conversion circuit 32 includes a buffer 1-2 that stores a signal multiplexed on the highway 11-2 in byte units.
And a write control unit 2-2 for instructing an address when a part of the signal is written to the buffer 1-2 according to the reception clock (CLK1-2), and an address for reading a signal from the buffer 1-2 according to CLK2. The read control unit 3-2 for performing the phase comparison in which the write address and the read address given to the buffer 1-2 are compared to detect the approach between the two, and issues a double read or skip request to the buffer 1-2. When both the unit 4-2 and the justification request signals 23-1 and 23-2 of the current and standby frame phase conversion circuits are received, the double reading or skipping for the buffer 1-2 is read out by the read control unit 3 -2, the justification execution determination unit 19-2, and the highway 12
-2 and a selector 6-2 for inserting a pointer generated by the read control unit 3-2 into the signal on the -2. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 8, the active frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase variation due to the speed difference between -1 and CLK2, and the variation is absorbed by executing the justification by double reading or skipping of the buffer 1-1. Further, the read control unit 3-1 reads the VC-4 from the buffer 1-1 so as to accommodate the VC-4 read from the buffer 1-1 in the STM-1 frame, and further reads the STM-1 frame on the read side. A
The U-4 pointer is calculated, and an instruction is issued to the selector 6-1 to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the ST according to the frame phase of the VC-4 in the received STM-1 frame is held by the device.
Change to M-1 frame. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 causes the signal on the output highway 13-1 of the active frame phase conversion circuit 31 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32. Select one of them.

In order to switch from the active frame to the standby frame with no interruption using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. For that purpose, the active frame phase conversion circuit 31 and the backup frame phase conversion circuit 32 must always perform the same operation. That is, the current frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 must execute justification at the same time. Therefore, the phase comparison unit 4-1 determines the justification execution determination unit 19- when the write address and the read address given to the buffer 1-1 approach or exceed a predetermined standard.
1 and 19-2 justification request signal 23
Give -1. Further, the phase comparison unit 4-2 includes the buffer 1-
When the write address and the read address given to 2 approach or exceed a predetermined standard, a justification request signal 23-2 is issued to the justification execution determination units 19-1 and 19-2. The justification execution determination unit 19-1 commands the read control unit 3-1 to execute justification when both the justification request signals 23-1 and 23-2 are received. The justification execution determination unit 19-2 commands the read control unit 3-2 to execute the justification when both the justification request signals 23-1 and 23-2 are received. As a result, both the active frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 can perform justification at the same time, so that the output frames of both can always be matched.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

The seventh embodiment of the present invention will be described with reference to FIG. In this embodiment, the frame phase of the signal on the working input highway 11-1 is converted and output to the output highway 13-1, and the frame phase of the signal on the spare input highway 11-2 is converted. And a selector 7 for selecting one of the signal on the output highway 13-1 and the signal on the output highway 13-2.
Composed of and. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
If the write address and the read address given to the buffer 1-1 are compared to detect the approach between the two, a justification request by double reading or skipping for the buffer 1-1 is issued to the read control unit 3.
-1 and the phase comparison unit 4-1 that outputs to the preliminary frame phase conversion circuit 32, and the selector 6 that inserts the pointer generated by the read control unit 3-1 into the signal on the highway 12-1.
1 and 1. On the other hand, the preliminary frame phase conversion circuit 32 includes a buffer 1-2 that stores the signals multiplexed on a byte unit on the highway 11-2, and a buffer 1-2.
A write control unit 2-2 for instructing an address when a part of the signal is written according to the reception clocks (CLK1-2)
In the case where the read controller 3-2 for instructing an address when reading a signal from the buffer 1-2 according to CLK2 and the approach between the read address and the read address given to the buffer 1-2 are detected. A phase comparison unit 4-2 which issues a double read request or a read skip request to the buffer 1-2, and a justification request signal 23-of the active and standby frame phase conversion circuits.
On the highway 12-2, a justification execution determination unit 19 for instructing the read control unit 3-2 to perform double reading or skipping for the buffer 1-2 when either 1 or 23-2 is received. And a selector 6-2 which inserts a pointer generated by the read control unit 3-2 into the signal. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 9, the current frame phase conversion circuit 3
The operation of No. 1 will be described. STM from highway 11-1
A -1 frame signal is developed in parallel in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 is a VC in the STM-1 frame.
Only -4 is stored. The write control unit 2-1 uses CLK1
-1 to specify a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and instructs the read address when reading the VC-4 from the buffer 1-1 so as to change the VC-4 into the STM-1 frame according to the frame phase of the device. . CLK1 here
There is a phase variation due to the speed difference between -1 and CLK2, and the variation is absorbed by executing the justification by double reading or skipping of the buffer 1-1. Further, the read control unit 3-1 reads the VC-4 from the buffer 1-1 so as to accommodate the VC-4 read from the buffer 1-1 in the STM-1 frame, and further reads the STM-1 frame on the read side. A
The U-4 pointer is calculated, and an instruction is issued to the selector 6-1 to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the ST according to the frame phase of the VC-4 in the received STM-1 frame is held by the device.
Change to M-1 frame. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 causes the signal on the output highway 13-1 of the active frame phase conversion circuit 31 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32. Select one of them.

In order to switch from the active frame to the standby frame with no interruption by using the selector 7, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. For that purpose, the active frame phase conversion circuit 31 and the backup frame phase conversion circuit 32 must always perform the same operation. That is, the current frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 must execute justification at the same time. Therefore, the phase comparison unit 4-1 requests the justification request to the read control unit 3-1 and the justification execution determination unit 19 when the write address and the read address given to the buffer 1-1 approach or exceed a predetermined standard. Issue signal 23-1. Further, the phase comparison unit 4-2 outputs the justification request signal 23-2 to the justification execution determination unit 19 when the write address and the read address given to the buffer 1-2 approach or exceed a predetermined standard. . When receiving the justification request signal 23-1, normally, the justification execution determination unit 19 commands the read control unit 3-2 to execute the justification. Further, when switching from the standby mode to the active mode, the justification execution determination unit 19 instructs the read control unit 3-2 to execute the justification when the justification request signal 23-2 is received. To do. That is, in the preliminary frame phase conversion circuit 32, both the justification can be executed by the judgment of the phase comparison unit 4-2 and the justification can be executed by the instruction of the active frame phase conversion circuit 31. As a result, both the active frame phase conversion circuit 31 and the spare frame phase conversion circuit 32 can perform justification at the same time, so that the output frames of both can always be matched.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active frame is switched to the standby frame without interruption.

The eighth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the frame phase of the signal on the working input highway 11-1 is converted to the output highway 13-1.
The active frame phase conversion circuit 31 and the spare input highway 11-2 and the spare frame phase conversion circuit 32, which outputs the converted frame phase to the output highway 13-2, and the output highway 13-1. The selector 7 selects one of the signals on the output highway 13-2 and the other. Further, the current frame phase conversion circuit 31 stores a part of the signal multiplexed in bytes on the highway 11-1 and a buffer 1-1, and a reception clock (hereinafter referred to as CLK1-1) in the buffer 1-1. (Hereinafter referred to as "."), And a read control unit 3 for instructing an address when writing a signal according to (1). -1, and
When the write address and the read address given to the buffer 1-1 are compared to detect the approach between the two, the phase comparison unit 4 which issues a justification request by double reading or skipping to the buffer 1-1.
-1, and either the justification request signal 23-1 or the justification request signal 23-1 or 24-1 of the current and standby frame phase conversion circuits is received, the justification by double reading or skipping is read to the buffer 1-1. Justification execution determination unit 19-1 for instructing the control unit 3-1; a pointer display unit 25-1 for displaying the AU-4 pointer value of the output frame of the current frame phase conversion circuit 31; Justification instruction section 26-1 for outputting the execution request signal 24-1 of the above according to an instruction from the outside, and a selector 6-for inserting the pointer generated by the read control section 3-1 into the signal on the highway 12-1. 1 and 1. On the other hand, the spare frame phase conversion circuit 32 stores a part of the signal in the buffer 1-2 according to the reception clock (CLK1-2) in the buffer 1-2, which stores the signal multiplexed in bytes on the highway 11-2. A write control unit 2-2 for instructing an address for writing, a read control unit 3-2 for instructing an address for reading a signal from the buffer 1-2 according to CLK2, and a buffer 1-2.
When the approaching of both is detected by comparing the write address and the read address given to the buffer 1-
2. A phase comparator 4-2 that issues a request for justification by double reading or skipping for 2 and a justification request signal 23-2 or 24-2 of the active and standby frame phase conversion circuits is received. In this case, the justification execution determination unit 19-2 for instructing the read control unit 3-2 to perform double reading or skipping for the buffer 1-2, and AU-4 of the output frame of the preliminary frame phase conversion circuit 32. A pointer display section 25-2 for displaying a pointer value and a justification instruction section 26-for outputting a justification execution request signal 24-2 by an external instruction.
2 and the read control unit 3 for the signal on the highway 12-2.
-2 and a selector 6-2 for inserting the pointer generated in -2. Further, the system comprises a selector 7 which selects one of the outputs from the above-mentioned working and spare frame phase conversion circuits.

The format of the signal to be processed is the same as in the first embodiment.

Returning to FIG. 10, the operation of the frame phase conversion circuit will be described using the active frame phase conversion circuit 31.
From the highway 11-1, an STM-1 frame signal is expanded in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 stores only VC-4 in the STM-1 frame. The write control unit 2-1 operates according to CLK1-1, and instructs a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and in order to change the VC-4 into an STM-1 frame according to the frame phase of the apparatus, the VC is changed.
-4 indicates the read address when reading from the buffer 1-1. Here, there is a phase fluctuation due to the speed difference between CLK1-1 and CLK2, and the fluctuation is detected by the buffer 1
Absorb by performing a justification by double reading or skipping of -1. Also, the read control unit 3-1 reads the V read from the buffer 1-1.
In order to accommodate C-4 in the STM-1 frame, VC-4 is read from the buffer 1-1, and S on the read side is read.
Compute the AU-4 pointer for the TM-1 frame,
The selector 6-1 is instructed to insert the calculated AU-4 pointer into the STM-1 frame. By the above operation, the VC-4 in the received STM-1 frame is transferred to the STM-1 frame according to the frame phase of the device. The preliminary frame phase conversion circuit 32 also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 7 operates in the active frame phase conversion circuit 3
One of the signal on the output highway 13-1 of No. 1 and the signal on the output highway 13-2 of the preliminary frame phase conversion circuit 32 is selected.

In order to switch from the active to the standby by the selector 7 without interruption, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 31 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, if the output frames of the active frame phase conversion circuit 31 and the backup frame phase conversion circuit 32 are different, it is necessary to forcibly execute the justification in either the active or standby frame phase conversion circuit. is there. Therefore, when switching transmission lines, look at the pointer display units 25-1 and 25-2,
If the two values are different, the justification instructing unit 26-2 is used to issue the justification request signal 24-2 to execute the justification. By the above operation, justification is executed, and the output STM- of the preliminary frame phase conversion circuit 32 is executed.
The position of VC-4 in one frame is shifted and the output of the active frame phase conversion circuit 31 is VC- in the STM-1 frame.
Adjust to position 4. As a result, the output frames of the active frame phase conversion circuit 31 and the backup frame phase conversion circuit 32 can be matched.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

The ninth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the frame phase of the signal on the working input highway 11-1 is converted to the output highway 13-1.
The active frame phase conversion circuit 31 and the spare input highway 11-2 and the spare frame phase conversion circuit 32, which outputs the converted frame phase to the output highway 13-2, and the output highway 13-1. It comprises a selector 9 for selecting one of the signals on the output highway 13-2 and a monitoring unit 10 for comparing the signals on the highways 13-1 and 13-2. The active frame phase conversion circuit 31 further includes a buffer 1-1 for storing a part of the signal multiplexed on the highway 11-1 in byte units.
And a reception clock (hereinafter, CLK1-
It is called 1. ), And a read controller 3 for instructing an address when a signal is written, and a read controller 3 for instructing an address when a signal is read from the buffer 1-1 according to a device clock (hereinafter referred to as CLK2).
-1 and the write address and the read address given to the buffer 1-1 are detected to approach each other, the read control unit 3 executes the justification by reading twice or skipping the buffer 1-1. -1, the phase comparison section 4-1, which instructs -1, the phase comparison section 5-1, the phase comparison section 6-1, and the phase comparison section 4
, 5-1 and 6-1 for selecting one, and a selector 8 for inserting the pointer generated by the read control unit 3-1 into the signal on the highway 12-1.
-1 and. On the other hand, the preliminary frame phase conversion circuit 32 includes a buffer 1-2 that stores the signals multiplexed on a byte unit on the highway 11-2 and a buffer 1-.
2, a write control unit 2-instructing an address when writing a part of the signal in accordance with the reception clock (CLK1-2)
2, and a read control unit 3-2 for instructing an address when reading a signal from the buffer 1-2 according to CLK2,
When the write address and the read address given to the buffer 1-2 are compared to detect the approach of the two, the read control unit 3-2 is instructed to execute the justification by reading twice or skipping the buffer 1-2. Phase comparator 4-2 and phase comparator 5-
2, the phase comparison unit 6-2, and the phase comparison units 4-2 and 5
-2 and 6-2 to select one selector 7-2
And a read control unit 3-for the signal on the highway 12-2.
2 and a selector 8-2 for inserting the pointer generated in 2. Further, the system compares the selector 9 for selecting one of the outputs from the working and spare frame phase conversion circuits with the output frame of the working frame phase conversion circuit 31 and the output frame of the spare frame phase conversion circuit 32. If they do not match, the selector 7-
1 or the monitoring unit 10 for instructing the selector 7-2 to change the selection of the phase comparison unit. The format of the signal to be processed is the same as that of the first embodiment.

Returning to FIG. 11, the operation of the frame phase conversion circuit will be described using the active frame phase conversion circuit 31.
From the highway 11-1, an STM-1 frame signal is expanded in 8 bits and input in a state where frame synchronization and byte synchronization are established. The buffer 1-1 stores only VC-4 in the STM-1 frame. The write control unit 2-1 operates according to CLK1-1, and instructs a write address when writing the VC-4 into the buffer 1-1. The read control unit 3-1 operates according to CLK2, and in order to change the VC-4 into an STM-1 frame according to the frame phase of the apparatus, the VC is changed.
-4 indicates the read address when reading from the buffer 1-1. Here, there is a phase fluctuation due to the speed difference between CLK1-1 and CLK2, and the fluctuation is detected by the buffer 1
It is absorbed by justification by double reading or skipping of -1. That is, the write address and the read address given to the buffer 1-1 are compared by the phase comparison unit selected by the selector 7-1 of the phase comparison units 4-1, 5-1 and 6-1 and the two approaches. If it is detected, the justification by reading twice or skipping the buffer 1-1 is executed, and STM-1 is executed.
The read control unit 3-1 is instructed at a specific position of the frame. Further, the read control unit 3-1 includes the buffer 1-1.
In order to accommodate the VC-4 read from the STM-1 frame in the STM-1 frame, the VC-4 is read from the buffer 1-1, and the AU-4 for the STM-1 frame on the read side is read.
AU calculated pointer and calculated to STM-1 frame
-4 Instructs the selector 8-1 to insert the pointer. By the above operation, the VC-4 in the received STM-1 frame is STM-1 according to the frame phase of the device.
Put it on the frame and change it. Preliminary frame phase conversion circuit 32
Also performs the same operation. Further, when such a frame phase conversion circuit has a redundant configuration, the selector 9 causes the signal on the output highway 13-1 of the active frame phase conversion circuit 31 and the output highway 13 of the spare frame phase conversion circuit 32.
Select either one of the signals above -2.

In order to switch from the active to the standby by the selector 9 without interruption, the active frame phase conversion circuit 31 is used.
The signal on the output highway 13-1 and the signal on the output highway 13-2 of the spare frame phase conversion circuit 32 must be the same. That is, the position of VC-4 in the STM-1 frame output from the current frame phase conversion circuit 31 and the STM output from the preliminary frame phase conversion circuit 32.
The position of the VC-4 within the -1 frame must be the same. Therefore, the monitoring unit 10 compares the output frames of the active frame phase conversion circuit 31 and the backup frame phase conversion circuit 32, and if the two do not match, executes justification for the backup frame phase conversion circuit 32. Command. At this time, the spare frame phase conversion circuit 32
Selector 7-2 selects a phase comparison unit different from the currently selected phase comparison unit. Here, the phase comparison unit 4-
2, 5-2 and 6-2 have different justification execution conditions. Since the justification execution condition is changed by changing the phase comparison unit selected by the selector 7-2, the justification is forcibly executed in the preliminary frame phase conversion circuit 32. By the above operation, justification is executed, the position of VC-4 in the output STM-1 frame of the preliminary frame phase conversion circuit 32 is shifted, and the output STM-1 of the current frame phase conversion circuit 31 is shifted.
Align with the position of VC-4 in the frame.

By the above processing, the output frames of the active frame phase conversion circuit 31 and the standby frame phase conversion circuit 32 are made to coincide with each other, and the active mode is switched to the standby mode without interruption.

[0068]

As described above, according to the present invention, the outputs of the active and standby frame conversion circuits are forcibly matched with each other by using the stuff, so that the active and standby can be switched without interruption.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a hitless transmission path switching circuit according to the present invention.

FIG. 2 is a diagram of a frame used to describe an embodiment according to the present invention.

FIG. 3 is a diagram of a frame used to describe an embodiment according to the present invention.

FIG. 4 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 5 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 6 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 7 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 8 is a diagram showing the configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 9 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 10 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

FIG. 11 is a diagram showing a configuration of an embodiment of a hitless transmission line switching circuit according to the present invention.

[Explanation of symbols]

1-1 ... Buffer, 1-2 ... Buffer, 2-1 ... Write control section, 2-2 ... Write control section, 3-1 ... Read control section, 3-2 ... Read control section, 4-1 ... Phase comparison , 4-2 ... Phase comparison section, 5-1 ... Buffer or frame phase detection section, 5-2 ... Buffer or frame phase detection section or phase comparison section, 6-1 ... Write control section or selector or phase comparison section, 6-2 ... write control unit or selector, 7 ... selector, 7-1 ...
Read control unit or selector, 7-2 ... Read control unit or selector, 8-1 ... Phase comparison unit or selector, 8-2 ... Phase comparison unit or selector, 9-1
... selector, 9-2 ... selector, 10 ... selector or monitoring unit, 11-1 to 14-1 ... highway, 11-2
~ 14-2 ... Highway, 15 ... Highway, 16-
1, 17-1 ... Received frame phase, 16-2, 17-2
... reception frame phase, 18-1, 18-2 ... AU-4 pointer of output frame, 19 ... justification execution determination unit, 20-1, 20-2 ... counter, 21-
1, 21-2 ... Device frame phase, 22-1, 22-2
... Counter output 23-1, 23-2 ... Justification request signal, 24-1, 24-2 ... Justification request signal, 25-1, 25-2 ... Pointer display section, 26-1, 26- 2 ... Justification instruction section, 31 ... Working frame phase conversion circuit, 32 ...
Preliminary frame phase conversion circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H04L 7/027 (72) Inventor Masahiro Ashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. Mfg. Co., Ltd. Information & Communication Business Department (72) Inventor Tadayuki Sugano 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Communication Business Department (72) Inventor Koji Kogure 1-6, Uchisai-cho, Chiyoda-ku, Tokyo Date (72) Inventor Hideki Kataoka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan Telegraph and Telephone Corp.

Claims (35)

[Claims] 1. N (where N
Is a positive integer) and simultaneously transmits the high-speed signal in a multiplexed format in which the frame phase of the low-speed signal is indicated by the pointer, and the receiving side converts the pointer value of the reception signal of the current transmission path. In the system, one of the first output signal of the working frame phase conversion circuit and the second output signal of the protection frame phase conversion circuit that converts the pointer value of the reception signal of the protection transmission line is selected. By exchanging information regarding the frame phase between the circuit and the preliminary frame phase conversion circuit, the stuffing is executed if necessary in the working or preliminary frame phase conversion circuit, and the frame of the low speed signal of the first output signal is transmitted. An uninterruptible transmission line that switches the selection after matching the phase and the frame phase of the low-speed signal of the second output signal Toggles way. 2. N (where N is multiplexed into a high-speed signal)
Is a positive integer) and simultaneously transmits the high-speed signal in a multiplexed format in which the frame phase of the low-speed signal is indicated by the pointer, and the receiving side converts the pointer value of the reception signal of the current transmission path. In the system, one of the first output signal of the working frame phase conversion circuit and the second output signal of the protection frame phase conversion circuit that converts the pointer value of the reception signal of the protection transmission line is selected. The circuit performs stuffing in the spare frame phase converter, if necessary, by sending information about the frame phase to the spare frame phase converter to convert the frame phase of the slow signal of the second output signal to the slow speed of the first output signal. After matching the frame phase of the signal,
A method for switching transmission paths without interruption for switching the selection. 3. N (where N is multiplexed into a high-speed signal)
Is a positive integer) and simultaneously transmits the high-speed signal in a multiplexed format in which the frame phase of the low-speed signal is indicated by the pointer, and the receiving side converts the pointer value of the reception signal of the current transmission path. In the system for selecting one of the first output signal of the working frame phase conversion circuit and the second output signal of the protection frame phase conversion circuit for converting the pointer value of the reception signal of the protection transmission line, the protection frame phase conversion The circuit performs stuffing in the active frame phase converter, if necessary, by sending information about the frame phase to the active frame phase converter to convert the frame phase of the slow signal of the first output signal to the slow speed of the second output signal. After matching the frame phase of the signal,
A method for switching transmission paths without interruption for switching the selection. 4. N (where N
Is a positive integer) and simultaneously transmits the high-speed signal in a multiplexed format in which the frame phase of the low-speed signal is indicated by the pointer, and the receiving side converts the pointer value of the reception signal of the current transmission path. A first output signal in a system for selecting one from a first output signal of a working frame phase conversion circuit and a second output signal of a protection frame phase conversion circuit for converting a pointer value of a reception signal of a protection transmission line If the frame phase of the low-speed signal in the second output signal and the frame phase of the low-speed signal in the second output signal are different, the stuff is forcibly performed in the working or backup frame phase conversion circuit to A non-instantaneous-interruption-transmission-path switching method in which the selection is switched after the frame phase of the low-speed signal and the frame phase of the low-speed signal of the second output signal are matched. 5. N (where N
Is a positive integer) and simultaneously transmits the high-speed signal in a multiplexed format in which the frame phase of the low-speed signal is indicated by the pointer, and the receiving side converts the pointer value of the reception signal of the current transmission path. A first output signal in a system for selecting one from a first output signal of a working frame phase conversion circuit and a second output signal of a protection frame phase conversion circuit for converting a pointer value of a reception signal of a protection transmission line When the frame phase of the low-speed signal in the inside and the frame phase of the low-speed signal in the second output signal are different, by instructing from the outside, the stuff is forcibly carried out in the working or spare frame phase conversion circuit, Instantaneous switching of the selection is performed after matching the frame phase of the low speed signal in the first output signal and the frame phase of the low speed signal in the second output signal. Transmission line switching method. 6. The information relating to the frame phase according to claim 1, 2 or 3 is a frame phase of the high speed signal written in a memory in the frame phase conversion circuit according to an input side clock. A non-instantaneous-interruption-transmission-path switching method, characterized in that the third signal shown is a signal read in accordance with a clock on the output side. 7. The low-speed signal in the high-speed signal according to claim 1, wherein the information on the frame phase is written in a memory in the frame phase conversion circuit in accordance with an input-side clock. Is a signal read out according to a clock on the output side, which is a fourth signal indicating the frame phase of 1. 8. The information relating to the frame phase according to claim 1, 2 or 3, wherein the frame phase of the low speed signal in the high speed signal at the output side of the frame phase conversion circuit is the fifth. A non-interruption transmission line switching method characterized by being a signal of. 9. The information relating to the frame phase according to claim 1, 2 or 3, wherein the frame phase of the high speed signal on the input side and the frame phase of the high speed signal on the output side of the frame phase conversion circuit. The method for switching transmission paths without interruption is characterized in that 10. The information relating to the frame phase according to claim 1, 2 or 3, wherein the frame phase of the high speed signal on the input side of the frame phase conversion circuit and the low speed of the high speed signal on the output side. A method for switching a transmission line without interruption, which is characterized by a difference from a frame phase of a signal. 11. The information relating to the frame phase according to claim 1, 2 or 3, wherein the frame phase of the low speed signal in the high speed signal on the input side of the frame phase conversion circuit and the high speed on the output side of the frame phase conversion circuit. A method for switching a transmission line without interruption characterized in that the difference is from the frame phase of a low-speed signal in the signal. 12. The information relating to the frame phase according to claim 1, 2 or 3, wherein the frame phase of the low speed signal in the high speed signal on the input side of the frame phase conversion circuit and the high speed on the output side of the frame phase conversion circuit. A method for switching a transmission line without interruption characterized in that it is a difference from a frame phase of a signal. 13. The information on the frame phase according to claim 1, 2 or 3, wherein the frame phase conversion is performed in order to carry out the stuffing simultaneously by the active frame phase conversion circuit and the spare frame phase conversion circuit. A non-instantaneous transmission line switching method, which is information that informs that the circuit is ready for stuffing. 14. The information on the frame phase according to claim 1, 2 or 3, wherein the information on the frame phase is used for stuffing the active frame phase conversion circuit and the spare frame phase conversion circuit simultaneously. A non-instantaneous-interruption transmission line switching method, which is a signal for instructing stuff execution from either the conversion circuit or the preliminary frame phase conversion circuit. 15. The non-interruptible transmission line switching according to claim 1, 2 or 3, wherein the information regarding the frame phase is a pointer value of an output frame of the frame phase conversion circuit. Method. 16. The non-interruptible transmission line switching method according to any one of claims 1 to 5, wherein the execution of the staff is a change of a staff execution condition. 17. The method according to claim 16, wherein after the staff execution condition is changed and the staff is executed, when the standby is switched to the current one, the staff execution condition is returned to that before the change. Method of switching transmission line without interruption. 18. The method according to claim 1, wherein there are K (K is a positive integer) number of the active transmission lines and active frame phase conversion circuits, and the auxiliary transmission lines and the auxiliary frame phase conversion circuits are provided. When there are L circuits (L is a positive integer), one pair of working and protection frame phase conversion circuits is selected, and then the output frames of the one pair of working and protection frame phase conversion circuits are matched. A method for switching a transmission line without interruption without interruption. 19. The frame phase conversion according to any one of claims 1 to 18, wherein the frame phase conversion is executed independently of the first mode in which the frame phases of the low-speed signals are made to match in the working frame and the spare frame phase converting circuit. A second mode is provided, and each mode is selected from the outside. 20. The frame phase conversion according to any one of claims 1 to 18, wherein a frame phase conversion is executed independently of the first mode in which the frame phases of the low speed signals are made to match in the working frame and the spare frame phase converting circuit. The second mode is provided, and normally the first mode is operated, and the output frames are matched because the difference between the frame phase of the high-speed signal on the working transmission line and the frame phase of the high-speed signal on the protection transmission line is large. A non-instantaneous-interruption-transmission-path switching method characterized in that it is operated in the second mode only when it is not possible. 21. The high-speed signal processed by the frame phase conversion circuit according to claim 1, wherein the high-speed signal is CCITT Recommendation G.264. 709 is a higher order virtual container (VC-3 or VC-4), the low speed signal is a basic virtual container (VC-1 or VC-2), and the staff is a pointer. A method of switching transmission paths without interruption, which is frequency justification used. 22. The high-speed signal processed by the frame phase conversion circuit according to claim 1, wherein the high-speed signal is CCITT Recommendation G.264. 709, Synchronous Transport Module Level N
(STM-N), the low-speed signal is a higher-order virtual container (VC-3 or VC-4), and the staff is a frequency justification using a pointer, and there is no interruption transmission line switching. Method. 23. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. , A spare frame phase conversion circuit having the same configuration as the working frame phase conversion circuit, means for notifying the spare frame phase conversion circuit of the frame phase of the input side frame from the working frame phase conversion circuit, and the input of the spare frame phase conversion circuit The frame phase of the side frame and the frame of the input side frame of the active frame phase conversion circuit. A stuffing execution decision circuit for deciding stuffing execution by comparing the phase of the quadrature, and a selector for selecting one output from the output from the active frame phase conversion circuit and the output from the spare frame phase conversion circuit. A circuit for switching transmission paths without interruption. 24. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A spare frame phase converting circuit having the same configuration as the working frame phase converting circuit, means for informing the spare frame phase converting circuit from the working frame phase converting circuit of the frame phase of the low speed signal in the output side high speed frame, and the spare frame Frame phase of low-speed signal and high-speed signal in output side of phase converter From the output from the working frame phase conversion circuit and the output from the spare frame phase conversion circuit, the stuff execution determination circuit that determines the stuff execution by comparing the frame phase of the low speed signal in the output side high speed signal of the conversion circuit A non-instantaneous-interruption-transmission-path switching circuit comprising a selector that selects one output. 25. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A spare frame phase conversion circuit having the same configuration as the working frame phase conversion circuit, means for informing the working frame phase conversion circuit of the frame phase of the input side frame from the spare frame phase conversion circuit, and an input to the working frame phase conversion circuit The frame phase of the side frame and the frame of the input side frame of the spare frame phase conversion circuit. A stuffing execution decision circuit for deciding stuffing execution by comparing the phase of the quadrature, and a selector for selecting one output from the output from the active frame phase conversion circuit and the output from the spare frame phase conversion circuit. A circuit for switching transmission paths without interruption. 26. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A spare frame phase converting circuit having the same configuration as the working frame phase converting circuit, means for notifying the working frame phase converting circuit of the working frame phase converting circuit of the frame phase of the low speed signal in the input side high speed signal, and the working frame Frame phase conversion of low speed signal in input side high speed signal of phase converter and preliminary frame phase conversion 1 out of the output from the active frame phase conversion circuit and the stuff execution determination circuit that determines stuff execution by comparing the frame phase of the low speed signal in the high speed signal on the input side of the path A non-instantaneous transmission line switching circuit characterized by comprising a selector for selecting one output. 27. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. , A spare frame phase conversion circuit having the same configuration as the working frame phase conversion circuit, and a difference between the frame phase of the input side frame and the frame phase of the output side frame in the working frame phase conversion circuit is reserved from the working frame phase conversion circuit. Means for informing the frame phase conversion circuit, and in the preliminary frame phase conversion circuit Stuff execution that determines stuff execution by comparing the difference between the frame phase of the output side frame and the frame phase of the output side frame and the difference between the frame phase of the input side frame and the frame phase of the output side frame in the active frame phase conversion circuit A non-instantaneous-interruption-transmission-path switching circuit comprising a decision circuit and a selector that selects one output from the outputs from the active frame phase conversion circuit and the spare frame phase conversion circuit. 28. N (wherein:
(N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether to perform stuffing. , A spare frame phase conversion circuit having the same configuration as that of the active frame phase conversion circuit, and the difference between the frame phase of the input side frame and the frame phase of the output side frame in the spare frame phase conversion circuit Means for notifying the frame phase conversion circuit, and Staff that decides stuff execution by comparing the difference between the frame phase of the output side frame and the frame phase of the output side frame and the difference between the frame phase of the input side frame and the frame phase of the output side frame in the spare frame phase conversion circuit A non-instantaneous-interruption transmission line switching circuit comprising an execution decision circuit and a selector that selects one output from the output from the active frame phase conversion circuit and the output from the backup frame phase conversion circuit. 29. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A first frame phase conversion circuit having the same configuration as the current frame phase conversion circuit, and a first frame notifying the current frame phase conversion circuit to the spare frame phase conversion circuit
Means, second means for informing the working frame phase conversion circuit that the stuff preparation is completed, and working staff for determining stuff execution in the working frame phase conversion circuit by the first means and the second means. Execution decision circuit, preliminary stuff execution decision circuit for deciding stuff execution of the preliminary frame phase conversion circuit from the first means and the second means, output from the current frame phase conversion circuit and output from the preliminary frame phase conversion circuit A non-interruptible transmission line switching circuit characterized by comprising a selector for selecting one output from among the above. 30. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A spare frame phase conversion circuit having the same configuration as that of the active frame phase conversion circuit, a third means for instructing the spare frame phase conversion circuit to perform stuff execution from the active frame phase conversion circuit, and a spare frame by the third means. Preliminary stuff execution decision circuit for deciding stuff execution in the phase conversion circuit, and active frame Uninterrupted transmission line switching circuit, characterized in that it consists of a selector for selecting one output from among the outputs of the output and pre-frame phase conversion circuit from the phase converter. 31. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read frame control circuit for instructing an address when reading a signal from the memory, and a phase comparator for comparing a write address given to the memory with a read address to determine whether or not to perform stuffing. A spare frame phase conversion circuit having the same configuration as the active frame phase conversion circuit, fourth means for instructing the active frame phase conversion circuit to perform stuff execution, and the active frame by the fourth means. Working stuff execution decision circuit for deciding stuff execution in the phase conversion circuit and working frame Uninterrupted transmission line switching circuit, characterized in that it consists of a selector for selecting one output from among the outputs of the output and pre-frame phase conversion circuit from the phase converter. 32. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. , A read control circuit that indicates an address when reading a signal from the memory, and a plurality of write control circuits that determine whether to perform stuffing by comparing a write address and a read address given to the memory and that have different determination conditions. A working frame phase conversion circuit including a phase comparator and a second selector that selects one of the plurality of phase comparators, and a preliminary frame phase conversion circuit having the same configuration as the working frame phase conversion circuit. And whether the output frames of the active frame phase conversion circuit and the backup frame phase conversion circuit match. And a monitoring circuit for instructing the second selector of the spare frame phase conversion circuit to select a phase comparator different from the currently selected phase comparator, and an active frame phase conversion A non-instantaneous-interruption-transmission-path switching circuit, comprising a selector that selects one output from the output from the circuit and the output from the preliminary frame phase conversion circuit. 33. N (wherein:
N is a positive integer) A memory for storing a low speed signal in the high speed signal in a multiplexed format in which a frame phase of the low speed signal is indicated by a pointer, and a write control circuit for instructing an address when writing a signal to the memory. A read control circuit that indicates an address when reading a signal from the memory, and a phase comparator that compares a write address and a read address given to the memory and issues a stuff execution request,
A current frame phase conversion circuit comprising a stuff execution request circuit from the phase comparator and a stuff execution determination circuit for deciding whether or not to execute stuff in response to an external instruction, and a spare having the same configuration as the current frame phase conversion circuit. A frame phase conversion circuit, a pointer display unit for displaying pointers of output frames of the active frame phase conversion circuit and the spare frame conversion circuit, and means for externally instructing the active or spare frame phase conversion circuit to perform stuffing,
A non-instantaneous-interruption-transmission-path switching circuit comprising a selector that selects one output from the output from the active frame phase conversion circuit and the output from the backup frame phase conversion circuit. 34. The high-speed signal processed by the frame phase conversion circuit according to any one of claims 23 to 33, is CCITT Recommendation G.264. 709 is a higher order virtual container (VC-3 or VC-4), and the low speed signal is a basic virtual container (VC-1 or VC-2),
The staff is a frequency-justification non-interruption transmission path switching circuit using a pointer. 35. The high-speed signal processed by the frame phase conversion circuit according to any one of claims 23 to 33, is CCITT recommendation G.264. 709 Synchronous Transport Module Level
N (STM-N), and the low speed signal is a higher order virtual container (VC-3 or VC-4).
The stuff is a frequency justification using a pointer, which is a non-interruptible transmission line switching circuit.