JPH0614340A - Video camera circuit - Google Patents

Abstract

PURPOSE:To provide a video camera circuit capable of omitting a memory to be used for YC separation or horizontal interpolation by providing the circuit with a memory for zooming processing. CONSTITUTION:A memory 1 for storing a CCD output signal is controlled by a memory control circuit 3 to constitute a zooming processing circuit. The circuit 3 generates an enable signal EN to be switched to 'high' in the advancing period of memory reading addresses in each unit period or 'low' in the stopped period of the addresses at the time of horizontal zooming. A YC separation circuit connected to the output terminal of the zooming processing circuit is provided with plural D-FFs 7, 10, 11 respectively having delay time corresponding to the unit time and allowed to execute data updating operation by the enable signal EN and outputs a luminance signal and color difference signals formed by the YC separation circuit to a horizontal interpolating circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera, and more particularly to a video camera circuit which realizes a zoom function by electrical processing.

[0002]

2. Description of the Related Art In order to meet the recent demands for downsizing and weight saving of video cameras, CC circuits are used in video camera circuits.
Digitalization has been studied in which an analog signal obtained from an image pickup device such as D is converted into a digital signal, and then various signal processes such as a zoom process and a color signal separation process are performed.

FIG. 7 shows a conventional circuit configuration for performing YC separation and horizontal zoom processing in such a digital video camera circuit. CCD output is A / D
Digital imaging signal obtained by conversion (CCD output signal)
Is separated into a luminance signal and a chrominance signal through a YC separation circuit (37), and then both signals are separated into a Y process circuit (38) and a C signal, respectively.
It is sent to the horizontal zoom processing circuit via the process circuit (39).

The horizontal zoom processing circuit is provided with memories (40) and (41) for the luminance signal and the color difference signal, respectively, and the memory control circuit (42) controls writing and reading to and from the both memories to expand the horizontal direction. The generated luminance signal and color difference signal are created. Both signals are horizontal interpolation circuit
The signal is sent to (43) and subjected to interpolation processing by weighted averaging, and then output as a Y signal and a C signal that form a zoom image to the subsequent circuit.

FIG. 8 conceptually shows the circuit operation when the horizontal zoom ratio is set to 2 times, and a predetermined area (zoom angle of view) to be subjected to zoom processing during one horizontal scanning period H. The CCD output signal is temporarily stored in the memory, and then the angle-of-view signal is read from the memory at a cycle twice the unit cycle of the clock CLK at the time of writing.

Although the video camera circuit is also equipped with a circuit for performing vertical interpolation associated with zoom processing,
Illustration and description are omitted here.

By the way, in an image pickup device generally composed of a CCD, a well-known complementary color filter having a mosaic arrangement as shown in FIG. 6A is arranged on the light receiving surface side thereof, and FIG. As schematically shown in (c), an array of odd-numbered field imaging signals is created by adding the light receiving outputs of vertically adjacent two lines, and the light receiving outputs of two lines deviated from the above by one line. By adding, an array of image pickup signals of even fields is created.

Further, in the YC separation, based on the array of the image pickup signals of each field, the array of low-frequency luminance signals schematically shown in FIG. 6 (d) and the color difference signal schematically shown in FIG. 6 (e). An array of is created. That is, for each pixel, by summing up with the adjacent pixels on the same line,
The low-frequency luminance signal (2R + 3G + 2B) in (d) is created.
Also, for each pixel, the difference between adjacent pixels on the same line is calculated to obtain a pair of color difference signals of FIG.
Either (2B-G) or (2R-G) is created.
These color difference signals will appear alternately for each line. Hereinafter, one color difference signal (2B-G) is abbreviated as Cb, and the other color difference signal (2R-G) is abbreviated as Cr. The signs of these color difference signals are alternately inverted for each pixel on the same line.

In the case of an image pickup apparatus having a complementary color filter, the two color difference signals Cr and Cb are 1 as shown in FIG.
Since they appear alternately every line (one horizontal scanning line), in order to obtain two color difference signals Cr and Cb for each line, it is necessary to perform a synchronization process using signals of at least upper and lower three lines. That is, when the color difference signal on a certain line is, for example, Cb, the color difference signal Cr does not exist on that line, and therefore the color difference signals C on the lines above and below that line.
By taking the average of r, the color difference signal C of the line
That is, r is artificially generated.

Because of this synchronization processing, the conventional video camera circuit is also equipped with two line memories (not shown) in the YC separation circuit (37) shown in FIG. Digital imaging signals for 3 lines are obtained.

[0011]

As described above, in the conventional video camera circuit, since the horizontal zoom processing is performed on each of the luminance signal and the color difference signal after YC separation, a memory other than the memory for YC separation is used. For horizontal zoom, two memories are required for the luminance signal and the color difference signal.

Therefore, when the video camera circuit is constituted by one or a plurality of integrated circuits, the area ratio occupied by the plurality of memories in one integrated circuit becomes extremely large, which causes a problem that the circuit becomes large. . In addition, there is a problem that power consumption becomes large because a plurality of memories are driven.

An object of the present invention is to provide a video camera circuit in which the memory for YC separation and the memory for horizontal interpolation can be omitted if one memory is provided for zoom processing, whereby the circuit can be downsized and the power consumption can be reduced. Is to reduce the

[0014]

As shown in FIG. 1, the video camera circuit according to the present invention has at least one horizontal scanning period.
A memory (1) capable of storing a CCD output signal of (1H) is provided, and writing and reading with respect to the memory (1) are controlled by a memory control circuit (3). Also, the memory control circuit
(3) generates an enable signal EN that switches to the first state while the read address for the memory (1) is advanced in a unit cycle with the horizontal zoom processing and to the second state when the read address is stopped. is there.

A plurality of unit delay elements each having a delay time corresponding to the unit cycle and permitting the data update operation by the enable signal in the first state are connected in series to the output terminal of the memory. It Then, each output terminal of the plurality of unit delay elements is subjected to a predetermined arithmetic processing including a weighted average in the time axis direction with respect to these output signals to obtain a luminance signal or a color difference signal to form a zoom image. A horizontal interpolation processing circuit for output is connected.

In the video camera circuit according to the present invention, the memory control circuit (3) reads a signal from the memory (1) in a unit cycle for a certain period from the start of reading each horizontal scanning line from the memory, and A timing control circuit (30) for forcibly setting the enable signal EN to the first state is provided.

[0017]

Operation: The memory (1) is controlled by the memory control circuit (3).
A digital image pickup signal of a predetermined line to be zoomed in is read out at a timing according to the zoom magnification as shown in FIG. 8 to generate a discrete image pickup signal stretched in the horizontal direction, and a plurality of units in the subsequent stage are generated. The signals are sequentially input to the delay element.

Here, the timing of the memory output signal to the unit delay element is mixed with the case where the interval of the unit cycle is set and the case where the time interval is set to an integral multiple of the unit cycle (see FIG. 3). . Therefore, in the latter case, if each unit delay element is always operated in a unit cycle, regardless of the signal output timing from the memory, a plurality of output signals from each unit delay element will cause a plurality of adjacent output signals on the imaging device. It is not a signal for a pixel, but two signals for the same pixel are output.

However, in the case of an image pickup device having a complementary color filter, signals for a plurality of pixels adjacent in the horizontal direction on the image pickup device are always provided for YC separation as shown in FIGS. 6B and 6C. Will be needed. Therefore, in this way, in order to always obtain signals for a plurality of adjacent pixels on the imaging device,
The enable signal E controls the operation of each unit delay element.
N.

That is, the enable signal EN output from the memory control circuit (3) to each unit delay element is set to the first state ("high") while the read address for the memory (1) is advanced in a unit cycle. Then, the data update operation of each unit delay element is permitted. Therefore, the plurality of signals output from each terminal delay element during this period are signals having unit cycle time intervals, and are signals of a plurality of pixels continuous in the horizontal direction on the imaging device.

On the other hand, while the read address for the memory (1) is stopped, the enable signal EN is in the second state.
Since it is set to (“low”) and the data update operation of each unit delay element is interrupted, the output signal of each unit delay element during this period does not change. Therefore, even in this period, the plurality of signals output from each unit delay element are signals having unit cycle time intervals, and are signals of a plurality of pixels continuous in the horizontal direction on the imaging device. .

As a result, the plurality of signals output from each unit delay element are signals of a plurality of pixels which are always continuous in the horizontal direction on the image pickup device, that is, FIG. 6B or irrespective of the zoom magnification.
The image pickup signals having the arrangement of (c) are provided, and the luminance signal Y and the color difference signal C can be calculated by the horizontal interpolation processing circuit based on these signals.

When the memory control circuit (3) is equipped with the timing control circuit (30), the enable signal EN is forcibly set to the first level for a certain period from the start of reading each horizontal scanning line to the memory (1). It is set to the state (“high”), and during this period, regardless of the zoom magnification, signals are rapidly supplied to the unit delay elements of the multiple stages in a unit cycle, and normal signals are set to all unit delay elements. The time required for

As a result, even when the number of stages of the unit delay elements is large and the zoom magnification is high, the period required for the signal setting is shortened, and it falls within the horizontal blanking period on the left side of the screen, and an abnormal image is generated. Is avoided.

[0025]

According to the video camera circuit of the present invention, since the zoom processing is performed before the YC separation and the horizontal interpolation, it suffices to provide one memory for the zoom processing. The memory for horizontal interpolation can be omitted. As a result, downsizing of the circuit and reduction of power consumption are realized.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of a zoom processing circuit, a YC separation circuit, and a horizontal interpolation circuit which form the video camera circuit of the present invention, and FIG. 3 shows the operation of these circuits.

As shown in FIG. 1, the zoom processing circuit is equipped with a memory (1) capable of storing a CCD output signal of one field, and the memory (1) is controlled by the memory control circuit (3) for writing and reading. Has been done. And the selection circuit (2)
When zoom processing is not performed by switching
Only when the CD output signal is directly sent to the YC separation circuit and the zoom process is performed, the CCD output signal of the zoom angle of view is read from the memory (1) and output to the YC separation circuit.

Then, the memory control circuit (3) controls the CC of a predetermined angle of view from the memory (1) at an appropriate timing according to the zoom coefficient α (1 / zoom magnification) supplied from the external circuit.
The D output signal is read out, and the discrete signal expanded in the horizontal direction by this is sent to the YC separation circuit via the selection circuit (2).

Further, the memory control circuit (3) is "high" when the memory read address is advanced in a unit cycle at the same time as the memory control, that is, when a signal of a new pixel is output from the memory (1). Is stopped, that is, when the signals of the same pixel are continuously output, the enable signal EN that switches to "low" is generated. Further, the memory control circuit (3) simultaneously creates an interpolation coefficient K necessary for horizontal interpolation processing and outputs it to the horizontal interpolation circuit.

FIG. 2 shows a specific structure of the memory control circuit (3), and FIGS. 4 and 5 show the operation of the memory control circuit (3) at the time of 2 × zoom. As the input signal, the zoom coefficient α, a horizontal address HAD given to each pixel of one line of the CCD, an address (start AD) of a zoom processing start point in the horizontal address, and a clock of a unit cycle The signal CLK is input. still,
As shown in FIG. 4, the horizontal address HAD is reset at the start of the horizontal scanning period at the rising edge of the horizontal drive signal HD and is counted up every clock of the clock signal CLK.

As shown in FIG. 2, in the memory control circuit (3), an adder (31) and a D-type flip-flop (DF) for cyclically adding the zoom coefficient α to generate a carry signal (carry).
A closed loop circuit composed of F) and (34) is formed, and the carry is output to the subsequent circuit as an enable signal EN through the OR circuit (32). Also, the enable signal EN is a counter
The signal is supplied to (35) and the read address counter (35) is counted up while the signal is "high".

The horizontal address HAD, the start address and the clock signal CLK are input to the timing control circuit (30), whereby the first control signal EN shown in FIG.
1, the second control signal EN2, and the reset signal RST are generated.

The reset signal RST, which becomes "high" at the start of the horizontal effective period, is sent to the read address counter (35) and the write address counter (36) in FIG. 2 to reset these counters. To do.

The first control signal EN1 becomes "high" during the first four clock periods of the horizontal effective period, and the signal becomes O.
By being supplied to the R circuit (32), the counter (35) is forcibly counted up during the period of the first four clocks. Also, the first control signal EN1 is applied to the switching circuit (33).
Is input to the switching circuit (33) while the signal is "high".
Is switched to the start address side, and the fractional part of the start address that is the initial value of the horizontal interpolation coefficient is selected and output. After the first control signal EN1 becomes "low", the switching circuit (33) is switched to the adder (31) side, and the addition result of the adder (31) is output to the subsequent circuit as a horizontal interpolation coefficient. or,
The second control signal EN2 becomes "high" after the horizontal address HAD becomes the start address, and counts up the write address counter (36).

As a result, the write address counter (36)
As shown in FIGS. 4 and 5, the memory that is sequentially counted up in unit cycles after the initial value “000” when the second control signal EN1 becomes “high” corresponding to the start address. The write address (WR address) is output.

On the other hand, from the read address counter (35), as shown in FIGS. 4 and 5, the starting point of the horizontal effective period is set to the initial value "000", and thereafter, only when the enable signal EN is "high". When the enable signal EN is "low" while being sequentially counted up in a unit cycle,
The memory read address (RD address) holding the previous value will be output.

By the above operation, only the signals after the start point of the zoom angle of view are written in the memory (1), and then only the signals necessary for the zoom processing are sequentially output from the memory (1) at time intervals corresponding to the zoom magnification. It becomes possible to read out, and thereby, the zoom process according to the zoom magnification is performed.

In the YC separation circuit shown in FIG. 1, two 1H delay lines (4) and (5) to which the CCD output signal read from the zoom processing circuit is input are arranged in series, and the input of both delay lines is input. From the output terminal, signals of three lines L0, L1 and L2 which are vertically adjacent to each other on one screen are obtained in parallel, and the signals are respectively input to D-FF (6) (7) (8). .

Regarding the intermediate line L1, the first delay signal output from the D-FF (7) and the second delay signal obtained by delaying the signal by one pixel (1 clock) by the D-FF (10). And a third delay signal obtained by delaying the signal by one pixel by the D-FF (11) are respectively supplied to the averaging circuit (12), and the first delay signal is ¼ and the second delay signal is delayed. 1/2 for signal, third
A weighted average obtained by multiplying the delayed signal by a coefficient of 1/4 is calculated. In a CCD having a complementary color filter, the weighted average value becomes the luminance signal.

Further, the signal output from the D-FF (7),
The signal obtained by delaying the signal by one pixel by the D-FF (13) is supplied to the subtractor (15) via the switching circuit (14), and the difference between the two signals is calculated. As a result, the color difference signal Cb or Cr shown in FIG. 6E is created. At this time, the switching circuit (14)
Switches the input / output relation based on the enable signal from the memory control circuit (3) so that the subtraction result of the subtractor (15), that is, the color difference signals Cb and Cr always have positive values.

On the other hand, for the upper and lower lines L0 and L2, the output of D-FF (6) and the output of D-FF (8) are added by an adder.
The signal obtained by averaging at (9) and the signal obtained by delaying the signal by one pixel at the D-FF (16) are supplied to the subtractor (18) via the switching circuit (17). , By this
The color difference signal Cr or Cb shown in (e) is created. At this time, the switching circuit (14) performs input / output based on the enable signal from the memory control circuit (3) so that the subtraction result by the subtractor (15), that is, the color difference signals Cr and Cb always have positive values. Switch. The color difference signal is a signal on the line L1 that is pseudo-created based on the signals on the lines L0 and L1.

Here, 2 obtained from each subtractor (15) (18)
One of the color difference signals is Cr and the other is Cb, and these are switched for each line. Therefore, the color difference signal Cr is always output from the one selection circuit (19) by the selection circuits (19) and (20). , The other selection circuit (20) always outputs the color difference signal Cb.
, The input / output relationship is switched by the line feed signal.

The horizontal interpolation circuit applies a weighted average to the luminance signal and the color difference signal obtained from the YC separation circuit according to the interpolation coefficient K from the memory control circuit (3), and thereby a luminance signal to form a zoom image. Y and two color difference signals C
r, Cb are generated, and for each of these three signals, a weighted average circuit (D-FF (21) (23) (25) for delaying one pixel and a weighted average circuit for performing weighted average by the interpolation coefficient K ( 22) (24) (26)
It is equipped with

The three weighted average outputs from the horizontal interpolation circuit are delayed by one pixel by the D-FFs (27), (28) and (29), respectively, and then the luminance signal Y and the color difference signal Cr are supplied to the subsequent circuit. , Cb are output.

In the YC separation circuit and the horizontal interpolation circuit of FIG. 1, each D-FF forming the unit delay element has an input terminal for the enable signal EN, and when the enable signal is "high". , Each D-FF receives new data, outputs the data after a delay time of one pixel. On the other hand, when the enable signal EN is "low", the data updating operation of the D-FF is stopped and the immediately previous output data is continuously output.

Therefore, as shown in FIG. 3, D-FF (6) (7)
Output of (8) and D-FF (10) (13) (16) and D-FF (1
The output of 1) is always a signal of three pixels that are horizontally adjacent to each other on the CCD regardless of the zoom magnification. In the case of an image pickup device having a complementary color filter, signals for a plurality of horizontally adjacent pixels on the CCD are always required for YC separation. Therefore, each D-FF is controlled by the enable signal as described above. By doing so, the calculation of the luminance signal by the averaging circuit (12) and the calculation of the color difference signal by the subtracters (15) and (18) are normally performed.

Also, the input and output of the D-FFs (21) (23) (25) are always signals of pixels adjacent in the horizontal direction on the CCD, and the weighted average circuits (22) (24) (26). The interpolation process by becomes normal.

By the way, in the above embodiment, as shown in FIG. 5, the first control signal EN1 is made to be "high" only during the first four clock periods of the horizontal effective period, and the four clock periods are set by the signal. The enable signal EN is forcibly set to "high", the memory read address is advanced in a unit cycle regardless of the presence / absence of zoom processing, and the YC
All the D-FFs of the separation circuit and the horizontal interpolation circuit are operated in a unit cycle.

If this process is omitted, the following problems will occur when the zoom magnification is high. For example, when the zoom magnification is 10 times, the YC separation circuit of FIG. 1 is equipped with three stages of D-FFs (7) (10) (11) for generating a luminance signal. Data is sequentially transmitted to the FF from the upstream side to the downstream side in a cycle of 10 clocks, so that 21 clocks (= 10 clocks × 10 clocks ×) until the normal CCD output signal reaches the most downstream D-FF. (2 + 1 clock) period is required. Therefore, during the period from the start of the horizontal effective period of the zoom screen to 20 clocks, each D-FF
Output becomes an abnormal value, and a normal luminance signal cannot be obtained from the averaging circuit (12).

When a zoom image is generated on the basis of such an abnormal luminance signal, the abnormal signal in the 20 clock period extends from the area of the horizontal blanking period on the left side of the screen to the image display area, and then on the left side of the screen. The image part may be abnormal. This problem will occur even when the zoom magnification is low, as the number of D-FF stages increases.

Therefore, in the present embodiment, a total of 4 including the D-FF (21) arranged in the subsequent stage of the YC separation circuit of FIG.
Taking into account the D-FF of the stage, by sending signals for four pixels to the YC separation circuit in the clock cycle during the first four clock periods of the horizontal effective period, the period of occurrence of the abnormal signal is the same as that during non-zoom. It is contained within 3 clocks. Abnormal signals in the first three clock periods are hidden in the horizontal blanking period on the left side of the screen and do not appear on the display screen.
As a result, a good image can be obtained even at high magnification.

As described above, according to the video camera circuit of the present invention, the CCD output signal before YC separation is written / read to / from the memory (1), so that the horizontal zoom can be performed by a single memory. Can be realized.
Further, by controlling the operation of the D-FF by the enable signal EN, it is possible to obtain a good zoom image even at a high magnification.

The above description of the embodiments is for explaining the present invention, and should not be construed as limiting the invention described in the claims or limiting the scope. The configuration of each part of the present invention is not limited to the above-mentioned embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims.

For example, in the YC separation circuit of FIG. 1, D
The number of -FF stages can be further increased. In this case, the period for setting the first control signal EN1 to "high" may be changed according to the number of D-FF stages. In the horizontal interpolation circuit, the D-FFs (23) and (25) and the weighted average circuits (24) and (26) also perform horizontal interpolation on the color difference signals, but these circuits can be omitted. As a result, the deterioration of image quality does not become a problem.

Furthermore, the memory (1) of the zoom processing circuit is
When only the horizontal zoom processing is intended, the line memory can be used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video camera circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a memory control circuit.

FIG. 3 is a timing chart showing the operation of the circuit shown in FIG.

FIG. 4 is a timing chart showing the operation of the circuit shown in FIG.

FIG. 5 is a timing chart showing the circuit operation of FIG. 2 with the time axis enlarged.

FIG. 6 is a table illustrating the principle of YC separation for a CCD having a complementary color filter.

FIG. 7 is a block diagram showing a configuration of a conventional video camera circuit.

FIG. 8 is a timing chart illustrating the principle of horizontal zoom processing.

[Explanation of symbols]

 (1) Memory (3) Memory control circuit (7) D-FF (10) D-FF (11) D-FF (12) Addition averaging circuit

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[Procedure amendment]

[Submission date] October 23, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

An object of the present invention, only Ru comprises one memory for zooming to provide a video camera circuitry horizontal zoom can be realized, thereby by made compact, reduced power consumption of the circuit is there.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025]

According to the video camera circuit according to the present invention, YC separation, because it was decided to perform the zoom processing prior to horizontal interpolation, if Sonaere one memory for zoom processing Kaku, conventional The two memories for the horizontal zoom processing can be omitted. As a result, downsizing of the circuit and reduction of power consumption are realized.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location H04N 9/78 Z 8626-5C (72) Inventor Masao Takuma 2-chome, Keihanhondori, Moriguchi-shi, Osaka Address Sanyo Denki Co., Ltd. (72) Inventor Seizou Kawakami 2-18, Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Co., Ltd.

Claims (2)

[Claims] 1. An image pickup output from an image pickup device having a complementary color filter is converted into a digital signal and stored in a memory, and a horizontal zoom is performed on the digital signal read from the memory corresponding to a screen area to be zoomed. In a video camera that performs processing to generate a luminance signal and a color difference signal of each horizontal scanning line that should form a zoom screen, a digital signal in pixel units that is to be the basis of horizontal interpolation is generated along with the horizontal zoom processing. A horizontal read address for sequentially reading from the memory is generated, and a period in which the read address is advanced in a unit cycle is in the first state,
A memory control circuit that generates an enable signal EN that switches to a second state during a stopped period is connected in series to an output terminal of the memory, has a delay time according to the unit cycle, and A plurality of unit delay elements whose data update operation is permitted by the enable signal in one state, and a predetermined arithmetic process including a weighted average in the time axis direction with respect to signals obtained from output terminals of the plurality of unit delay elements And a horizontal interpolation processing circuit for outputting the luminance signal or the color difference signal. 2. A timing for the memory control circuit to read a signal from the memory in a unit cycle for a certain period from the start of reading each horizontal scanning line to the memory and to forcefully set the enable signal EN to the first state. The video camera circuit of claim 1, comprising a control circuit.