JPH06149696A - Ipl system for multiprocessor system - Google Patents

Abstract

(57) [Summary] [Object] The present invention is a multiprocessor in which a plurality of processors are connected by a communication bus, and a unit for reading the IPL data of the IPL data device and a unit for transmitting the IPL data to each processor are provided in a specific processor. Processor system IP
It is an object of the L system to reduce the time required for system IPL in a multiprocessor system connected by a plurality of communication buses. A specific processor is provided with an IPL data storage device, and each processor of a multiprocessor system in which the specific processor and each other processor are mutually connected by a plurality of communication paths is provided with a communication path management means and a communication path switching means. The communication path management means manages the current communication path with each processor using the status management table, and the system IPL
When performing the above, the active communication path switching means is controlled so that the active communication path is distributed to each processor, and communication is performed with each of the other processors to switch the active communication path on both sides.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of processors, which are connected to each other by a communication bus, and which are used in
The present invention relates to an IPL method of a multiprocessor system in which a specific processor is provided with means for reading L data and transmitting IPL data to each processor.

[0002] A system configured by connecting a plurality of processors to each other via a communication bus is used for information and communication (exchange, etc.).
Known in the field. In such a multiprocessor system, the IPL is individually applied to each processor.
(Initial program loading) data is prepared and I
It is necessary to perform PL. However, since it takes time to complete the IPL for all of the multiprocessors, its improvement is desired.

[0003]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional multiprocessor system. 7, 70A to 70C are processors, 71 is an IPL data storage device provided only in the processor 70A, 72A to 72C are ring bus adapters connected to the communication bus # 0, and 73A to 73C.
Is a ring bus adapter connected to communication bus # 1, 74
Is a 0-type ring-type communication bus (indicated by bus # 0), 75
Is a 1-system (# 1) ring-type communication bus (indicated by bus # 1).

Normally, the processors 70A to 70C communicate with each other by using one of the two bus communication # 0 and communication bus # 1 as an active communication path and the other as a standby (standby) communication path. Send and receive communication data on the communication path.

In the conventional system, when the entire multiprocessor system is IPL (referred to as system IPL), if the working communication path is the communication bus # 0 and the backup communication path is the communication bus # 1, the IPL data storage device 71 outputs the IP.
The L data is read by the processor 70A and executed by using the communication bus # 0 which is the working communication path. That is, the IPL data is transferred to the processor 7 via the communication bus # 0.
0A, the ring bus adapter 72A, the communication bus # 0 and the ring bus adapter 72B are transferred to the processor 70B for IPL, and then the IPL data is sent to the processor 70C through the same communication bus # 0. IPL is performed.

[0006]

In the conventional IPL method of the multiprocessor system described above, the system IPL is used.
The entire system to transfer IPL data for each processor sequentially using the current communication path to
There is a problem that it takes time to perform L.

It is an object of the present invention to provide a multiprocessor IPL system capable of shortening the time required for IPL in a multiprocessor system connected by a plurality of communication buses.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a specific processor, 2 is an IPL data storage device provided in the specific processor,
3 is a plurality of processors # 0, # 1 ... #m (only a part of # 0 and # 1 is shown in the figure) other than the specific processor,
4 is a plurality of communication buses # 0 to #n (# in the figure
Only 0 and # 1 show the internal structure, and others are not shown).

In the specific processor 1, 1a is a communication bus access means, 1b is a communication path management means, 10 is a status management table of interprocessor communication paths, 1c is a current communication path switching means, and 1d is an average number of current communication paths. Means, 1e is I
PL data reading means 1f is an IPL data transmission means. Further, in each of the plurality of processors 3, 3a is a communication bus access means, 3b is a communication path management means, 30 is a status management table of inter-processor communication paths, 3c is an active communication path switching means, and 3d is an IPL data receiving means. .

According to the present invention, when IPL data is transmitted from a specific processor to a plurality of multiprocessors, a plurality of communication buses connecting the processors are used to simultaneously switch the active communication paths in accordance with the communication partner. The IPL data is transferred to a plurality of processors.

[0011]

The communication path management means 3b of each processor uses which communication bus among the plurality of communication buses 4 (# 0 to #n) in the status management table 30 of the inter-processor communication path when the processor is initialized. It is used as a path and set as a standby communication bus.

Similarly for the specific processor, at the time of processor initialization, the communication path management means 1b determines which of the communication buses 4 with the respective processors 3 should be the active communication path and the standby communication path. It is set in the communication path status management table 10. Normally, one communication bus is selected as the working communication path between the processors, and all other communication buses are set as standby buses.

When the specific processor 1 is driven to perform the system IPL, the working communication path switching means 1c is driven. The active communication path switching means 1c is the state management table 1
With reference to 0, control is performed to switch the active communication bus corresponding to each processor 3 so that the plurality of communication buses 4-0 to 4-n are distributed as much as possible as a communication path with each other processor 3. To do. That is, the processor 3 (# 0) uses the communication bus 4 (# 0) as the active path, the processor (# 1) uses the communication bus 4 (# 1) as the active communication path, and so on. Switch.

This switching is performed between each of the partner processors 3 when the working communication bus set in the state management table 10 is switched to the spare (including the case where the spare communication bus is switched to the working). Communication is sent and received, and the contents of the state management table 10 are changed according to the switching.

Each partner processor 3 controls the communication for switching the communication bus from the specific processor in the active communication path switching means 3c, and changes the contents of the state management table 30 in response to the switching.

Working communication path switching means 1 of the specific processor 1
c instructs the active communication path number averaging means 1d to determine whether the number of processors 3 using the individual communication buses 4 (# 0 to #n) as active communication paths is substantially the same.
If it is found by the judgment of the working communication number averaging means 1d that it is not averaged, the working communication path switching means 1c further switches so as to perform averaging.

When the active communication path for IPL is set between the specific processor 1 and each of the other plurality of processors 3 including the switching operation, the specific processor 1 refers to the state management table 10. , The communication bus access means 1a corresponding to each communication bus set as the active communication path of each processor 3 (a plurality of communication bus access means is provided corresponding to a plurality of communication buses) is activated, and the IPL data reading means 1e is The IPL data corresponding to each processor is read from the IPL data storage device 2 and is transmitted from the IPL data transmitting means 1f to each processor 3 via each active communication path. That is, the IPL data for each of the plurality of processors 3 are simultaneously transmitted in parallel, and high speed can be realized. (However, it is necessary to provide the communication bus access means 1a and the IPL data transmission means 1f in a number corresponding to the number of each communication bus).

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 is a structural example of an exchange system in which the present invention is implemented. In FIG. 2, 20 is an exchange system composed of multiprocessors, 21 is a master processor (indicated by MPR) for managing other processors, and 22-0 to 22.
-3 is a processor for performing call processing (displayed in CPR), 23
-0 to 23-3 are corresponding processors 22-
Digital switch module (displayed by DSM) that controls the communication path, controlled by 0 to 22-3, 2
4 is a 0-system (# 0) ring bus (common bus), 25 is 1
The system (# 1) ring bus, 26 is a ring bus adapter connected to the 0 system (# 0) ring bus 24, and 27 is a ring bus adapter connected to the 1 system (# 1) ring bus.

This system is an example in which two systems of a ring bus # 0 (24) and a ring bus # 1 (25) are provided as communication buses, and a master processor (hereinafter referred to as MPR).
21) holds the IPL data in an internal hard disk (not shown), and the MPR is used when the system is started up.
21 to each processor (hereinafter referred to as CPR) 22-
The individual IPL data for 0 to 22-3 are transferred by the ring bus selected according to the present invention through the corresponding ring bus adapter 26 or 27, and the IPL data is transferred.
Is executed.

Each processor (MPR, CPR) determines whether the communication path between the processors can be used or not according to the access route of each ring bus # 0, # 1 and the state of the ring bus adapter at the time of initialization. Which communication path between the processors of the
It is determined by communicating with R21 and is set in the state management table of each inter-processor communication path.

When the MPR 21 executes the IPL, it is 2
By changing the state of one ring bus 24, 25 set before IPL (only one ring bus is in use, the other is in standby), two ring buses 24, 25 are in use for each processor. The active communication path is switched to average and allocate each as a system.

In this case, the MPR 21 executes the processing shown in FIG. 3 with each CPR that needs to switch the state set as the working communication path in each CPR. Figure 3
Is a processing flow for switching the active communication path, FIG. 4 is an explanatory diagram of a communication path state management table, and FIG. 5 is an explanatory diagram of communication data between processors.

In this description, it is assumed that the ring bus 24 of the 0 system (# 0) is set as the current communication path and the ring bus 25 of the 1 system is set as the standby, while the communication path between the MPR and each CPR is set in advance. To do.

The state management table of the inter-processor communication path will be described with reference to FIG. The format is shown in A. Is set, state information S0 corresponding to the ring bus # 0 is set, and state information S1 corresponding to the ring bus # 1 is set as a communication path with the partner processor. These S0 and S1 are "1" for the current use, "2" for the standby,
When it is not usable, "3" is set, and in the case of two ring buses S0 and S1, one of them is set to "1" (active).

B. From MPR21 to each CPR22-0
22-3 show examples of setting of the state management table of the inter-processor communication paths for the above items. In this case, the ring bus # 0 is set as the active communication path between the MPR and each CPR, and the ring bus # 1 is set as the standby communication path in the initialization state.

In FIG. 3, the MPR 21 has one CP.
Communication path with R Working communication path switching factor (IPL
Is detected, or failure detection of the active communication path) is detected (S1 in FIG. 3), it is determined whether or not there is a standby path of the active communication path required for switching (S2).

If there is no standby communication path (unusable due to a failure or the like), a switching refusal determination output is generated (at the same step S).
3). If there is a standby communication path, an active communication path switching instruction order (its configuration will be described later) is sent (S
4). When this order is received by the other side (active communication path switching instruction receiving side) (at step S5), it is judged whether or not there is a standby communication path of the active communication path that needs to be switched (at step S6). Confirm order (its structure will be described later)
To the confirmation order (S7), and if there is a switchable order, the confirmation order is edited (S8). After that, a switching confirmation order (including the case of rejection) is sent to the MPR 21 (at step S9), and if switching is possible, switching is performed (at step S10).

After sending the working communication path switching instruction, the MPR 21 waits for a confirmation order for the instructed order (at step S11), and if it exceeds a certain time, processes it as a failure of working communication path switching (NG) at the same time (at step S11).
12). Upon receiving the switching confirmation order (at step S13),
The contents are identified and it is judged whether switching of the partner processor is possible or not (S14 of the same).
The same process as 11 (at step S15), and if possible, the active communication path switching is identified as permission (at step S16), and MPR
Switching of the active communication path in 21 (rewriting the status management table of the communication path between the other processors) is executed (at step S17).

Communication data between processors will be described with reference to FIG. A of FIG. Indicates the format of communication data between processors, and as shown in the figure, PA, SD ...
A data section is provided after each control signal such as SPA, and the working communication path switching instruction order and the working communication path switching confirming order used in the processing of FIG. 3 are set as this data section, and then the FCS (frame Check sequence), ED (end delimiter), and FS (frame state) are arranged.

FIG. 5B. Is the contents of the active communication path switching instruction order, and the active communication path switching instruction display, active communication path switching cause, and active ring bus number are set. In addition, C.I. Is a working communication path switching confirmation order, and a working communication path switching confirmation display and a working communication path switching result (whether switching is possible or not) are set.

In the example of FIG. 3, the MPR 21 and each CPR 22 are
During initialization as an active communication path between -0 and 22-3 (I
When the ring bus # 0 (24) is set in (before PL), the ring bus # 1 (25) is used between the MPR21 and the CPR22-1 and between the MPR21 and the CPR22-3 as the working communication path for the IPL. The switching process shown in FIG. 3 is performed by the MPR 21 and each CPR 22 so that the communication path is the active communication path.
-1 and the MPRs 21 and 22-3 are executed via the working communication path (ring bus # 0) to perform switching.
The other active communication paths of MPR21 and CPR22-0 and MPR21 and CPR22-2 are not changed.

A method of averaging the number of active communication paths for IPL will be described below. When the other processors are CPRi (i is an integer of i ≧ 1 and the maximum value is n) with respect to the master processor (MPR) and the communication path is provided with two systems of ring buses # 0 and # 1, the MPR is In this order, the active communication path switching process (FIG. 3 above) is started for each processor. At this time, one of the ring buses is set as the working communication path.

CPR1, CPR2, CPR3, ... CPRn MPR is the number of active communication paths on ring bus # 0 and active on ring bus # 1 among active communication paths between CPRj (j ≦ n). Let the numbers of communication paths be a and b, respectively.

A. When a ≧ b The working communication path between MPR and CPRj is set to ring bus # 1. B. When b ≧ a, the working communication path between MPR and CPRj is set to ring # 0. Ring bus # 0 from the new communication path state of the switching target
The above number of active communication paths = a and the number of active communication paths on the ring bus # 1 = b are updated, and the above processing is performed on CPR (j + 1).

In this way, the number of ring buses # 0 and the number of ring buses # 1 set as the active communication paths from the MPR to each CPRi become substantially equal. In the configurations shown in FIGS. 2 to 5, the ring bus is used as a communication path for connecting the processors of the multiprocessor, but the present invention is also applicable to a system connected by a bus type communication bus. You can

FIG. 6 shows an example of system configuration connected by a communication bus. In this example, the three processors A to C are respectively connected by two buses, bus # 0 and bus # 1, and the bus arbiter arbitrates the bus usage right of each processor via a bus adapter. Even in such a system, normally only one bus is used as the active communication path and the other is used as the standby communication path. However, according to the present invention, when performing IPL, the processor A having an IPL data storage device is used.
However, by using the two buses # 0 and # 1, for example, the communication between the processor A and the processor B is performed by the bus # 0.
Is set as the current communication bus, and the communication between the processors A and C is set as bus # 1 as the current communication bus, whereby IPL data communication can be performed.

[0037]

According to the present invention, in a multiprocessor system, the number of active communication paths for IPL data transfer is averaged by effectively utilizing each communication bus provided at the time of IPL, and the system IPL time is increased. Can be shortened.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a structural example of an exchange system in which the present invention is implemented.

FIG. 3 is a processing flow for switching an active communication path.

FIG. 4 is an explanatory diagram of a state management table of inter-processor communication paths.

FIG. 5 is an explanatory diagram of communication data between processors.

FIG. 6 is an example of a system configuration connected by a communication bus.

FIG. 7 is a configuration diagram of a conventional multiprocessor system.

[Explanation of symbols]

 1 Specific Processor 10 State Management Table 1a Communication Bus Access Means 1b Communication Path Management Means 1c Working Communication Path Switching Means 1d Working Communication Path Number Averaging Means 1e IPL Data Reading Means 1f IPL Data Sending Means 2 IPL Data Storage 3 Processors (# 0, # 1 ... #m) 30 status management table 3a communication bus access means 3b communication path management means 3c working communication path switching means 3d IPL data receiving means 4 communication bus (# 0, # 1, ... #n)

Claims (2)

[Claims] 1. An IPL of an IPL data storage device, wherein a plurality of processors are connected by a communication bus and a specific processor is connected to the IPL
An IPL for a multiprocessor system that includes means for reading and transmitting data, means for receiving the IPL data from another processor via the communication bus, and communication between arbitrary processors is performed via the communication bus. In the method, a plurality of the communication buses are provided, each processor is provided with an access means to the plurality of communication buses, and the specific processor connects the plurality of communication buses to the working communication between the specific processor and another processor at the time of IPL execution. A communication path managing means for instructing allocation as a path, and an active communication path switching means for transmitting and receiving a control signal for switching an active communication path between the specific processor and each of the other processors according to an instruction from the communication path managing means. When the switching is possible by the control signal, the active communication path is switched to another communication bus to transfer the IPL data. IPL system of a multiprocessor system and performs transmission. 2. The device according to claim 1, wherein the specific processor is provided with means for averaging the number of active communication buses on each communication bus, and each processor is instructed to perform active communication with the specific processor by an instruction from the specific processor. When the IPL of the system is changed by changing the route by the active channel switching means, the specific processor averagely allocates the number of active channels for transmitting IPL data to each processor to the communication bus. IPL method of multiprocessor system.