JPH06150700A - Non-volatile semiconductor memory circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To ensure proper operation of memory cells in the over-erased state and to optimize the test to see if they are in that state. In the first aspect of the invention, in the test mode, the row decoder does not select any row line, and the source of each memory cell is set to the ground level. In this state, when there is an overerased memory cell, since this cell has been made into a depression, it becomes conductive according to the depletion. It is detected that there is an overerased memory cell by the change in the potential of the column line based on this conduction. A differential amplifier is used to detect the potential change of the column line, and the potential of the column line is compared with the reference potential given to the dummy column line during the test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device, which is made by paying attention to the erase state test and proper operation of an electrically rewritable nonvolatile memory cell. The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art A ROM in which stored data can be electrically erased and new data can be rewritten is an EEPROM (EROM
electrically erasable and
Also known as Programmable ROM). This EEPROM has an EP
Unlike ROM, there is no need to use ultraviolet light. Therefore,
Data can be erased and rewritten electrically while mounted on the board. Therefore, the degree of freedom is very high and it is easy to use, so that demand for various control devices and memory cards is rapidly increasing.

9 to 12 show the structure of a memory cell of such a conventional semiconductor memory device. FIG. 9 is a pattern plan view,
10 is a sectional view taken along the line AA 'of FIG. 9, and FIG. 11 is a sectional view taken along the line B- of FIG.
FIG. 12 is a sectional view taken along the line B ′ and FIG. 12 is an equivalent circuit configuration diagram of the memory cell of FIG. 9. As shown in these figures, a field oxide film 20 is formed on the P-type substrate 13. On the region surrounded by the oxide film 20, a floating gate 11 made of polycrystalline silicon of the first layer is formed via a gate insulating film 18 having a thickness of about 100 angstrom. A control gate 12 made of polycrystalline silicon of the second layer is formed on the gate 11 via an insulating film 19. The insulating film 19 is formed of ONO (Oxide-Nitri).
It has a three-layer structure of de-Oxide) and has a thickness of 200 Å in terms of oxide film. The control gate 12 is used as a word line of the memory cell. Also,
On the P-type substrate 13 on both sides of the floating gate 11 and the control gate 12, a source 14 and a drain 15 made of an N + type diffusion layer are formed. A contact hole 16 is opened in the drain 15 region. The data line 17 made of an aluminum layer is connected to the drain 15 through the contact hole 16. Note that FIG.
In the equivalent circuit shown in, the control gate 12 is CG and the source 1
4 is indicated by S and the drain 15 is indicated by D.

The operation of the above arrangement will be described below. At the time of data erasing, an erasing voltage of about 12V is applied to the source 14, the drain 15 is set in a floating state, and the control gate 12 is set to 0V. As a result, the floating gate 11 is formed through the thin gate insulating film 18.
A high voltage is applied between the source 14 and the source 14. As a result, due to the Fowler-Nordheim tunnel effect, the electrons in the floating gate 11 are emitted to the source 14 and the data is erased. In the large-capacity memory LSI, it is impossible to make the source 14 independent for each bit due to the chip size. Therefore, erase all chips at once, or divide the memory into several blocks,
Erase in block units.

On the other hand, when writing data, the drain 1
5 to about 6V, source 14 to 0V, control gate 12 to 12V
Apply V. As a result, impact ionization occurs near the drain 15 and electrons are injected into the floating gate 14. That is, data writing is performed.

Further, when reading data, the drain 15
Is 1 V, the source 14 is 0 V, and the control gate 12 is 5 V. As a result, "0" or "1" data is obtained based on the presence / absence of electrons in the floating gate 11.

To erase the data in the memory cell, electrons in the floating gate 11 are applied to the source 14 at a high voltage,
What is done by pulling out to the source 14 side is as described above. That is, the electric field between the floating gate 11 and the source 14 causes a tunnel current to flow and erase is performed.

The problem here is the variation of the erasing characteristics due to the variation of the electric field. Factors that determine the variation of the electric field are various factors such as the variation of the gate insulating film 18 and the fluctuation of the overlap length (shown by Xjs in FIG. 11) between the floating gate 11 and the source 14. Therefore, even if a certain voltage is applied to the source 14 for a certain period of time, a cell having a strong electric field and a cell having a weak electric field are generated, which causes a difference in the erase characteristic and a distribution in the erase state. That is, some cells have a high erase speed and some cells have a slow erase speed.

The erase characteristic diagram of FIG. 13 shows the threshold voltage distribution of the memory cells when erased. FIG.
The horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the current Id of the drain 15. FIG.
As is apparent from the above, an erase distribution is generated between cells with fast erase and cells with slow erase. In other words, memory LSI
In the erased state, if erasing is continued until the slowest cell in the erase distribution is erased, the fast erasing cell is overlaid (the threshold voltage becomes negative). As a result, even if the voltage Vg of the control gate 12 is 0V, the memory cell is not turned off and a leak current flows. That is, when the over-erase state occurs, the threshold voltage of the memory cell becomes negative and depletion occurs, and even if the control gate 12 is at 0 level, the control gate 12 is turned on and a current flows, which causes a leak current. .

FIG. 14 is a circuit configuration diagram for explaining the operation of the memory LSI when there is a memory cell in the overerased state. In FIG. 14, the row decoder 23 accesses the row lines WL1 to WLm. The column decoder 22 accesses the column lines BL1 to BLn. The memory cells M11 to M1n and Mm1 to Mmn are arranged in a matrix at the intersections of the row lines WL1 to WLm and the column lines BL1 to BLn. Here, the memory cell Mmn is a cell depleted by overerasing. A sense amplifier SA for reading data is connected to the column lines BL1 to BLn.

In the above configuration, the column decoder 2
It is assumed that the column line BLn is selected by 2 and the row decoder 23 applies a voltage of 5V to the row line WL1 and a voltage of 0V to the WLm. At this time, the memory cell to be selected is the memory cell M1n. Here, the memory cell M1n is
It is assumed that the cell has been written with 0 ". At this time, no current should flow through the column line BLn. However, the control gate of the unselected memory cell Mmn is 0.
Despite V, the leak current Il flows. Therefore, the sense amplifier SA includes the memory cell M1n.
The data of 1 is mistakenly read as "1". That is,
If there is a memory cell in the over-erased state on the selected column line BL1 to BLn, the cell is changed to the row line WL1 to W.
Regardless of whether or not it is selected by Lm, a leak current always flows, and the sense amplifier SA always reads "1". That is, the data in the cells connected to the column lines BL1 to BLn in which the memory cells in the overerased state exist cannot be read correctly.

Therefore, it is very important to test whether or not the memory cells are overlaid and depleted to ensure the operational reliability of the memory LSI.

[0013]

As described above, conventionally, it is difficult to erase the threshold value of the entire memory cell to an appropriate value, and further, the threshold value becomes an appropriate value. I couldn't easily measure whether I was there.

Since the present invention has been made to solve the above problems, it is possible to properly measure whether or not a memory cell is in an overerased state, and ensure the operational reliability of a memory LSI. can do.

[0015]

A nonvolatile semiconductor memory device of the present invention has a source, a drain, a floating gate, and a control gate, and is a nonvolatile memory cell that is electrically writable and erasable. A plurality of memory cells arranged in row and column directions and a plurality of row lines commonly connected to the control gates of the plurality of memory cells arranged in one row direction are arranged in one column direction. In a nonvolatile semiconductor memory device having a plurality of column lines commonly connected to the drains of the plurality of memory cells, an output signal is obtained by comparing a potential supplied to the column line with a potential supplied to the dummy column line. And a reference potential supply means for supplying a reference potential to the dummy column line when all the memory cells are deselected by the row decoder,
This reference potential is compared with the potential of the column line to which the unselected memory cell is connected, and a test means for generating a predetermined output signal when the potential of the column line is equal to or lower than a predetermined voltage. Has been done.

[0016]

According to the present invention, in the test mode, the row decoder does not select any row line, and the source of each memory cell is set to the ground level. In this state, if there are over-erased memory cells,
Since this cell is depleted, the memory cell becomes conductive according to the depletion. Due to this conduction, a current path is formed between the column line to which the memory cell is connected and the source, so that the potential of the column line drops. As a result, originally, if there is no depleted memory cell, the potential of the column line becomes lower than the predetermined reference potential even though there is no voltage drop of the column line. By comparing this with the reference potential given by the reference potential generating circuit by the differential sense amplifier, it can be seen that there are overerased memory cells.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, the row lines WL1 ...
Memory cells M11 to M1n and Mm1 to Mmn arranged in a matrix are connected to WLm and the column lines BL1 to BLn. The sources of these cells are connected to the output terminal Vss * of the source switching circuit 25. Sense amplifier SA connected to column lines BL1 to BLn
An output circuit 24 is connected to the read circuit to read a signal. The gates of the memory cells M11 to M1n and Mm1 to Mmn are connected to the row lines WL1 to WLm for each row,
Each drain is connected to the column lines BL1 to BLn for each column. The gates of the column lines BL1 to BLn are column decoders 2
Enhancement type column line selection transistors Tr1 to Trn controlled by two output signal lines CL1 to CLn
Via a common connection point N10. The common connection point N10 is connected to the sense amplifier SA.
The sense amplifier SA includes memory cells M11 to M1n and Mm1.
˜Mmn data is detected and output to the outside via the output circuit 24. The sense amplifier SA uses not a circuit using a reference dummy cell but a circuit using an inverter for detecting data after amplifying the amplitude of the bit line. The operation of the above arrangement will be described below.

When erasing the memory LSI, the signal Er
When the ase becomes “H”, the source Vs of the memory cell
A high voltage Vpp is applied to s * to extract electrons from the floating gate. After erasing, test whether the memory cell is in the overerased state. First, the row decoder 23 outputs all the non-selected states, that is, all the row lines WL1 to WLm.
Is the ground level. At this time, the source Vss * is at the ground level. In this state, the column decoder 22 sequentially selects and selects the column lines BL1 to BLn, and the data from the sense amplifier SA at this time is read. As a result, it is possible to detect whether or not there is a memory cell in the overerased state.

That is, when the over-erased memory cell is connected to the selected column line, the threshold voltage of the over-erased memory cell is negative and the depletion occurs, so that a leak current flows in the selected column line. Flowing. Originally, the column lines BL1 to BLn are charged and the sense amplifier S
The output output from A through the output circuit 24 is "0".
It should be. However, due to the leak current, "1" is output from the output circuit 24. In this way, defective chips can be removed.

Further, the column decoders may be selected one by one for the test, or all the column decoders may be selected at the same time and the column line selection transistors are simultaneously turned on to perform the leak test.

FIG. 2 is a circuit diagram showing an example of a specific configuration of the row decoder of FIG. As shown in FIG. 2, the P-channel transistors 31A to 31C are connected in parallel and the N-channel transistors 31D to 31F are connected in series. The gates of the transistors 31A to 31C are
It is connected to the gates of the transistors 31D to 31F. An address signal RA is applied to each gate of 31D to 31F.
i, RBi and signal NT that becomes "0" in test mode
Each EST is given and a decoded output is obtained.

The decoded output is the address signal RC1.
~ RC8 gate input selection transistor 31G1
Selected by 31G8. This selection transistor 3
1G1 to 31G8 also serve as level shift transistors.

On the output side of the selection transistors 31G1 to 31G8, N-channel transistors 31K1 to 31K whose address signals RC1 to RC8 are input to their gates.
8 is connected. P-channel transistor 31J
1 to 31J8 are for pull-up. The P-channel transistors 31H1 to 31H8 and the N-channel transistors 31I1 to 31I8 form a buffer circuit. Through this buffer circuit, the selection signal is output to the row lines WL1 to WLm which are the output lines of the row decoder 23.

Power is supplied to the terminal SW from a booster circuit (not shown), which is 12V for writing and 5V for reading. In the test mode, the signal N
Since TEST becomes “0”, all row lines WL1 to WL
m becomes the ground level and is in a non-selected state. On the other hand, in the normal read state, the signal NTEST becomes "1", and only one row line WL1 to WLm decoded by the address signals RAi, RBi, RCi is selected.

The memory cells M11 to M1n and Mm1 have been described above.
The configuration of the inverter system which does not use the dummy cell serving as the reference for detecting the data of up to Mmn has been described. Next, a configuration using dummy cells will be described.

FIG. 3 is a circuit diagram of the semiconductor memory device according to the embodiment of the present invention. As shown in FIG. 3, the row lines WL1 to WLm, which are the output lines of the row decoder 23, are
A plurality of transistors are connected as a dummy cell DM. Each source is connected to the reference output terminal Vref * of the dummy cell source switching circuit 36. The sense amplifier SA has output signal lines CL1 to CLn.
Column lines BL1 to BLn and the dummy cell D selected by
The lines connected to M are connected, and the respective differential signals are output from the sense amplifier SA to the output circuit 24. Also,
The other end of the dummy vref column line is connected to a fixed cell used in the above-mentioned overerase test, and its gate is connected to the output of the fixed dummy cell decoder 23-1 selected in the test mode. This is because all the row lines are in the non-selected state (0
This is because the gate voltage of the dummy cell becomes 0V and is turned off. That is, since the dummy cell is turned off, a reference potential cannot be set and a correct test cannot be performed.

When data is rewritten, the dummy cell D
It is not necessary to erase M. This is because the threshold voltage changes when the dummy cells DM are continuously erased, and the potential that serves as a reference for data detection fluctuates. Further, when the dummy vref method is used, a high voltage (12V) applied to the row line when writing data to the memory cell in the main body is applied to the gate of the dummy cell. As a result, electrons are gradually injected into the floating gate of the dummy cell, the threshold value gradually rises, and stable cell operation cannot be ensured. This is the so-called gate disturb.

Therefore, by providing the dummy cell source switching circuit 36, the electric field applied to the gate and the substrate at the time of writing is relaxed. That is, in the write mode, a voltage of about 3 V is output to the output of the dummy cell source switching circuit and applied to the source and drain of the dummy cell. Therefore, the electric field applied to the gate and the substrate is equivalent to the relaxation of 3V, and the gate disturb does not occur.

As described above, the semiconductor memory device according to the embodiment of the present invention selects a fixed cell other than the dummy cell used when reading data when testing whether or not it is in the overerase state. In addition, since a cell having the same characteristics as the main body dummy cell can be used, an operation margin can be secured.

Another embodiment of the present invention is shown in FIG. 4, the same elements as those in FIG. 3 are designated by the same reference numerals. The difference is that a fixed voltage cell having the same shape as the main body memory cell is not used during the overerase test, and a reference voltage generating transistor is provided outside the memory cell array. With this configuration, the dimension of the transistor can be set arbitrarily, and the reference potential can be set freely. That is, since the reference potential during the overerase test can be changed, the margin for the leak amount can be set freely.

The above-mentioned over-erase test can also be used in the case of a memory cell as shown in FIG. Figure 5
A plan view of the memory cell and its equivalent circuit are shown in FIG. Here, an example in which four row lines are included in each block is shown, but it goes without saying that the same can be said with eight or sixteen line lines. Further, there are four memory cells connected to one data line (for example, DL1) through the block selection transistor 42-1.

In particular, the layout shown in FIG. 5 is characterized in that the common drain 16 of these four memory cells is connected only by the diffusion layer and is not in contact with the aluminum line. The common drain 16 is connected to the diffusion layer 16A through the block selection transistor 42-1. The diffusion layer 16A is connected to the data line DL (aluminum line) via the contact 17. As a result, the number of contacts 17 is one for eight transistors in the upper and lower blocks. That is,
The number of contacts becomes 1/4, which effectively acts to reduce the pattern size. The source 15 of each cell is the diffusion layer 1
It is commonly connected at 5 A and is also connected to the Vss line 27 via a contact.

Next, the operation of such a memory cell will be described. This memory cell differs from the memory cell in that the concept of erasing is defined as having a high threshold value.
In order to reduce the gate disturbance at the time of writing to a cell having a low threshold value, the threshold value of all cells is first set to be high and the electrons are selectively extracted from the floating gate. In the erase operation, first, the select line BSL of the block in which the data is rewritten is set to "L" and the block select transistors 42-1 and 42-2 are turned off to bring it into a floating state. In this state, the source line Vss is set to the ground level (0V) and the row line in the block is set to 20V to inject electrons into the floating gate. At this time, since electrons are injected into the floating gate by the FN mechanism, almost no current flows. In this way, electrons are injected into the floating gate to raise the threshold value of all memory cells in the block.

Next, the write operation will be described. Writing is performed by selectively extracting electrons from the floating gate. The row line for writing is set to 0V, and the row lines in other blocks are set to 10V. 10 unselected row lines
The reason why the voltage V is set is that the high voltage is applied to the drains of all the memory cells in the block when the high voltage is applied to the drain for writing, so that the electric field between the drain and the gate is relaxed. Is. In this state, a high voltage of 20 V is applied to the drain of the memory cell to be written, so that electrons are extracted from the floating gate. That is, the threshold value becomes low. On the other hand, in the memory cell in which the drain is 0 V, electrons are not emitted from the floating gate,
The erased state is maintained as it is.

In the read operation, 5 V is applied to the gate of the block selection transistor of the block to be read, and the block is selected. Then, it is performed by applying 5V to the selected row line in the block. That is, if the threshold value is sufficiently high, the memory cell is turned off and no current flows. However, if the threshold value is low, the memory cell is turned on and a current flows. FIG. 6 shows the voltage relationship in the above operation in which this state is detected by the sense amplifier circuit.

Even in such a memory cell, electrons are extracted from the floating gate when writing is performed.
Overwriting at the time of writing is a problem, such as overerasing at the time of erasing in the type of the first embodiment. Therefore, after writing the data, it is necessary to perform an over-program test whether the memory cell is depleted.

Next, FIG. 7 shows a circuit configuration of a semiconductor memory device using such a memory cell. The example shown in FIG. 7 shows a type of sense amplifier circuit that is received by an inverter. In the over program test, all the block selection transistors 42-1 and 42-2 are selected to bring all the row lines (WL1 to WLm) into the non-selected state. In this state, the column decoder 22 causes the column line selection transistor (Tr
1 to Trn) are sequentially selected and read. If there is no over-programmed memory cell, no current flows and "0" data is output, but if there is an over-programmed memory cell, current flows and "1" data is output, and over-programming can be detected. In this test mode, all the column selection transistors may be selected at the same time, tests may be performed in block units, or all blocks may be performed simultaneously. The configuration of the inverter system that does not use a dummy cell that serves as a reference for detecting data has been described above. Next, a configuration using dummy cells will be described.

FIG. 8 is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention. As shown in FIG. 8, the row lines WL1 to WLm which are the output lines of the row decoder 23.
, A plurality of transistors are connected as a dummy cell DM. Each source is connected to the reference output terminal Vref * of the dummy cell source switching circuit 36.
The sense amplifier SA includes output signal lines CL1 to CL.
The column lines BL1 to BLn selected by Ln are connected to the lines connected to the dummy cells DM, and the respective differential signals are output from the sense amplifier SA to the output circuit 24. In addition to the memory cell array, a reference potential generating transistor used in the over program test is connected. This is because at the time of the above-mentioned over program test, all the row lines are in the non-selected state (0V), so that the gates of the dummy cells also become 0V and are turned off. That is, since the dummy cell is turned off, a reference potential cannot be set and a correct test cannot be performed.

When data is rewritten, the dummy cell D
No need to do this for M. Also, such a dummy vr
When the ef method is used, the high voltage (20 V) applied to the row line when setting the initial state of the memory cell in the main body is applied to the gate of the dummy cell. As a result, electrons are gradually injected into the floating gate of the dummy cell DM, the threshold value gradually rises, and stable cell operation cannot be ensured. This is the so-called gate disturb. Therefore, by providing the dummy cell source switching circuit 36, the electric field applied to the gate and the substrate during erasing is relaxed. That is, in the erase mode, a voltage of about 3 V is output to the output of the dummy cell source switching circuit 36 and applied to the source and drain of the dummy cell DM. Therefore, the electric field applied to the gate and the substrate is equivalent to the relaxation of 3V, and the gate disturb does not occur. By providing the reference voltage generating transistor outside the memory cell array without using the fixed cell having the same shape as the main body memory cell, the dimension of the transistor can be arbitrarily set, and the reference potential can be freely set. That is, since the reference potential during the overerase test can be changed, the margin for the leak amount can be set freely.

In the above embodiment, the reference potential used in the differential amplifier at the time of reading is the one using the floating gate type transistor, but the present invention is not limited to this, and various circuits are used. Conceivable. For example, the reference potential having a predetermined value may be formed by resistively dividing the power supply voltage. However, when the dummy cell shown in the embodiment is used, it can be formed in the same region as the region where the memory cell is formed, and can be formed in the same process. Therefore, since there is almost no variation in the performance of the transistors of the memory cell and the dummy cell, there is an effect that an error does not easily occur in the read data even when the substrate potential changes due to the influence of noise or the like.

Further, in the above embodiment, the comparison between the voltage of the column line and the reference potential in the test mode is detected by the differential sense amplifier for reading, but the present invention is not limited to this. Instead, it is sufficient if it can detect the voltage drop of the column line. For example, a person skilled in the art can consider various means such as newly using another detection circuit.

[0043]

According to the present invention, the reference memory cell can be set using the same memory cell as the main body memory cell, and variations in cell characteristics can be reflected similarly to the main body cell. Even with such a configuration, it is possible by selecting another reference potential generating transistor even if all the row lines are in the non-selected state during the test. Therefore, a stable read operation can be secured, and whether the threshold value of the memory cell is negative can be properly measured.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a memory cell of a semiconductor memory device according to another embodiment of the present invention.

FIG. 6 is a diagram showing operating voltages in a semiconductor memory device according to another embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 9 is a diagram showing a memory cell of a conventional semiconductor memory device.

FIG. 10 is a diagram showing a memory cell of a conventional semiconductor memory device.

FIG. 11 is a diagram showing a memory cell of a conventional semiconductor memory device.

FIG. 12 is a diagram showing a memory cell of a conventional semiconductor memory device.

FIG. 13 is a diagram showing erase characteristics of a conventional semiconductor memory device.

FIG. 14 is an explanatory diagram of an overerase state of a conventional semiconductor memory device.

[Explanation of symbols]

 22 column decoder 23 row decoder 23-1 fixed dummy cell decoder 24 output circuit 25 source switching circuit 36 dummy cell source switching circuit

Claims (4)

[Claims] 1. A memory having a source, a drain, a floating gate, and a control gate, which is configured by arranging a plurality of electrically writable and erasable nonvolatile memory cells in the row and column directions. A cell array and a plurality of row lines commonly connected to the control gates of the plurality of memory cells arranged in one row direction, and a column commonly connected to the drains of the plurality of memory cells arranged in one column direction. In a nonvolatile semiconductor memory device having a plurality of lines and a dummy column line, a differential sense amplifier for generating an output signal by comparing a potential supplied to the column line with a potential supplied to the dummy column line. And a reference potential supply means for supplying a reference potential to the dummy column line when all the memory cells are unselected,
The reference potential is compared with the potential of the column line to which the non-selected memory cell is connected, and a test means for generating a predetermined output signal when the potential of the column line is a predetermined voltage or less. A non-volatile semiconductor memory device characterized by the above. 2. A memory having a source, a drain, a floating gate, and a control gate, and configured by arranging a plurality of electrically writable and erasable nonvolatile memory cells in the row and column directions. A cell array and a plurality of row lines commonly connected to the control gates of the plurality of memory cells arranged in one row direction, and a column commonly connected to the drains of the plurality of memory cells arranged in one column direction. In a non-volatile semiconductor memory device having a plurality of lines, a source, a floating gate, a drain connected to a dummy column line, and a control gate connected to the row line are read, and data of a predetermined memory cell is read out. Sometimes a dummy memory cell that supplies a predetermined potential to the dummy column line and a difference that generates an output signal by comparing the potential supplied to the column line with the potential supplied to the dummy column line. Type sense amplifier, it has all of the reference potential supplying means for supplying a reference potential to the dummy column line when the memory cell was not selected,
The reference potential is compared with the potential of the column line to which the non-selected memory cell is connected, and when the potential of the column line is equal to or lower than a predetermined voltage, a predetermined output signal is output to the differential sense circuit. A non-volatile semiconductor memory device having means for generating in an amplifier. 3. The reference potential supply means comprises a floating gate type transistor, and when all the memory cells are deselected, the reference potential and the column line to which the unselected memory cells are connected. The potentials of the transistors are compared with each other, and when the potential of the column line is equal to or lower than a predetermined voltage, the transistor is controlled to be in a conductive state in a test mode in which a predetermined output signal is generated. 1
Alternatively, the nonvolatile semiconductor memory device according to claim 2. 4. The reference potential supply means compares potentials of the reference potential and the column line to which the non-selected memory cells are connected when all the memory cells are unselected, and the column Connected to a fixed dummy cell decoder that generates a control signal in a test mode that generates a predetermined output signal when the potential of the line is equal to or lower than a predetermined voltage, and the dummy column line that becomes conductive when the control signal is input. 2. The fixed dummy cell formed according to claim 1,
Alternatively, the nonvolatile semiconductor memory device according to claim 2.