JPH06151448A - Method for manufacturing heterojunction bipolar transistor - Google Patents

Abstract

(57) [Summary] [Structure] In a process of manufacturing an HBT having a collector-up structure in which a semiconductor layer containing Al is used as a wide-gap emitter layer 102, a plasma including F is formed after a collector mesa is formed to expose the base layer 103. The treatment is performed to increase the resistance of the external base region 106 and the external emitter region 107. Then, by performing annealing at 400 to 600 ° C., the resistance of the external base region 106 is lowered to the level before the plasma treatment. On the other hand, the external emitter region 107
Further increases the resistance. [Effect] A collector-up type HBT having a small base / collector capacitance and an external base resistance and a large current gain.
Can be manufactured by a simple process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an ultrahigh speed bipolar transistor, and more particularly to a method for manufacturing a heterojunction bipolar transistor having a collector-up structure having a small base-collector capacitance.

[0002]

2. Description of the Related Art In an AlGaAs / GaAs heterojunction bipolar transistor (HBT), a base layer can be heavily doped without lowering current gain. for that reason,
It has attracted attention as a transistor that has a small parasitic base resistance and can operate at high speed. In order to realize a high-speed HBT circuit, it is important to further reduce the base-collector capacitance due to the external base region. As a countermeasure,
For example, IEE Electron Device Letters EDL-7 Volume 1 January 1986
Pages 32-34 (IEEE ELECTRON DEVICE LETTERS, VOL.E
DL-7, No. 1 JANUARY 1986 P. 32-34)
As described in (1), a so-called collector-up structure HBT having a subcollector layer as an uppermost layer has been proposed. In the collector-up structure HBT, the parasitic capacitance is extremely small because there is no external base-collector junction.
There is concern that the current gain may decrease due to electron injection at the external emitter-base junction. In order to suppress such electron injection in the external emitter-base junction, techniques for increasing the resistance of the external emitter region by ion implantation have been studied.

[0003]

In order to increase the resistance of the external emitter of the collector-up structure HBT described above, ion implantation of B or O is used to increase the resistance of the AlGaAs emitter layer. At this time, the external base layer on the emitter layer is also damaged by the irradiation of ions accelerated to several hundred keV, which causes an increase in parasitic base resistance. In order to suppress the increase in resistance of the external base layer due to this ion irradiation damage, measures such as further implantation of a p-type dopant are being studied. However, the annealing process after the dopant implantation reduces the resistance of the external emitter layer, which has been increased in resistance. That is, when the ion implantation technique is used, there is a problem that there is a trade-off relationship between the resistance increase of the external emitter and the resistance decrease of the external base of the collector-up structure HBT.

[0004]

In a manufacturing process of a collector-up structure HBT in which a semiconductor containing Al is adopted as a wide-gap emitter layer, a collector mesa is formed using a desired mask pattern and an external base region is exposed. , F containing gas is subjected to plasma treatment. afterwards,
Annealing at 400 to 600 ° C. is performed. This allows
It is possible to increase the resistance of the external emitter region while maintaining the low resistance value of the external base resistance before the plasma processing.

[0005]

When the semiconductor containing n-type Al is subjected to the plasma treatment containing F on the external base region composed of the wide gap emitter layer and the high concentration p-type base layer, the emitter layer and the base layer have high resistance. . The energy of ions incident on the sample by the plasma treatment is several tens of eV, which is orders of magnitude smaller than the acceleration energy of ion implantation. Therefore,
Ion irradiation damage to the outer base layer is also small. After that, when an annealing treatment at 400 to 600 ° C. is performed, the resistance of the base layer returns to the value before the plasma treatment. On the other hand, it was experimentally confirmed by the inventor that the emitter layer has a much higher resistance (FIG. 3). It is considered that this is because F introduced into the wide gap emitter layer of a semiconductor containing Al formed a trap that became active by annealing.

[0006]

【Example】

<Embodiment 1> An embodiment of the present invention will be described with reference to the process chart shown in FIG. MB on a semi-insulating GaAs substrate 100
High concentration n-type GaAs sub-emitter layer 10 using the E method
1, n-type AlGaAs emitter layer 102, p-type GaAs
The base layer 103, the low concentration GaAs collector layer 104, and the high concentration n-type GaAs subcollector layer 105 were sequentially grown (FIG. 1A). Next, a collector mesa was formed by using a normal lithography technique and a dry etching technique to expose the external base region of the p-type GaAs base layer 103 (FIG. 1B). Then, the sample was subjected to NF ₃ plasma treatment using a parallel plate electrode device. The NF ₃ gas pressure at this time is 10 mtorr. This process results in the external base region 106 and the underlying external emitter layer 10
7 has a high resistance (FIG. 1 (c)). Subsequently, the sample was annealed at 450 ° C. for 10 minutes in an H ₂ atmosphere using an annealing furnace. By this annealing, p-type GaAs
The external base region 106 is made to have a low resistance value before the NF ₃ plasma treatment.

On the other hand, the external emitter region 107 made of low concentration GaAs has a higher resistance (FIG. 2 (a)). Next, a base mesa was formed by using a normal lithography technique and a dry etching technique to expose the sub-emitter layer 101. After that, the sub-emitter layer 101 and the sub-collector layer 1 are formed by the usual lithography technique and lift-off method.
For 04, an emitter electrode 108 and a collector electrode 109 made of AuGe / Ni / Au were formed. In addition, the external base region 106 made of high-concentration p-type GaAs
Also for the base electrode 1 made of AuZu / Ni / Au
10 was formed (FIG. 2 (b)).

In this embodiment, since the resistance of the external emitter region 107 can be selectively increased, the parasitic base resistance can be reduced, and therefore, the HBT capable of operating at high speed can be manufactured.

Further, in this embodiment, the NF ₃ plasma treatment is used to increase the resistance of the external base region 106 and the external emitter layer 107 thereunder, but another gas containing F such as SF ₆ is used. It is also effective when used.

In this embodiment, the HB is composed of an AlGaAs emitter / GaAs base formed on a GaAs substrate.
As for T, but InAlAs on InP substrate
The same effect can be obtained by using the HBT composed of the emitter / InGaAs base.

<Embodiment 2> An embodiment of the present invention will be described with reference to the process diagrams shown in FIGS. Semi-insulating GaA
On the s substrate 200, a high concentration n-type GaA is formed by using the MBE method.
s sub-emitter layer 201, n-type AlGaAs emitter layer 202, p-type GaAs base layer 203, low concentration GaAs
Collector layer 204 and high-concentration n-type GaAs and InGa
A sub-collector layer 205 made of As is sequentially grown,
Next, the WSi film 206 was deposited by using the sputtering method (FIG. 4A). Next, using a normal lithography technique and a dry etching technique using SF ₆ and SiCl ₄ gas, W
The Si film 206 was patterned, and the subcollector layer 205 and the collector layer 204 were etched using the same mask to expose the base layer 203. At this time, the external base region 207 and the external emitter region 2 thereunder
08 has a high resistance (FIG. 4 (b)). Subsequently, the sample was annealed at 450 ° C. for 10 minutes in an H ₂ atmosphere using an annealing furnace. By this annealing, p-type GaA
The outer base region 207 made of s is SF ₆ and SiCl ₄
The resistance is reduced to the value before dry etching by gas. On the other hand, the external emitter region 2 made of low concentration GaAs
08 further increases the resistance (FIG. 4 (c)). Next, a base mesa was formed by using a normal lithography technique and a dry etching technique to expose the sub-emitter layer 201. After that, the emitter electrode 209 made of AuGe / Ni / Au and the base electrode 210 made of AuZu / Ni / Au are formed on the sub-emitter layer 201 and the external base region 207 by the usual lithography technique and lift-off method (FIG. 5). ).

In this embodiment, WSi serving as the collector electrode is used.
Step of patterning the film 206, sub-collector layer 20
5 and the collector layer 204 are etched to form the base layer 20.
Since the step of exposing 3 and the step of increasing the resistance of the external base region 207 and the external emitter layer 208 thereunder are continuously performed in the same chamber or device using the same mask, the steps can be greatly simplified.

<Embodiment 3> An embodiment of the present invention will be described with reference to the process charts shown in FIGS. Semi-insulating GaA
On the s substrate 300, a high concentration n-type GaA is formed by using the MBE method.
s sub-emitter layer 301, n-type AlGaAs emitter layer 302, p-type GaAs base layer 303, low concentration GaAs
Collector layer 304 and high-concentration n-type GaAs and InGa
The sub-collector layer 305 made of As grows sequentially,
Next, the WSi film 306 was deposited by using the sputtering method (FIG. 6A). Then, the WSi film 306 is patterned by using a normal lithography technique and a dry etching technique, and subsequently, the sub-collector layer 305 is formed by using the same mask.
And the collector layer 304 is etched to form the base layer 303.
Was exposed to form a collector mesa (FIG. 6B). Next, a SiO ₂ film 307 was deposited on the entire surface (FIG. 6A).
After that, the SiO ₂ film 307 was etched by reactive ion etching using a gas containing F to form the side wall SiO ₂ film 308 in a self-aligned manner with respect to the collector mesa. Further, at this time, the external base region 309 and the external emitter region 310 therebelow have high resistance (FIG. 7).
(a)). Subsequently, the sample was annealed at 450 ° C. for 10 minutes in an H ₂ atmosphere using an annealing furnace. By this annealing, the resistance of the external base region 309 made of p-type GaAs is lowered to the resistance value before the formation of the side wall SiO ₂ film 308. On the other hand, the external emitter region 310 made of low concentration GaAs has a higher resistance (FIG. 7B). Next, AuZu / Ni / is formed in a region including the collector mesa and its periphery by using a normal lithography technique and a lift-off method.
After the base electrode 311 made of an Au film was vapor-deposited, a resist film 312 was applied to flatten the surface (FIG. 7C). After that, etching back is performed using an ion milling technique to form a base electrode 311 on the external base region 309 separated from the collector mesa by the width of the sidewall SiO ₂ film 308 (FIG. 8A). Then, a base mesa was formed by using a normal lithography technique and a dry etching technique to expose the sub-emitter layer 301. After that, the sub-emitter layer 301 is formed by the usual lithography technique and lift-off method.
Emitter electrode 313 made of AuGe / Ni / Au on top
Was formed (FIG. 8 (b)).

In this embodiment, the base electrode 313 is formed on the external base region 309 separated by the width of the side wall SiO ₂ film 308 formed in self-alignment with the collector mesa.
The parasitic base resistance can be reduced. Further, since the step of forming the sidewall SiO ₂ film 308 and the step of increasing the resistance of the external base region 309 and the external emitter region 310 thereunder are performed in the same step, the steps can be simplified.

[0015]

According to the present invention, in the HBT having the collector-up structure, the resistance of the external emitter region can be selectively increased. Therefore, it is possible to realize an HBT that has a small base resistance and a large current gain and can operate at high speed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a process according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a process according to the first embodiment of the present invention.

FIG. 3 is an explanatory view of a high resistance phenomenon used in the present invention.

FIG. 4 is an explanatory diagram of a process according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a process according to a second embodiment of the present invention.

FIG. 6 is a process explanatory diagram of Embodiment 3 of the present invention.

FIG. 7 is a process explanatory diagram of Embodiment 3 of the present invention.

FIG. 8 is a process explanatory diagram of Embodiment 3 of the present invention.

[Explanation of symbols]

100 ... Semi-insulating GaAs substrate, 101 ... Sub-emitter layer, 102 ... Emitter layer, 103 ... Base layer, 104 ...
Collector layer, 105 ... Sub-collector layer, 106 ... External base region, 107 ... External emitter region.

Claims (4)

[Claims] 1. A high-concentration n-type sub-emitter layer made of a first semiconductor, an n-type emitter layer made of a second semiconductor containing Al, and a high-concentration p made of the first semiconductor on a semiconductor substrate.
A base layer, a low-concentration collector layer made of the first semiconductor, and a high-concentration n-type subcollector layer made of the first semiconductor, and a collector mesa is formed using a desired mask pattern. Exposing a high-concentration p-type extrinsic base region made of a semiconductor, and a gas containing F for the high-concentration p-type extrinsic base region and an n-type emitter layer made of a second semiconductor below the region And a step of performing an annealing treatment at 400 to 600 ° C., the method for manufacturing a heterojunction bipolar transistor. 2. A high-concentration n-type sub-emitter layer made of a first semiconductor, an n-type emitter layer made of a second semiconductor containing Al, and a high-concentration p made of the first semiconductor on a semiconductor substrate.
Type base layer, low-concentration collector layer made of the first semiconductor, and high-concentration n-type subcollector layer made of the first semiconductor, plasma etching of a gas containing F using a desired mask pattern And a step of exposing the high-concentration p-type external base region made of the first semiconductor, and a step of performing an annealing treatment at 400 to 600 ° C., thereby manufacturing a heterojunction bipolar transistor. 3. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein SF ₆ and NF ₃ gases are used for plasma treatment of the gas containing F. 4. The plasma treatment of the gas containing F according to claim 2, wherein SF ₆ , NF ₃ gas and Cl such as SiCl ₄ are used.
Method for manufacturing a heterojunction bipolar transistor using a gas containing helium.