JPH06162062A - Two-dimensional 8x8 discrete cosine transforming circuit and two-dimensional 8x8 discrete cosine inverse transforming circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The number of multiplications is small and the calculation accuracy does not decrease. 2
Dimension 8x8 Discrete Cosine Transform Circuit (2D 8x8 DCT
Circuit). [Structure] A two-dimensional 8 × 8 DCT conversion matrix is decomposed into a matrix, and between the original input data [x] and the output data [x],
[Y] = 1/32 [R] [Q4] [Q3] [Q2] [Q
1] [Q1] [x]. [Q1], [Q2],
[Q3] and [Q4] are constant matrices containing 0, 1, -1, and the multiplications are performed by the first addition / subtraction circuit 3, the second addition / subtraction circuit 5, and the third addition / subtraction circuit 7.
[R] is a matrix containing an irrational number defined by a two-dimensional 8 × 8 DCT, and the multiplication and addition circuit 9 performs the calculation for multiplication. Also, for a two-dimensional 8x8 IDCT, a two-dimensional 8x
The calculation opposite to the case of 8DCT is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform used in digital image processing and the like.
sform: DCT) circuit and inverse discrete cosine transform (Inverse
DCT: IDCT) circuit.

[0002]

2. Description of the Related Art Discrete Cosine Transform and Inverse Discrete Cosine Transform are ones of orthogonal transforms for transforming a real space to a frequency space and an inverse transform thereof.
Used for image processing.

The two-dimensional 8x8 discrete cosine transform, which is one of the discrete cosine transform and the discrete cosine inverse transform, and the two-dimensional 8x8 discrete cosine inverse transform, which is the inverse thereof, are expressed by the following equations (1) and (2). it can.

[Equation 1]

Here, the matrix [X] is the original data in the real space of 8 rows × 8 columns, and the matrix [Y] is the matrix data in the frequency space of 8 rows × 8 columns. The matrix [P] is a constant matrix of 8 rows × 8 columns for conversion, and [P ^t ] is a transposed matrix of the matrix [P]. Hereinafter, the subscript t on the right shoulder indicates a transposed matrix. The matrix [P] is defined by the following equation (3).

[Equation 2]

Two-dimensional 8 × 8 represented by the above equation (1)
The DCT calculation process is realized by repeating the one-dimensional 8 × 8 DCT calculation process twice. That is,
To obtain all the components (64) of [Y], eight multipliers are used to calculate the 8th-order inner product of [P] and [X] (or [X] and [P ^t ]) 64 times. Then, using another eight multipliers, [P] [X] and [ ^Pt ] (or [P]
And [X] [P ^t ]) are performed 64 times. Therefore, 8 × 64 × 2 = 1024 multiplications are required to obtain all the components (64) of [Y].

In addition, regarding the calculation processing of the two-dimensional 8 × 8 IDCT represented by the above-mentioned equation (2), the one-dimensional 8 × 8 ID
It is realized by repeating the calculation process of CT twice. That is, in order to obtain all the components (64) of [X], eight multipliers are used to calculate the 8th-order inner product of [Y] and [P] (or [P ^t ] and [Y]). 64 times,
After that, using another eight multipliers, [P ^t ] and [Y]
Eighth-order inner product calculation of [P] (or [P ^t ] [Y] and [P]) is performed 64 times. Therefore, 8 × 64 × 2 = 1024 multiplications are required to obtain all the components (64) of [X].

[0007]

In the above-described conventional two-dimensional 8x8 DCT circuit and two-dimensional 8x8 IDCT circuit, the multiplication must be performed 1024 times, and the multiplication becomes complicated as compared with the addition circuit or the subtraction circuit. The number of circuits increases, and the two-dimensional 8x8 DCT circuit and 8x8
There is a problem that the circuit configuration itself of the IDCT circuit becomes very complicated. Further, when an arithmetic operation including an irrational number is performed many times, there is a problem that an error caused by approximation of the irrational number is accumulated and the accuracy of the calculation result is deteriorated.

The present invention solves the above problems, reduces the number of multiplications, simplifies the circuit configuration, and reduces the circuit scale.
An object of the present invention is to provide a two-dimensional 8x8 discrete cosine transform circuit that can obtain a highly accurate calculation result, and a two-dimensional 8x8 discrete cosine transform circuit as an inverse transform circuit thereof.

[0009]

In order to solve the above problems and achieve the above-mentioned object, a discrete cosine transform circuit and a discrete cosine inverse transform circuit according to the present invention include a basic equation of discrete cosine transform and a discrete cosine inverse transform. The basic expression of is decomposed into a constant matrix that is as simple as possible within the range that does not change the operation result, and the operation expression is modified. Based on the modified operation expression, the number of multiplications is reduced as much as possible, and simple operation processing is performed. The circuit configuration is sufficient.

[0010] of the above-described formula (1) and (2), each component x _ij of the data components y _ij and the original data [y] [x] on the frequency, the following formula (4) and ( There is a linear primary conversion relationship that can be expressed by 5).

[Equation 3]

[M] in the equation (4) and [M ^t ] in the equation 5 can be matrix-decomposed (factor decomposition), and the equations (4) and (5) are respectively represented by the following equations (6) and (7). Can be rewritten as FIG. 10 shows a trigonometric function formula used in matrix decomposition.

[Equation 4]

The matrix [R] in the equation (6) is composed of 16 small matrices [R ₁₁ ] to [R ₄₄ ] as shown in FIG. 55, and the small matrix [R ₁₁ ] is shown in FIG. [R ₁₂ ] is shown in FIG.
7, the small matrix [R ₁₃ ] is shown in FIG. 58, and the small matrix [R ₁₄ ] is shown in FIG.
9. The small matrix [R ₂₁ ] is shown in FIG. 60 and the small matrix [R ₂₂ ] is shown in FIG.
1. The small matrix [R ₂₃ ] is shown in FIG. 62 and the small matrix [R ₂₄ ] is shown in FIG.
3, the small matrix [R ₃₁ ] is shown in FIG. 64, and the small matrix [R ₃₂ ] is shown in FIG.
5. The small matrix [R ₃₃ ] is shown in FIG. 66 and the small matrix [R ₃₄ ] is shown in FIG.
7. The small matrix [R ₄₁ ] is shown in FIG. 68 and the small matrix [R ₄₂ ] is shown in FIG.
9, the small matrix [R ₄₃ ] is shown in FIG. 70, and the small matrix [R ₄₄ ] is shown in FIG. 71.
Is defined as Thus, the matrix [R] is 8x
8 Irrational numbers A, B, C, D, E, F, and G defined by the cosine function in the discrete cosine transform and these negative irrational numbers -A, -B, -C, -D,- E, -F,
64x including -G and "1", "-1", "0"
There are 64 matrices.

The matrix [Q1] in equation (6) is shown in FIG.
As shown in FIG. 12, it is composed of 16 sub-matrices [Q1 ₁₁ ] to [Q1 ₄₄ ]. The sub-matrices [Q1 ₁₁ ] are shown in FIG.
1 ₁₂ ] is shown in FIG. 13, small matrix [Q1 ₁₃ ] is shown in FIG. 14, small matrix [Q1 ₁₄ ] is shown in FIG. 15, small matrix [Q1 ₂₁ ] is shown in FIG. 16, small matrix [Q1 ₂₂ ] is shown in FIG. Q1 ₂₃ ] is shown in FIG. 18, a small matrix [Q1 ₂₄ ] is shown in FIG. 19, a small matrix [Q1 ₃₁ ] is shown in FIG.
The small matrix [Q1 ₃₂ ] is shown in FIG. 21, and the small matrix [Q1 ₃₃ ] is shown in FIG.
2, the small matrix [Q1 ₃₄ ] is shown in FIG. 23, the small matrix [Q1 ₄₁ ] is shown in FIG. 24, the small matrix [Q1 ₄₂ ] is shown in FIG. 25, the small matrix [Q1 ₄₃ ] is shown in FIG. 26, and the small matrix [Q1 ₄₄ ] is shown in FIG. 27 is defined.

The matrix [Q2] in equation (6) is shown in FIG.
As shown in FIG. 29, 16 sub-matrices [Q2 ₁₁ ] to [Q2 ₄₄ ] are included. The sub-matrices [Q2 ₁₁ ] are shown in FIG.
2 ₁₂ ] is shown in FIG. 30, the small matrix [Q2 ₁₃ ] is shown in FIG. 31, the small matrix [Q2 ₁₄ ] is shown in FIG. 32, the small matrix [Q2 ₂₁ ] is shown in FIG. 33, the small matrix [Q2 ₂₂ ] is shown in FIG. Q2 ₂₃ ] is shown in FIG. 35, a small matrix [Q2 ₂₄ ] is shown in FIG. 36, and a small matrix [Q2 ₃₁ ] is shown in FIG. 37.
The small matrix [Q2 ₃₂ ] is shown in FIG. 38, and the small matrix [Q2 ₃₃ ] is shown in FIG.
9. The small matrix [Q2 ₃₄ ] is shown in FIG. 40, the small matrix [Q2 ₄₁ ] is shown in FIG. 41, the small matrix [Q2 ₄₂ ] is shown in FIG. 42, the small matrix [Q2 ₄₃ ] is shown in FIG. 43, and the small matrix [Q2 ₄₄ ] is shown in FIG. It is defined as 44.

The matrix [Q3] in the equation (6) is shown in FIG.
As shown in Figure 4, four 8x8 submatrixes [Q
3 ₁₁ ], [Q 3 ₂₂ ], [Q 3 ₃₃ ], [Q 3 ₄₄ ] and the other factors are 0. The small queue [Q3 ₁₁ ] is shown in Figure 46,
The small matrix [Q3 ₂₂ ] is shown in FIG. 47, and the small matrix [Q3 ₃₃ ] is shown in FIG.
8, the small matrix [Q3 _44] is defined as in Figure 49. The matrix [Q4] in the equation (6) has four 8 × 8 sub-matrices [Q4 ₁₁ ] and [Q4] on the diagonal as shown in FIG.
4 ₂₂ ], [Q 4 ₃₃ ], [Q 4 ₄₄ ], and the other factors are 0. The sub-matrix [Q4 ₁₁ ] is shown in FIG.
₂₂ ] is shown in FIG. 52, and the sub-matrix [Q4 ₃₃ ] is shown in FIG.
₄₄ ] is defined as shown in FIG.

The matrix [R ^t ] in equation (7) is shown in FIG.
As shown in 6, sixteen small matrices [R ^t ₁₁ ]-[R ^t ₄₄ ].
And the small matrix [R ^t ₁₁ ] is shown in FIG.
^t _12] FIG. 118, the small matrix [R ^t _13] FIG. 119, the small matrix [R ^t _14] FIG. 120, the small matrix [R ^t _21] Figure 12
1, the small matrix [R ^t _22] FIG. 122, the small matrix [R ^t _23] FIG. 123, the small matrix [R ^t _24] FIG. 124, the small matrix [R ^t
_31] FIG. 125, the small matrix [R ^t _32] FIG. 126, the small matrix [R ^t _33] FIG. 127, the small matrix [R ^t _34] FIG. 128,
The small matrix [R ^t ₄₁ ] is shown in FIG. 129, and the small matrix [R ^t ₄₂ ] is shown in FIG.
30, small matrix [R ^t ₄₃ ] is shown in FIG. 131, small matrix [R ^t ₄₄ ].
Is defined as shown in FIG. Thus, the matrix [R
^t ] is an irrational number A, B, C, D, E, defined by the cosine function in the 8 × 8 discrete cosine transform and defined by the equation 3.
F, G and these negative irrational numbers -A, -B, -C, -D,
-E, -F, -G and "1", "-1", "0"
Is a 64x64 matrix containing.

The matrix [Q1 ^t ] in equation (7) is as shown in FIG.
As shown in FIG. 2, 16 small matrices [Q1 ^t ₁₁ ] to [Q1 ^t
₄₄ ], the small matrix [Q1 ^t ₁₁ ] is shown in FIG. 73, the small matrix [Q1 ^t ₁₂ ] is shown in FIG. 74, the small matrix [Q1 ^t ₁₃ ] is shown in FIG.
The small matrix [Q1 ^t ₁₄ ] is shown in FIG. 76, the small matrix [Q1 ^t ₂₁ ] is shown in FIG. 77, the small matrix [Q1 ^t ₂₂ ] is shown in FIG. 78, and the small matrix [Q
1 ^t _23] FIG. 79, the small matrix [Q1 ^t _24] FIG. 80, the small matrix [Q1 ^t _31] FIG. 81, the small matrix [Q1 ^t _32] Figure 8
2. Sub-matrix [Q1 ^t ₃₃ ] is shown in FIG. 83, sub-matrix [Q1 ^t ₃₄ ].
84, the small matrix [Q1 ^t ₄₁ ] is shown in FIG. 85, the small matrix [Q1 ^t ₄₁ ].
^t _42] FIG. 86, the small matrix [Q1 ^t _43] FIG. 87, the small matrix [Q1 ^t _44] is defined as in Figure 88.

The matrix [Q2 ^t ] in the equation (7) is shown in FIG.
16 sub-matrices [Q2 ^t ₁₁ ]-[Q2 ^t
Consists of _44], small matrix [Q2 ^t _11] FIG. 90, the small matrix [Q2 ^t _12] FIG. 91, the small matrix [Q2 ^t _13] FIG. 92,
The small matrix [Q2 ^t ₁₄ ] is shown in FIG. 93, the small matrix [Q2 ^t ₂₁ ] is shown in FIG. 94, the small matrix [Q2 ^t ₂₂ ] is shown in FIG. 95, and the small matrix [Q
2 ^t _23] FIG. 96, the small matrix [Q2 ^t _24] FIG. 97, the small matrix [Q2 ^t _31] FIG. 98, the small matrix [Q2 ^t _32] Figure 9
9. The small matrix [Q2 ^t ₃₃ ] is shown in FIG.
2 ^t _34] FIG. 101, the small matrix [Q2 ^t _41] FIG. 102,
The sub-matrix [Q2 ^t ₄₂ ] is defined as shown in FIG. 103, the sub-matrix [Q2 ^t ₄₃ ] is defined as shown in FIG. 104, and the sub-matrix [Q2 ^t ₄₄ ] is defined as shown in FIG.

The matrix [Q3 ^t ] in the equation (7) is shown in FIG.
As shown in 06, four 8x8 submatrixes [Q
3 ^t ₁₁ ], [Q3 ^t ₂₂ ], [Q3 ^t ₃₃ ], [Q3 ^t ₄₄ ]
And all other factors are zero. Small line [Q3 ^t ₁₁ ]
107, the small matrix [Q3 ^t ₂₂ ] is shown in FIG. 108, the small matrix [Q3 ^t ₃₃ ] is shown in FIG. 109, and the small matrix [Q3 ^t ₄₄ ] is shown in FIG.
It is defined as 0.

The matrix [Q4 ^t ] in equation (7) is as shown in FIG.
As shown in FIG. 11, four 8 × 8 sub-matrices [Q
4 ^t ₁₁ ], [Q4 ^t ₂₂ ], [Q4 ^t ₃₃ ], [Q4 ^t ₄₄ ]
And all other factors are zero. Small line [Q4 ^t ₁₁ ]
112, the small matrix [Q4 ^t ₂₂ ] is shown in FIG. 113, the small matrix [Q4 ^t ₃₃ ] is shown in FIG. 114, and the small matrix [Q4 ^t ₄₄ ] is shown in FIG.
It is defined as 5.

The calculation of the matrix composed of the factors 0, 1, -1 may be performed by the addition process for the factor 1 and the subtraction process for the factor -1, so that the addition / subtraction circuit can be used and the multiplication circuit is not required. Therefore, in the calculations shown in the above equations (6) and (7), it is sufficient to perform multiplication only on the matrix [R] including the irrational number and its transposed matrix [R ^t ]. Since the matrix [R] and the matrix [R ^t ] each have at most four irrational factors in each row, the number of irrational multiplications required when performing an operation by multiplying the matrix [R] and the matrix [R ^t ] Is at most 4 times for each factor.

The 8 × 8 discrete cosine transform circuit of the present invention is
A first addition / subtraction circuit that performs addition / subtraction corresponding to an inner product of the first constant matrix [Q1] and the input data in matrix form; and the first constant matrix [Q1] and the operation result in the first addition / subtraction circuit. A second addition / subtraction circuit for performing addition / subtraction corresponding to the inner product operation of the above, and a first addition / subtraction corresponding to an inner product operation of the second constant matrix [Q2] and the operation result in the second addition / subtraction circuit; Second addition / subtraction corresponding to the inner product operation of the constant matrix [Q3] of the above and the operation result of the first addition / subtraction, and the inner product of the fourth constant matrix [Q4] and the operation result of the second addition / subtraction A third adder / subtractor circuit for performing a third adder-subtractor corresponding to the operation, the fifth matrix [R],
And a multiplication / addition circuit for performing multiplication / addition corresponding to inner product calculation with the calculation result in the third addition / subtraction circuit.

The 8 × 8 discrete cosine inverse transform circuit is
A multiply-add circuit that performs a multiply-add operation corresponding to an inner product of the first matrix [R ^t ] and the input data in a matrix format, the second constant matrix [Q4 ^t ] and the operation result in the multiply-add circuit. A second addition / subtraction corresponding to an inner product operation, a second addition / subtraction corresponding to an inner product operation of the third constant matrix [Q3 ^t ] and the operation result of the first addition / subtraction, and the fourth constant matrix. A first addition / subtraction circuit that performs a third addition / subtraction corresponding to an inner product operation of [Q2 ^t ] and the operation result of the second addition / subtraction, the fifth constant matrix [Q1 ^t ], and the first A second addition / subtraction circuit that performs addition / subtraction corresponding to an inner product operation with the operation result in the addition / subtraction circuit, and the fifth constant matrix [Q1
^t ] and a third addition / subtraction circuit that performs addition / subtraction corresponding to an inner product operation of the operation result in the second addition / subtraction circuit.

Further, regarding circuits for performing discrete cosine transform and discrete cosine inverse transform other than the above-mentioned two-dimensional 8x8 discrete cosine transform and two-dimensional 8x8 discrete cosine inverse transform, for example, the transform matrix of the discrete cosine transform and the discrete cosine inverse transform is used. Is decomposed into a constant matrix whose factors are +1, -1 or 0 and a matrix containing irrational numbers defined by the discrete cosine transform, and the arithmetic operation is performed using the adder-subtractor circuit and the multiply-add circuit, respectively. Reduce the number of multiplications in matrices containing numbers.

[0025]

The two-dimensional 8 × 8 discrete cosine transform circuit of the present invention calculates the equation 6 in the following six steps.

[Equation 5]

At this time, the multiplication is performed only in step 6 when the matrix [R] having at most four irrational factors in each column is multiplied, and the multiplication is performed only at most four times to obtain each factor of the output data. Is done. In addition, the data path for obtaining each factor includes only one multiplication. The two-dimensional 8 × 8 discrete cosine transform circuit of the present invention includes a calculation of step 1 as a first addition / subtraction circuit, a calculation of step 2 as a second addition / subtraction circuit, and a calculation of steps 3, 4, and 5 as a third addition / subtraction circuit. , Step 6 is performed using a multiplication / addition circuit.

The two-dimensional 8 × 8 discrete cosine inverse transform circuit of the present invention calculates the equation 7 in the following six steps.

[Equation 6]

At this time, the multiplication is performed only in step 1 when the matrix [R ^t ] having at most four irrational factors in each column is multiplied, and only at most four times are required to obtain each factor of the output data. Multiplication is performed. In addition, the data path for obtaining each factor includes only one multiplication. 2 of the present invention
The dimension 8 × 8 discrete cosine inverse transform circuit includes a calculation of step 1 for a multiplication / addition circuit, a calculation of steps 2, 3, and 4 as a first addition / subtraction circuit, a calculation of step 5 as a second addition / subtraction circuit, and a calculation for step 6. Is performed using the third adder / subtractor circuit.

[0029]

[Embodiment] Two-dimensional 8 for performing time division processing according to an embodiment of the present invention
x8 discrete cosine transform (two-dimensional 8x8 DCT) circuit and two-dimensional 8x8 inverse discrete cosine transform (8x8IDCT)
The circuit will be described.

A two-dimensional 8 × 8 DCT circuit will be described. FIG. 1 shows a block diagram of a two-dimensional 8 × 8 DCT circuit. The two-dimensional 8 × 8 DCT circuit 1 shown in FIG. 1 performs the operation defined by the equation (6) by using three addition / subtraction circuits and one multiplication / addition circuit in six steps of the following equations (8) to (13). .

[Equation 7]

[Q1], [Q2], [Q3], [Q
4] and [R] are the same as previously defined. In addition, [x] is all the elements (64
Vector). [Y] is a vector obtained by converting [x] into a frequency space, and is a vector composed of 64 elements.

As shown in FIG. 1, the two-dimensional 8 × 8 DCT circuit 1 includes an input register 2, a first addition / subtraction circuit 3, a first intermediate value holding circuit 4, a second addition / subtraction circuit 5, and a second intermediate value holding. It is composed of a circuit 6, a third addition / subtraction circuit 7, a third intermediate value holding circuit 8, a multiplication / addition circuit 9, and an output register 10. The first addition / subtraction circuit 3 is the first stage, the second intermediate value holding circuit 5 is the second stage, the second intermediate value holding circuit 6 is the second stage, and the second intermediate value holding circuit 6 is the third addition / subtraction circuit 7. Is a third stage, and a multiplication / addition circuit 9 is a fourth stage via a third intermediate value holding circuit 8.

The input register 2 inputs the original data [x] in word serial every clock cycle. Since the original data [x] consists of 64 elements, it is necessary to store all the data of the original data [x] in the input register 2 with 6 elements.
It takes 4 clock cycles. The first adder / subtractor circuit 3 performs the calculation of step 1. The first intermediate value holding circuit 4 temporarily holds the calculation result of the first addition / subtraction circuit 3. Second
The adder / subtractor circuit 5 performs the calculation in step 2. The second intermediate value holding circuit 6 temporarily holds the calculation result of the second addition / subtraction circuit 5. The third adder / subtractor circuit 7 performs step 3,
The calculation of step 4 and step 5 is performed. The third intermediate value holding circuit 8 temporarily holds the calculation result of the third addition / subtraction circuit 7. The multiplication / addition circuit 9 performs the calculation in step 6. The output register 10 outputs the data [y] in the frequency space word-serially for each clock cycle.

Hereinafter, for the sake of simplicity, it is assumed that one addition, subtraction, and multiplication / addition are completed in one clock cycle, and the first addition / subtraction circuit 3, the second addition / subtraction circuit 5, and the third addition / subtraction circuit 7 are performed.
The multiplication and addition circuit 9 completes the predetermined addition and subtraction and multiplication and addition within 64 clock cycles. for that reason,
The input data input to the input register 2 words serially is pipelined and output from the output register 10 word serially.

Description of Operation in Step 1 In step 1, the coefficient is 1 for the original data [x],
-1 or 0, which is the constant matrix [Q
1] is calculated. Vectors [s] and [x] in the calculation formula [s] = [Q1] [x] of step 1 are defined as follows.

[Equation 8]

The calculation of step 1 is shown in the following equations (14) to (21).

[Equation 9]

The calculation in step 1 is performed by one adder 1
The time division method is performed using the first adder / subtractor circuit 3 having one unit adder / subtractor circuit 12 which is composed of 5 and one subtractor 16.

FIG. 2 shows a basic block diagram of the unit addition / subtraction circuit 12. As shown in FIG. 2, the unit addition / subtraction circuit 12 includes a pair of adders 15 and subtractors 16. Input data a
And b are input to both the adder 15 and the subtractor 16, the adder 15 outputs the addition result (a + b) of a and b, and the subtracter 16 outputs the subtraction result (ab) of a and b. Output.

Using the first adder / subtractor circuit 3, the above equation (1
4)-(21) will be described. FIG. 3 shows a signal flow graph for the calculation of equations (14) to (21). The first adder / subtractor circuit 3 performs (1) addition and subtraction of the inputs x _8i and x _{8i + 7} using a pair of adder 15a and subtractor 16a in one clock cycle, and the adder 15a Addition result (x _8i + x
_{8i + 7} ), and the subtractor 16a outputs the subtraction result (x _8i −x
_{8i + 7} ) is output. At this time, the output of the subtractor 16a (x _8i
−x _{8i + 7} ) becomes s _{i + 56} . (2) In two clock cycles, addition and subtraction of the inputs x _{8i + 1} and x _{8i + 6} are performed using the pair of adder 15b and subtractor 16b, and the adder 15b outputs the addition result (x _{8i + 1} +
x _{8i + 6} ) and the subtractor 16b outputs the subtraction result (x _{8i + 1}
-X _{8i + 6} ) is output. At this time, the output (x _{8i + 1} −x _{8i + 6} ) of the subtractor 16b becomes s _{i + 48} . (3) In 3 clock cycles, addition and subtraction of the inputs x _{8i + 2} and x _{8i + 5} are performed using the pair of adder 15c and subtractor 16c, and the adder 15c outputs the addition result (x _{8i + 2} +
x _{8i + 5} ) is output, and the subtractor 16c outputs the subtraction result (x _{8i + 2}
-X _{8i + 5} ) is output. At this time, the output (x _{8i + 2} −x _{8i + 5} ) of the subtractor 16c becomes s _{i + 40} . (4) In 4 clock cycles, addition and subtraction of the inputs x _{8i + 3} and x _{8i + 4} are performed using the pair of adder 15d and subtractor 16d, and the adder 15d outputs the addition result (x _{8i + 3} +
x _{8i + 4} ) is output, and the subtractor 16d outputs the subtraction result (x _{8i + 3}
-X _{8i + 4} ) is output. At this time, the output (x _{8i + 3} −x _{8i + 4} ) of the subtractor 16d becomes s _{i + 32} .

(5) In 5 clock cycles, a pair of adder 15e and subtractor 16e are used to input (x _8i + x
_{8i + 7} ) and ( _{x8i + 3} + _{x8i + 4} ) are added and subtracted, and the adder 15e outputs the addition result ( _x8i + _{x8i + 7} + _{x8i + 3).}
+ X _{8i + 4} ), and the subtractor 16e outputs the subtraction result (x _8i
+ X _{8i + 7} −x _{8i + 3} −x _{8i + 4} ) is output. At this time, the output ( _x8i + _{x8i + 7- x8i + 3- x8i + 4} ) of the subtractor 16e is s.
_{i + 24} . (6) In 6 clock cycles, a pair of adder 15f and subtractor 16f are used to input (x _{8i + 1} + x _{8i + 6} ) and (x _{8i + 1} + x _{8i + 6} )
_{8i + 2} + x _{8i + 5} ) and performs addition and subtraction,
f outputs the addition result (x _{8i + 1} + x _{8i + 6} + x _{8i + 2} + x _{8i + 5} ), and the subtractor 16f outputs the subtraction result (x _{8i + 1} + x _{8i + 6} −
x _{8i + 2} −x _{8i + 5} ) is output. At this time, the output of the subtractor 16f ( _{x8i + 1} + _{x8i + 6- x8i + 2- x8i + 5} ) becomes _{si + 16} . (7) In 7 clock cycles, input (x _8i + x _{8i + 7} + x _{8i + 3} +) using a pair of adder 15g and subtractor 16g
x _{8i + 4} ) and (x _{8i + 1} + x _{8i + 6} + x _{8i + 2} + x _{8i + 5} ) are added and subtracted, and the adder 15g calculates the addition result as (x
_8i + x _{8i + 7} + x _{8i + 3} + x _{8i + 4} + x _{8i + 1} + x _{8i + 6} + x _{8i + 2}
+ X _{8i + 5} ) is output, and the subtracter 16g outputs the subtraction result (x _{8i + 5} ).
+ X _{8i + 7} + x _{8i + 3} + x _{8i + 4} −x _{8i + 1} −x _{8i + 6} −x _{8i + 2} −
x _{8i + 5} ) is output. At this time, the output (x
_8i + x _{8i + 7} + x _{8i + 3} + x _{8i + 4} + x _{8i + 1} + x _{8i + 6} + x _{8i + 2}
+ X _{8i + 5} ) becomes s _i , and the output of the subtractor 16g (x _8i +5
x _{8i + 7} + x _{8i + 3} + x _{8i + 4} −x _{8i + 1} −x _{8i + 6} −x _{8i + 2} −x
_{8i + 5} ) becomes s _{i + 8} .

As described above, the eight elements (s _i , s _{i + 8} , s _{i + 16} , s _{i + 24} , s _{i + 32} , s _{i + 40} , s) of the vector [s] are
The calculation of the equations (14) to (21) for obtaining _{i + 48} , s _{i + 56} ) is performed using the unit addition / subtraction circuit 12 of the addition / subtraction circuit 3 seven times. Therefore, all elements (64
Number) is obtained by using the unit addition / subtraction circuit 12 7 times × 8 = 56 times. The calculation in step 1 is performed by the first addition / subtraction circuit 3
For 56 clock cycles, and the output vector [s] (64 elements) is written to the first intermediate value holding circuit 4.

Description of Operation in Step 2 In step 2, the vector [s] held in the first intermediate value holding circuit 4 after the processing in step 1 is performed is further multiplied by a constant matrix [Q1]. To do. The vector [t] in the calculation formula [t] = [Q1] [s] of step 2 is determined as follows.

[Equation 10] [S] is the same as that defined in step 1.

The calculation of step 2 is shown in the following equations (22) to (29).

[Equation 11] The calculation of step 2 is performed by the second addition / subtraction circuit 5.
The second adder / subtractor circuit 5 is the same as the first adder / subtractor circuit 3. The calculation of the above formulas (22) to (29) can be described by the signal flow graph shown in FIG. The signal flow graph of FIG. 4 is the same as the signal flow graph shown in FIG. 3 of step 1 described above. Therefore, the eight elements (t _i , t _{i + 8} , t _{i + 16} , t _{i + 24} , t of the vector [t] are
_{i + 32} , t _{i + 40} , t _{i + 48} , t _{i + 56} ) Expression 22 to Expression 2
The calculation of 9 is performed using the unit addition / subtraction circuit 12 described above seven times. Therefore, all elements (6
4) is obtained by using the unit addition / subtraction circuit 12 7 times × 8 = 56 times. The calculation in step 2 is performed by using the second addition / subtraction circuit 5 having one unit addition / subtraction circuit 12 over 56 clock cycles, and the output vector [t] (64 elements) is stored in the second intermediate value holding circuit 6. Written.

Description of operation of step 3 In step 3, the vector [t] held in the second intermediate value holding circuit 6 after the processing of step 2 is performed is applied to the constant matrix [Q2 defined in claim 2]. ] Is calculated. The vector [u] in the calculation formula [u] = [Q2] [t] of step 3 is defined as follows.

[Equation 12] [T] is the same as that determined in step 2.

The calculation of step 3 is shown in the following equations (30) to (93).

[Equation 13]

[0046]

[Equation 14]

[0047]

[Equation 15]

[0048]

[Equation 16]

[0049]

[Equation 17]

[0050]

[Equation 18]

The calculation in step 3 is performed in a time division manner by using the third addition / subtraction circuit 7 having the same configuration as the first addition / subtraction circuit 3. Since each calculation of the equations (34) to (93) can be performed by using the unit addition / subtraction circuit 12 of the third addition / subtraction circuit 7 once, all calculations of the equations (34) to (93) are performed. , The unit addition / subtraction circuit 12 is used 30 times. No special circuit is required for each calculation of Expression (30) to Expression (33). Therefore, all elements of vector [u] (64)
Is calculated using the unit addition / subtraction circuit 12 30 times. Therefore, the calculation of step 3 is performed by one unit addition / subtraction circuit 12
30 clock cycles using the third adder / subtractor circuit 7 having

Description of operation of step 4 In step 4, for the vector [u] calculated in step 3, the constant matrix [Q3] defined in claim 2 is defined.
Calculate by multiplying by. The vector [v] in the calculation formula [v] = [Q3] [u] of step 4 is defined as follows.

[Formula 19] [U] is the same as that defined in step 3.

The calculation of step 4 is shown in the following equations (94) to (157).

[Equation 20]

[0054]

[Equation 21]

[0055]

[Equation 22]

[0056]

[Equation 23]

[0057]

[Equation 24]

[0058]

[Equation 25]

The calculation in step 4 is performed by the time division method using the third addition / subtraction circuit 7 used in the calculation in step 3. Formula (107), Formula (108), Formula (126)-
Each calculation of Expression (157) is performed using the third addition / subtraction circuit 7 once. Therefore, all calculations of Expression (107), Expression (108), Expression (126) to Expression (157) are
The third addition / subtraction circuit 7 is used 17 times. Expression (9
4) to formula (106) and formula (109) to formula (125)
Does not require any special calculation and does not require any special circuit. Therefore, all the elements (64) of the vector [v] are obtained by using the unit addition / subtraction circuit 12 of the third addition / subtraction circuit 7 17 times. Therefore, the calculation in step 4 is performed using the third addition / subtraction circuit 7 in 17 clock cycles.

Description of operation of step 5 In step 5, for the vector [v] calculated in step 4, the constant matrix [Q4] defined in claim 2 is defined.
Calculate by multiplying by. The vector [w] in the calculation formula [w] = [Q4] [v] of step 5 is defined as follows.

[Equation 26] [V] is the same as that defined in Step 4.

The calculation in step 5 is shown in the following equations (158) to (221).

[Equation 27]

[0062]

[Equation 28]

[0063]

[Equation 29]

[0064]

[Equation 30]

[0065]

[Equation 31]

[0066]

[Equation 32]

The calculation in step 5 is performed in a time division manner by using the third addition / subtraction circuit 7 used in the calculations in steps 3 and 4. Expression (210) to Expression (221)
Each calculation of is performed using the third addition / subtraction circuit 7 once. Therefore, all the calculations of Expressions (210) to (221) are performed by using the unit addition / subtraction circuit 12 of the third addition / subtraction circuit 7 by six.
It is performed by using it again. Equations (158) to (209) do not require any particular calculation and need not be provided with a special circuit.

Therefore, all the elements of the vector [w] (64
6) is the unit addition / subtraction circuit 12 of the third addition / subtraction circuit 7.
It is calculated by using it again. Therefore, the calculation in step 5 is
This is performed in 6 clock cycles using the third adder / subtractor circuit 7. As described above, the calculation of step 3, step 4 and step 5 is performed by using the third adder / subtractor circuit 7.
0 + 17 + 6 = 53 clock cycles, and the output vector [w] (64 elements) is the third intermediate value holding circuit 8
Written in.

Description of Operation of Step 6 In step 6, for the vector [w] held in the third intermediate value holding circuit 8 after the processing of step 5 is performed, at most each column defined in claim 4 A calculation is performed by multiplying a matrix [R] having four irrational factors. The vector [y] in the calculation formula [y] = 1/32 [R] [w] of step 6 is defined as follows.

[Expression 33] [W] is the same as that determined in step 5.

The calculation of step 6 is shown in the following equations (222) to (285). However, although the calculation result of [R] [w] is finally multiplied by 1/32 in the calculation formula of step 6, this calculation may be performed by shifting the output of [R] [w] by 5 bits to the right. Therefore, the circuit does not require a multiplication circuit or a division circuit.

[Equation 34]

[0071]

[Equation 35]

[0072]

[Equation 36]

[0073]

[Equation 37]

[0074]

[Equation 38]

[0075]

[Formula 39]

The calculation in step 6 is performed by the multiplication / addition circuit 9. FIG. 5 shows a configuration diagram of the multiplication / addition circuit 9. The multiplication / addition circuit 9 includes a multiplication unit 20, a multiplication unit 21, and a multiplication unit 22. The multiplication unit 21 includes a multiplier 30, an accumulator 32, and a coefficient storage memory 34. The multiplication unit 22
It has the same configuration as the multiplication unit 21, and includes a multiplication unit 22 and a multiplication unit 2.
Since 1 uses the same coefficient for calculation, the coefficient storage memory 34 can be configured to be shared. The multiplication unit 20 includes a multiplier 30, a first accumulator 32a, a second accumulator 32b, and a coefficient storage memory 36.

The multiply-add circuit 9 has a certain clock cycle k.
At, the input data is input to the multiplier 21, the multiplier 22, or the multiplier 30 of the multiplier 20. The multipliers 30 of the multiplication unit 21 and the multiplication unit 22 receive the input data and the coefficient D recorded in the coefficient storage area 34 a of the coefficient storage memory 34,
The coefficient E recorded in the coefficient storage area 34b, the coefficient F recorded in the coefficient storage area 34c, or the coefficient G recorded in the coefficient storage area 34d is multiplied to obtain a multiplication result as a signal S30.
Is output to the accumulator 32. The accumulator 32 is the multiplier 3
The multiplication result input from 0 to the signal S30 and the multiplication result input from the multiplier 30 in the previous clock cycle (k-1) are added or subtracted, and the addition / subtraction result is S
Output as 32. Therefore, the multiplication unit 21 and the multiplication unit 22 can realize an nth-order inner product operation in n clock cycles.

The multiplier 30 of the multiplication unit 20 records the input data and the coefficient A recorded in the coefficient storage area 36a of the coefficient storage memory 36, the coefficient B recorded in the coefficient storage area 36b, or the coefficient storage area 36c. The coefficient C is multiplied and the multiplication result is output as a signal S30 to the accumulators 32a and 32b. Accumulator 32a and accumulator 32
b is the multiplication result input as the signal S30 from the multiplier 30 and the multiplier 30 in the previous clock cycle (k-1).
The addition or subtraction is performed with the multiplication result input from, and the addition / subtraction result is output as S32. The multiplication unit 20
Since the two accumulators 32a and 32b are provided, it is possible to perform two different accumulation operations on the same multiplication result.

The calculation of equations 222 to 285 in step 6 is performed by multiplying section 20, multiplying section 21 and multiplying section 2 of multiplying and adding circuit 9.
The procedure performed in 2 will be described. The multiplication unit 21 uses the equation (223) of the fourth-order inner product operation including the coefficients D, E, F, and G,
(225), (227), (229), (230),
(234), (246), (250), (255),
(257), (259), (261), (262),
Calculation of (266), (278), and (282) is performed. Since each expression is a quadratic inner product calculation expression, the multiplication unit 21 executes each expression in four clock cycles. Therefore, the multiplication unit 21 performs these 16 expressions in 4 × 16 = 64 clock cycles.

The multiplication section 22 uses the equations (232), (236), (23) of the fourth-order inner product operation including the coefficients D, E, F, G.
9), (241), (243), (245), (24
8), (252), (264), (268), (27
1), (273), (275), (277), (28
0) and (284) are calculated. Since each expression is a quadratic inner product calculation expression, the multiplication unit 22 performs each expression in four clock cycles. Therefore, the multiplication unit 22 performs these 16 equations in 4 × 16 = 64 clock cycles as in the multiplication unit 21.

The multiplication unit 20 uses the equations (224), (228), (238), (2) of the quadratic inner product operation including the coefficients B and C.
42), (256), (260), (270), (27
4), a fourth-order inner product calculation formula (23 including the coefficients A, B, and C)
1), (233), (235), (237), (24
7), (249), (251), (253), (26
3), (265), (267), (269), (27
9), (281), (283), (285), and
Expressions (240), (24) of the quadratic inner product operation including the coefficient A
4), (272) and (276) are performed.

The eight expressions of the quadratic inner product operation including the coefficients B and C are 2 × 8 = using only the accumulator 32a of the multiplication unit 20.
It takes 16 clock cycles. The 16 equations of the 4th-order inner product calculation including the coefficients A, B, and C are performed using the accumulators 32a and 32b of the multiplication unit 20. At this time, for example, the calculation of equation (231) and equation (285) are both multiplication results 1 · w ₄₈ , b · w ₅₇ , a · w ₆₁ , c · w.
₆₃ is required, and its accumulation procedure (addition / subtraction procedure) is different. Therefore, equation (231) and equation (285)
Is calculated by the accumulator 32a and the accumulator 32 of the multiplication unit 20.
4 clock cycles using b. Similarly, equation (23
3) and equation (283), equation (235) and equation (28
1), formula (237) and formula (279), formula (247)
And equation (269), equation (249) and equation (26
7), formula (251) and formula (265), formula (253)
Also, the calculation of Expression (263) is also performed in the multiplication unit 20 in four clock cycles. Therefore, the coefficients A, B, C
The 16 equations of the fourth-order inner product operation including
× 8 = 32 clock cycles.

Similarly, for the four expressions of the quadratic inner product operation including the coefficient A, the accumulators 32a and 32b of the multiplication unit 20 are also included.
Using. For example, equation (240) and equation (27
The calculation of 6) requires the multiplication results w ₁₂ and a · w ₁₄ in all cases, and only the accumulation procedure (addition / subtraction procedure) is different. Therefore, the calculation of Expression (240) and Expression (276) is performed in two clock cycles using the accumulators 32a and 32b of the multiplication unit 20. Therefore, the four expressions of the quadratic inner product operation including the coefficient A are 2 × 2 =
It takes 4 clock cycles. In this way, the multiplication unit 2
16 of fourth-order inner product operation including coefficients A, B, and C using 0
4 equations of the quadratic inner product including 32 equations and the coefficient A are performed in 32 + 4 = 36 clock cycles. Note that equation (222), equation (226), equation (254), and equation (25
In 8), it is not necessary to perform calculation, and no special circuit is needed.

As described above, the calculation in step 6 is performed using the multiplying / adding circuit 9 in 64 clock cycles, and the output vector [y] (64 elements) is output from the output register 10.
Written word serially.

Thus, the two-dimensional 8 × 8 DCT of this embodiment is
In the circuit 1, the number of multiplications required when calculating the data [y] (64 elements) on the frequency by performing the two-dimensional 8 × 8 DCT calculation is only 180 performed in step 6, and the multiplication and addition are completed in one clock cycle. In this case, the multiplication / adder is required to have three multiplication units 20, 21, and 22, and the circuit configuration is simple. Further, since the data path includes only one multiplication, it is possible to prevent the accumulation of rounding errors and the accumulation of calculation errors due to approximation of irrational numbers, and it is possible to obtain a highly accurate calculation result.

As a hardware circuit for realizing the two-dimensional 8 × 8 DCT circuit of the present invention, an electronic circuit for performing the above arithmetic processing, a DSP (digital signal processor),
A circuit or the like using a semiconductor device can be considered. Such an implementation circuit configuration is also applied to the 8 × 8 IDCT circuit described below.

Next, a two-dimensional 8x8 IDCT for performing the inverse operation of the above two-dimensional 8x8 DCT circuit will be described. Figure 6
The block diagram of the two-dimensional 8 × 8 IDCT 51 is shown in FIG. The two-dimensional 8 × 8 IDCT 51 shown in FIG. 6 performs the operation defined by the above equation 7 by using one multiplication / addition circuit and three addition / subtraction circuits in six steps of the following equations (286) to (291).

[Formula 40] [Q1 ^t), (Q2 ^t), (Q3 ^t), (Q4 ^t],
[R ^t ] is the same as previously defined. [X] and [y] are all the elements (64) of the original data [X] of 8x8, respectively, as in the case of the two-dimensional 8x8 DCT described above.
And a vector composed of 64 elements obtained by converting [x] into a frequency space.

As shown in FIG. 6, a two-dimensional 8 × 8 IDCT
Reference numeral 51 denotes an input register 52, a multiplication / addition circuit 53, a first intermediate value holding circuit 54, a first addition / subtraction circuit 55, a second intermediate value holding circuit 56, a second addition / subtraction circuit 57, and a third intermediate value holding. It is composed of a circuit 58, a third addition / subtraction circuit 59 and an output register 60. In the two-dimensional 8 × 8 IDCT 51, the multiplication / addition circuit 53 is in the first stage, the first addition / subtraction circuit 55 is in the second stage via the first intermediate value holding circuit 54, and the second intermediate value holding circuit 56 is in the second stage. Adder / subtractor circuit 57
The third adder / subtractor circuit 59 has a fourth stage via the intermediate value holding circuit 58.

The input register 52 inputs the data [y] on the frequency in word serial every clock cycle. Since the data [y] on the frequency consists of 64 elements, it takes 64 clock cycles for all the data on the frequency to be aligned in the input register 52. Multiply-adder circuit 53
Performs the process of step 1. First intermediate value holding circuit 5
4 temporarily holds the calculation result of the multiplication and addition circuit 53.
The first adder / subtractor circuit 55 performs the processing of step 2, step 3 and step 4. Second intermediate value holding circuit 56
Holds the calculation result of the first addition / subtraction circuit 55 temporarily. The second addition / subtraction circuit 57 performs the process of step 5. The third intermediate value holding circuit 58 includes the second addition / subtraction circuit 5
The calculation result of 7 is temporarily held. Third adder / subtractor circuit 5
9 performs the process of step 6. The output register 60 is
The original data [x] is word-serially output every clock cycle. Hereinafter, for simplification, it is assumed that one addition, subtraction, and multiplication / addition are completed in one clock cycle, and the multiplication / addition circuit 53, the first addition / subtraction circuit 55, and the second addition / subtraction circuit 5
The seventh and third adder / subtractor circuits 59 complete predetermined multiplication / addition and addition / subtraction within 64 clock cycles, respectively.

Description of Operation of Step 1 In step 1, for the data [y] on the frequency held in the input register 52, a matrix having at most four irrational factors in each column defined in claim 9 R ^t ]. Formula for step 1 [w ' ] = [R ^t ] [y] vector [w ′ ] Is defined as follows.

[Formula 41] The vector [y] is the same as that defined in step S6 of the two-dimensional 8 × 8 DCT described above. The calculation of step 1 is shown in the following equations (292) to (355).

[0091]

[Equation 42]

[0092]

[Equation 43]

[0093]

[Equation 44]

[0094]

[Equation 45]

[0095]

[Equation 46]

[0096]

[Equation 47]

[0097]

[Equation 48] The calculation in step 1 is performed by the multiplication / addition circuit 53.

FIG. 7 shows a block diagram of the multiply-add circuit 53. The multiplication / addition circuit 53 includes a multiplication unit 70, a multiplication unit 71, and a multiplication unit 72. The multiplication unit 70 uses the above 8 × 8DC
The adder / subtractor 74 is added to the multiplication unit 20 of the T circuit 1, and the two input signals S74b and S74b are added or subtracted by the adder / subtractor 74, and the addition result or the subtraction result is output to the multiplier 30. . Multiplier 71 and multiplier 7
2 is the same as the multiplying unit 21 and the multiplying unit 22 of the 8 × 8 DCT circuit 1.

Expressions (292) to (355) of step 1
A procedure for performing the calculation of 1 in the multiplication unit 70, the multiplication unit 71, and the multiplication unit 72 of the multiplication and addition circuit 53 will be described. Multiplication unit 71
Is a fourth-order inner product arithmetic expression (3 that includes coefficients D, E, F, and G).
08) to formula (323) are calculated. Since each expression is a quadratic inner product operation, the multiplication unit 71 performs each expression in 4 clock cycles. Therefore, the multiplication unit 71 performs these 16 expressions in 4 × 16 = 64 clock cycles.

The multiplication section 72 calculates the equations (324) to (355) of the fourth-order inner product operation including the coefficients D, E, F and G. Since each expression is a quadratic inner product operation, the multiplication unit 72 performs each expression in 4 clock cycles. Therefore, the multiplication unit 7
2 performs these 16 equations in 4 × 16 = 64 clock cycles.

The multiplication section 70 uses the expressions (296) to (307) of the quadratic and quaternary inner product operations including the coefficients A, B and C,
Equations (340) to (355) are calculated. Among these calculation formulas, formulas (296) to (303) are calculated by the multiplication unit 70.
8 × 8 using the above multiplier 30 and accumulator 32
The calculation is performed in the same manner as the multiplication unit 20 of the DCT circuit 1.

The equations (304) to (307) and the equations (340) to (355) are calculated using the adder / subtractor 74, the multiplier 30 and the accumulator 32 of the multiplication unit 70.
For example, the calculation of equation (340) and equation (349) is
First, the addition (subtraction) result (y ₉ + y
_{63), (y 9 -y 63} ), (y 27 + y 45), (y 27 -
y ₄₅ ) is calculated in 4 clock cycles. Next, multiplier 3
Using 0, the multiplication result 1 · (y ₉ + y ₆₃ ), b · (y ₉
−y ₆₃ ), 1 · (y ₂₇ + y ₄₅ ), c · (y ₂₇ −y ₄₅ ) are calculated in 4 clock cycles. Further, by using the accumulator 32, two accumulation results (y ₉ + y ₆₃ ) + (y ₂₇ + y ₄₅ ), b · (y ₉ −y) are obtained in 2 + 2 = 4 clock cycles.
₆₃ ) + c · (y ₂₇ −y ₄₅ ) is calculated.

Similar to equations (340) and (349), equations (341) and (345), equations (342) and (344), equations (343) and (348),
Formula (346) and formula (351), formula (347) and formula (350), formula (352) and formula (354), formula (353) and formula (355) can also be calculated, and pipeline processing can be performed. The calculation result can be obtained every 4 clock cycles. Further, the calculation of Expression (304) and Expression (306), Expression (305) and Expression (307) can be performed in two clock cycles using the multiplication unit 70. Further, the equations (292) to (295) do not require any particular calculation, and no special circuit is required.

Therefore, the multiplication unit 70 uses the equations (296) to
All calculations of Expression (307), Expression (340) to Expression (355) can be performed in 4 × 8 + 2 × 2 = 36 clock cycles. In this way, the calculation in step 1 is performed in 64 clock cycles using the multiplying / adding circuit 53, and the output vector [w ′] (64 elements) is written in the first intermediate value holding circuit 54.

Description of Operation of Step 2 In step 2, for the vector [w '] held in the first intermediate value holding circuit 54 after the processing of step 1 is performed, the constant matrix [defined in claim 7 perform the calculations multiplying the Q4 ^t]. Step stipulated 2 equation a [v '] = [Q4 ^t] [w'] To finish the vector [v '] as follows.

[Equation 49] [W ′] is the same as that defined in step 1.

The calculation formula of step 2 is expressed by the following formula (356)-
It is shown in Expression (419).

[0107]

[Equation 50]

[0108]

[Equation 51]

[0109]

[Equation 52]

[0110]

[Equation 53]

[0111]

[Equation 54]

[0112]

[Equation 55]

The calculation in step 2 is performed in a time division manner using the first addition / subtraction circuit 55. The first addition / subtraction circuit 55 has the same configuration as the first addition / subtraction circuit 3 of the 8 × 8DCT circuit 1, and has a unit addition / subtraction circuit 12 including one adder 15 and one subtractor 16 inside. Have one.

Of the expressions (356) to (419), the expression (4
05) -expression (409), expression (411), expression (413)-
The calculation of the equation (418) is performed using the unit addition / subtraction circuit 12 of the first addition / subtraction circuit 55 six times. Expression (356) to Expression (4
04), formula (410), formula (412), formula (419)
Requires no special calculation and does not require any special circuit. Therefore, the calculation in step 2 is performed using the first adder / subtractor circuit 55 over 6 clock cycles to obtain the vector [v '] (64 elements).

Description of Operation of Step 3 In step 3, the constant matrix [Q3 defined in claim 7 is defined for the vector [v '] calculated in step 2.
^t ]] is calculated. Step 3 formula [u '] = [Q3 ^t] [v' vector in] a [u '] defined as follows.

[Equation 56] [V ′] is the same as that defined in step 2.

The calculation formula of step 3 is expressed by the following formula (420)-
It is shown in Expression (483).

[Equation 57]

[0117]

[Equation 58]

[0118]

[Equation 59]

[0119]

[Equation 60]

[0120]

[Equation 61]

[0121]

[Equation 62] The calculation in step 3 is performed in a time division manner using the first adder / subtractor circuit 55 as in step 2.

Of the expressions (420) to (483), the expression (4
33), formula (434) and formula (452) to formula (48).
3) is calculated by the unit adder / subtractor 1 of the first adder / subtractor circuit 55.
2 using 17 times. Also, equations (420) to (43)
2) and equations (435) to (451) do not require any particular calculation and no special circuit is required. Therefore, the calculation in step 3 is performed in 17 clock cycles using the second adder / subtractor circuit 5, and all elements (6
4 pieces) is required.

Description of Operation in Step 4 In step 4, the constant matrix [Q] defined in claim 7 is applied to the vector [u '] calculated in step 3.
2 ^t ]. Step 4 of formula [t '] = [Q2 ^t] [u' vector [t '] in] determined as follows.

[Equation 63] [U ′] is the same as that defined in step 3.

The calculation in step 4 is shown in the following equations (484) to (547).

[Equation 64]

[0125]

[Equation 65]

[0126]

[Equation 66]

[0127]

[Equation 67]

[0128]

[Equation 68]

[0129]

[Equation 69]

The calculation in step 4 is performed in a time division manner using the first addition / subtraction circuit 55 as in step 3. Expression (486) -of Expression (484) -Expression (547)
The calculation of Expression (491), Expression (494) to Expression (547) is
The unit addition / subtraction circuit 12 of the first addition / subtraction circuit 55 is performed 30 times, and the equations (420) to (432) and (43) are used.
The calculations of 5) to (451) do not require special calculations and do not need to be provided with a special circuit. Therefore, step 4
Is calculated in 30 clock cycles by the first adder / subtractor circuit 55, and all elements (64
Are output to the second intermediate value holding circuit 56.

Step 2, Step 3 and Step 4
As described above, the calculation of step 2, step 3 and step 4 is performed by using the first addition / subtraction circuit 55 as 6 (step 2) +17 (step 3) +30 (step 4).
= 53 clock cycles.

Description of Operation of Step 5 In step 5, for the vector [t '] held in the second intermediate value holding circuit 56 after the processing of step 4 is performed, the constant matrix [defined in claim 7 Q1 ^t ] is calculated. Step formula 5 [s'] = [Q1 ^t] [t 'vector [s'] in] determined as follows.

[Equation 70] [T '] is the same as that defined in step 4.

The calculation of step 5 is shown in the following equations (548) to (555).

[Equation 71]

The calculation in step 4 is performed by the second addition / subtraction circuit 5
7 is used. The second addition / subtraction circuit 57 is the same as the above-mentioned first addition / subtraction circuit 55, and has one unit addition / subtraction circuit 12 inside. The signal processing in the case of performing the calculation of the above formulas (548) to (555) using the second addition / subtraction circuit 57 will be described. Equations (548) to (55) are shown in FIG.
The signal flow graph of 5) is shown. The second adder / subtractor circuit 57 (1) performs addition and subtraction of the inputs t ′ _i and t ′ _{i + 8} using a pair of adder 15 a ′ and subtractor 16 a ′ in one clock cycle, and performs addition. vessel 15a 'is the addition result (t''outputs a _{i + 8,} the subtracter 16a _i + t)' outputs the subtraction result _{(t 'i -t' i +} 8). (2) Input in two clock cycles using a pair of adder 15b 'and subtractor 16b' (t ' _i + t' _{i + 8} )
And t'i _{+ 24} are added to and subtracted from the adder 15a '
Outputs the addition result (t ′ _i + t ′ _{i + 8} + t ′ _{i + 24} ), and the subtractor 16 a ′ outputs the subtraction result (t ′ _i + t ′ _{i + 8} −
t'i _{+ 24} ) is output. (3) in three clock cycles, input using a pair of adders 15c 'and subtractor _{16c' (t 'i -t'} i + 8)
And t'i _{+ 16} are added and subtracted, and the adder 15a '
Outputs the addition result (t ′ _i −t ′ _{i + 8} + t ′ _{i + 16} ), and the subtractor 16 a ′ outputs the subtraction result (t ′ _i −t ′ _{i + 8} −
t ′ _{i + 16} ) is output.

(4) Input (t ′ _i) using a pair of adder 15d ′ and subtractor 16d ′ in 4 clock cycles.
+ T ′ _{i + 8} + t ′ _{i + 24} ) and t ′ _{i + 56} are added and subtracted, and the adder 15d ′ outputs the addition result (t ′ _i + t ′).
_{i + 8} + t ' _{i + 24} + t' _{i + 56} ) is output and the subtracter 16d '
Is the subtraction result (t ' _i + t' _{i + 8} + t ' _{i + 24} −
t'i _{+ 56} ) is output. At this time, the addition result (t ' _i +
_{t 'i + 8 + t'} i + 24 + t 'i + 56) is s' _8i, the subtraction result _{(t' i + t 'i} + 8 + t' i + 24 -t 'i + 56) is s' _{8i + 7}
Becomes (5) Input (t ′ _i −t ′ _{i + 8} +) using a pair of adder 15e ′ and subtractor 16e ′ at 5 clock cycles.
t ′ _{i + 16} ) and t ′ _{i + 48} are added and subtracted, and the adder 15e ′ outputs the addition result (t ′ _i −t ′ _{i + 8} + t ′ _{i + 16).}
+ T ′ _{i + 48} ) and the subtractor 16e ′ outputs the subtraction result (t ′ _i −t ′ _{i + 8} + t ′ _{i + 16} −t ′ _{i + 48} ). At this time, the addition result (t ′ _i −t ′ _{i + 8} + t ′ _{i + 16} +
t _{'i + 48)} is s' _{8i + 1,} the subtraction result _{(t 'i -t' i +} 8 +
t'i _{+ 16-} t'i _{+ 48} ) becomes _{s'8i + 6} .

(6) Input (t ′ _i) using a pair of adder 15f ′ and subtractor 16f ′ in 6 clock cycles.
−t ′ _{i + 8} −t ′ _{i + 16} ) and t ′ _{i + 40} are added and subtracted, and the adder 15f ′ outputs the addition result (t ′ _i −t ′).
_{i + 8} −t ′ _{i + 16} + t ′ _{i + 40} ) and outputs the subtracter 16f ′
Is the subtraction result (t ′ _i −t ′ _{i + 8} −t ′ _{i + 16} −
t'i _{+ 40} ) is output. At this time, the addition result (t ′ _i −
t ′ _{i + 8} −t ′ _{i + 16} + t ′ _{i + 40} ) is s ′ _{8i + 2} , and the subtraction result (t ′ _i −t ′ _{i + 8} −t ′ _{i + 16} −t ′ _{i + 40} ) is _{s'8i + 5}
Becomes (7) Input (t ′ _i −t ′ _{i + 8} −) using a pair of adder 15 g ′ and subtractor 16 g ′ in 7 clock cycles.
t ′ _{i + 24} ) and t ′ _{i + 32} are added and subtracted, and the adder 15g ′ outputs the addition result (t ′ _i −t ′ _{i + 8} −t ′ _{i + 24).}
+ T ′ _{i + 32} ) and the subtractor 16g ′ outputs the subtraction result (t ′ _i −t ′ _{i + 8} −t ′ _{i + 24} −t ′ _{i + 32} ). At this time, the addition result (t ′ _i −t ′ _{i + 8} −t ′ _{i + 24} +
t ′ _{i + 32} ) is s ′ _{8i + 3} , and the subtraction result (t ′ _i −t ′ _{i + 8} −
t'i _{+ 24-} t'i _{+ 32} ) becomes _{s'8i + 4} .

As described above, the eight elements of the vector [s'] ( _s'8i , _{s'8i + 1} , _{s'8i + 2} , _{s'8i + 3} , _{s'8i + 4} ,
Expression (548) for _{obtaining s'8i + 5} , _{s'8i + 6} , _{s'8i + 7} )
The calculation of Expression (555) is performed using the unit addition / subtraction circuit 12 of the second addition / subtraction circuit 57 seven times. Therefore, all the elements (64) of the vector [s ′] are obtained by using the unit addition / subtraction circuit 12 7 × 8 = 56 times. The calculation in step 5 is performed by writing 56 clock cycles using the second adder / subtractor circuit 57, and the output vector [s'] (64
Element) is written in the third intermediate value holding circuit 58.

Description of Operation in Step 6 In step 6, the vector [s'] held in the third intermediate value holding circuit 58 after the processing in step 5 is performed is further multiplied by [Q1 ^t ]. To do. Formula for Step 6 [x] = 1/2 [Q1 ^t] [s '] in [s'] is identical to that determined in step 5.

The calculation of step 6 is shown in the following equations (556) to (563). However, although the calculation result of [Q1 ^t ] [s '] is finally halved in the calculation formula of step 6, this calculation shifts the output of [Q1 ^t ] [s'] right by 1 bit. Therefore, a multiplication circuit or a division circuit is not necessary in terms of the circuit.

[Equation 72] The calculation of step 6 is performed by the third addition / subtraction circuit 59. The configuration of the third addition / subtraction circuit 59 is the same as that of the first addition / subtraction circuit 55.

The calculation of the above equations (556) to (563) can be described by the signal flow graph shown in FIG. The signal flow graph of FIG. 9 is the same as the signal flow graph shown in FIG. 8 of step 5 described above. Therefore, the eight elements of the vector [x] (x _8i , x _{8i + 1} , x _{8i + 2} ,
x _{8i + 3} , x _{8i + 4} , x _{8i + 5} , x _{8i + 6} , x _{8i + 7} ) are calculated by using the unit adder / subtractor circuit 12 seven times to calculate the formulas (556) to (563). Is done. Therefore, all the elements (64) of the vector [x] are performed by using the unit addition / subtraction circuit 12 7 times × 6 = 56 times. The calculation in step 6 is performed in 56 clock cycles using the third adder / subtractor circuit 59 having one unit adder-subtractor circuit 12, and the output vector [x] (64 elements) is written in the output register 60 in word-serial manner. .

As described above, the two-dimensional 8 × 8 IDC of this embodiment is used.
In the T circuit 51, the number of multiplications required to obtain the original data [x] (64 elements) by performing the two-dimensional 8 × 8 IDCT calculation is only 180 performed in step 1, and the multiplication and addition are 1
When it is completed in a clock cycle, the multiplication / adder needs to have four multiplication units 70, 71 and 72, which simplifies the circuit configuration. Further, since the data path includes only one multiplication, it is possible to prevent the accumulation of rounding errors and the accumulation of calculation errors due to approximation of irrational numbers, and it is possible to obtain a highly accurate calculation result.

The above-mentioned 8 × 8 DCT circuit 1 and the first, second and third addition / subtraction circuits of the two-dimensional 8 × 8 IDCT 51 are configured to have one unit addition / subtraction circuit 12, but are configured to have a plurality of unit addition / subtraction circuits 12. You may. The multiplication / addition circuit 9 includes a multiplication unit 20 and a multiplication unit 2.
1. The multiplication unit 22 may be realized by a combination different from the above. The same applies to the multiply-add circuit 53.

[0143]

According to the two-dimensional 8x8 discrete cosine transform circuit of the present invention, the number of multiplications can be reduced as compared with the conventional two-dimensional 8x8 discrete cosine transform circuit. Therefore, the number of multipliers can be reduced, the circuit configuration can be simplified, and the circuit scale can be reduced. In addition, the number of operations including irrational numbers is reduced, and it is possible to reduce the accumulation of errors that occur when performing approximation of irrational numbers. In addition, the two-dimensional 8 of the present invention
According to the x8 discrete cosine inverse transform circuit, the conventional two-dimensional 8
The number of multiplications can be reduced as compared with the x8 discrete cosine inverse conversion circuit. Therefore, the number of multipliers can be reduced, the circuit configuration can be simplified, and the circuit scale can be reduced. In addition, the number of operations including irrational numbers is reduced, and it is possible to reduce the accumulation of errors that occur when performing approximation of irrational numbers.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an adder / subtractor circuit of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 3 is a signal flow graph when the first addition / subtraction circuit of the two-dimensional 8 × 8 DCT circuit according to the embodiment of the present invention performs the calculation of step 1.

FIG. 4 is a signal flow graph when the second addition / subtraction circuit of the two-dimensional 8 × 8 DCT circuit according to the embodiment of the present invention performs the calculation of step 2.

FIG. 5 is a configuration diagram of a multiply-add circuit of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 6 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a block diagram of a circuit.

FIG. 7 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a block diagram of the multiplication-addition circuit of a circuit.

FIG. 8 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
6 is a signal flow graph when the second adder / subtractor circuit of the circuit performs the calculation of step 5.

FIG. 9 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a signal flow graph when the 3rd addition / subtraction circuit of a circuit performs the calculation of step 6.

FIG. 10 is a formula table of trigonometric functions.

FIG. 11 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q1] of.

12 is a determinant of the small matrix [Q1 ₁₁ ] of FIG.

FIG. 13 is a determinant of the small matrix [Q1 ₁₂ ] of FIG.

14 is a determinant of the small matrix [Q1 ₁₃ ] of FIG.

15 is a determinant of the small matrix [Q1 ₁₄ ] of FIG.

16 is a determinant of the small matrix [Q1 ₂₁ ] of FIG.

17 is a determinant of the small matrix [Q1 ₂₂ ] of FIG.

18 is a determinant of the small matrix [Q1 ₂₃ ] of FIG.

19 is a determinant of the small matrix [Q1 ₂₄ ] of FIG.

20 is a determinant of the small matrix [Q1 ₃₁ ] of FIG.

21 is a determinant of the small matrix [Q1 ₃₂ ] of FIG.

22 is a determinant of the small matrix [Q1 ₃₃ ] of FIG.

23 is a determinant of the small matrix [Q1 ₃₄ ] of FIG.

24 is a determinant of the small matrix [Q1 ₄₁ ] of FIG.

25 is a determinant of the small matrix [Q1 ₄₂ ] of FIG.

FIG. 26 is a determinant of the small matrix [Q1 ₄₃ ] of FIG.

27 is a determinant of the small matrix [Q1 ₄₄ ] of FIG.

FIG. 28 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q2] of.

29 is a determinant of the small matrix [Q2 ₁₁ ] of FIG.

30 is a determinant of the small matrix [Q2 ₁₂ ] of FIG.

31 is a determinant of the small matrix [Q2 ₁₃ ] of FIG.

32 is a determinant of the small matrix [Q2 ₁₄ ] of FIG. 28.

FIG. 33 is a determinant of the small matrix [Q2 ₂₁ ] of FIG. 28.

34 is a determinant of the small matrix [Q2 ₂₂ ] of FIG.

FIG. 35 is a determinant of the small matrix [Q2 ₂₃ ] of FIG. 28.

FIG. 36 is a determinant of the small matrix [Q2 ₂₄ ] of FIG. 28.

FIG. 37 is a determinant of the small matrix [Q2 ₃₁ ] of FIG.

FIG. 38 is a determinant of the small matrix [Q2 ₃₂ ] of FIG. 28.

FIG. 39 is a determinant of the small matrix [Q2 ₃₃ ] of FIG.

FIG. 40 is a determinant of the small matrix [Q2 ₃₄ ] of FIG.

41 is a determinant of the small matrix [Q2 ₄₁ ] of FIG. 28.

42 is a determinant of the small matrix [Q2 ₄₂ ] of FIG.

FIG. 43 is a determinant of the small matrix [Q2 ₄₃ ] of FIG.

FIG. 44 is a determinant of the small matrix [Q2 ₄₄ ] of FIG. 28.

FIG. 45 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q3] of.

46 is a determinant of the small matrix [Q3 ₁₁ ] of FIG.

47 is a determinant of the small matrix [Q3 ₂₂ ] of FIG. 45. FIG.

FIG. 48 is a determinant of the small matrix of FIG. 45 [Q3 _33].

FIG. 49 is a determinant of the small matrix [Q3 ₄₄ ] of FIG. 45.

FIG. 50 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q4] of.

51 is a determinant of the small matrix [Q4 ₁₁ ] of FIG.

52 is a determinant of the small matrix [Q4 ₂₂ ] of FIG.

FIG. 53 is a determinant of the small matrix of FIG. 50 [Q4 _33].

FIG. 54 is a determinant of the small matrix of FIG. 50 [Q4 _44].

FIG. 55 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the small matrix of matrix [R] of.

56 is a determinant of the small matrix [R ₁₁ ] of FIG. 55. FIG.

FIG. 57 is a determinant of the small matrix [R ₁₂ ] of FIG. 55.

58 is a determinant of the small matrix [R ₁₃ ] of FIG. 55.

FIG. 59 is a determinant of the small matrix [R ₁₄ ] of FIG. 55.

FIG. 60 is a determinant of the small matrix [R ₂₁ ] of FIG. 55.

FIG. 61 is a determinant of the small matrix [R ₂₂ ] of FIG. 55.

62 is a determinant of the small matrix [R ₂₃ ] of FIG. 55. FIG.

63 is a determinant of the small matrix [R ₂₄ ] of FIG. 55. FIG.

64 is a determinant of the small matrix [R ₃₁ ] of FIG. 55.

65 is a determinant of the small matrix [R ₃₂ ] of FIG. 55.

66 is a determinant of the small matrix [R ₃₃ ] of FIG. 55. FIG.

67 is a determinant of the small matrix [R ₃₄ ] of FIG. 55. FIG.

68 is a determinant of the small matrix [R ₄₁ ] of FIG. 55. FIG.

69 is a determinant of the small matrix [R ₄₂ ] of FIG. 55.

70 is a determinant of the small matrix [R ₄₃ ] of FIG. 55. FIG.

71 is a determinant of the small matrix [R ₄₄ ] of FIG. 55. FIG.

FIG. 72 is a two-dimensional 8 × 8 IDC according to an embodiment of the present invention.
It is a diagram showing a submatrix T matrix [Q1 ^t].

73 is a determinant of the small matrix [Q1 ^t ₁₁ ] of FIG. 72. FIG.

74 is a determinant of the small matrix [Q1 ^t ₁₂ ] of FIG.

75 is a determinant of the small matrix [Q1 ^t ₁₃ ] of FIG.

76 is a determinant of the small matrix [Q1 ^t ₁₄ ] of FIG. 72. FIG.

77 is a determinant of the small matrix [Q1 ^t ₂₁ ] of FIG. 72. FIG.

78 is a determinant of the small matrix [Q1 ^t ₂₂ ] of FIG. 72. FIG.

79 is a determinant of the small matrix [Q1 ^t ₂₃ ] of FIG.

80 is a determinant of the small matrix [Q1 ^t ₂₄ ] of FIG. 72. FIG.

81 is a determinant of the small matrix [Q1 ^t ₃₁ ] of FIG. 72. FIG.

82 is a determinant of the small matrix [Q1 ^t ₃₂ ] of FIG.

83 is a determinant of the small matrix [Q1 ^t ₃₃ ] of FIG.

84 is a determinant of the small matrix [Q1 ^t ₃₄ ] of FIG.

85 is a determinant of the small matrix [Q1 ^t ₄₁ ] of FIG.

86 is a determinant of the small matrix [Q1 ^t ₄₂ ] of FIG. 72. FIG.

87 is a determinant of the small matrix [Q1 ^t ₄₃ ] of FIG. 72. FIG.

88 is a determinant of the small matrix [Q1 ^t ₄₄ ] of FIG. 72. FIG.

FIG. 89 is a two-dimensional 8 × 8 IDC according to an embodiment of the present invention.
It is a diagram showing a submatrix T matrix of [Q2 ^t].

90 is a determinant of the small matrix [Q2 ^t ₁₁ ] of FIG. 89. FIG.

91 is a determinant of the small matrix [Q2 ^t ₁₂ ] of FIG. 89. FIG.

92 is a determinant of the small matrix [Q2 ^t ₁₃ ] of FIG. 89. FIG.

93 is a determinant of the small matrix [Q2 ^t ₁₄ ] of FIG. 89. FIG.

FIG. 94 is a determinant of the small matrix [Q2 ^t ₂₁ ] of FIG. 89.

95 is a determinant of the small matrix [Q2 ^t ₂₂ ] of FIG. 89. FIG.

96 is a determinant of the small matrix [Q2 ^t ₂₃ ] of FIG. 89. FIG.

97 is a determinant of the small matrix [Q2 ^t ₂₄ ] of FIG. 89. FIG.

98 is a determinant of the small matrix [Q2 ^t ₃₁ ] of FIG. 89. FIG.

99 is a determinant of the small matrix [Q2 ^t ₃₂ ] of FIG. 89. FIG.

FIG. 100 is a determinant of the small matrix [Q2 ^t ₃₃ ] of FIG. 89.

101 is a determinant of the small matrix [Q2 ^t ₃₄ ] of FIG. 89.

102 is a determinant of the small matrix [Q2 ^t ₄₁ ] of FIG. 89. FIG.

103 is a determinant of the small matrix [Q2 ^t ₄₂ ] of FIG. 89. FIG.

FIG. 104 is a determinant of the small matrix [Q2 ^t ₄₃ ] of FIG. 89.

FIG. 105 is a determinant of the small matrix [Q2 ^t ₄₄ ] of FIG. 89.

FIG. 106 is a two-dimensional 8 × 8 ID according to an embodiment of the present invention.
It is a diagram showing a submatrix CT matrix of [Q3 ^t].

107 is a determinant of the small matrix [Q3 ^t ₁₁ ] of FIG. 106. FIG.

108 is a determinant of the small matrix [Q3 ^t ₂₂ ] of FIG. 106. FIG.

109 is a determinant of the small matrix [Q3 ^t ₃₃ ] of FIG. 106. FIG.

110 is a determinant of the small matrix [Q3 ^t ₄₄ ] of FIG. 106. FIG.

FIG. 111 is a two-dimensional 8x8 ID according to an embodiment of the present invention.
It is a diagram showing a submatrix CT matrix of [Q4 ^t].

112 is a determinant of the small matrix [Q4 ^t ₁₁ ] of FIG. 111. FIG.

113 is a determinant of the small matrix [Q4 ^t ₂₂ ] of FIG. 111. FIG.

114 is a determinant of the small matrix [Q4 ^t ₃₃ ] of FIG. 111. FIG.

115 is a determinant of the small matrix [Q4 ^t ₄₄ ] of FIG. 111. FIG.

FIG. 116 is a two-dimensional 8 × 8 ID according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [R ^t ] of CT.

117 is a determinant of the small matrix [R ^t ₁₁ ] of FIG. 116.

118 is a determinant of the small matrix [R ^t ₁₂ ] of FIG. 116.

FIG. 119 is a determinant of the small matrix [R ^t ₁₃ ] of FIG. 116.

120 is a determinant of the small matrix [R ^t ₁₄ ] of FIG. 116.

121 is a determinant of the small matrix [R ^t ₂₁ ] of FIG. 116.

122 is a determinant of the small matrix [R ^t ₂₂ ] of FIG. 116.

123 is a determinant of the small matrix [R ^t ₂₃ ] of FIG.

FIG. 124 is a determinant of the small matrix [R ^t ₂₄ ] of FIG. 116.

125 is a determinant of the small matrix [R ^t ₃₁ ] of FIG. 116.

126 is a determinant of the small matrix [R ^t ₃₂ ] of FIG. 116.

127 is a determinant of the small matrix [R ^t ₃₃ ] of FIG. 116.

128 is a determinant of the small matrix [R ^t ₃₄ ] of FIG. 116.

FIG. 129 is a determinant of the small matrix [R ^t ₄₁ ] of FIG.

130 is a determinant of the small matrix [R ^t ₄₂ ] of FIG. 116.

131 is a determinant of the small matrix [R ^t ₄₃ ] of FIG. 116.

132 is a determinant of the small matrix [R ^t ₄₄ ] of FIG. 116.

[Explanation of symbols]

 1 ... Two-dimensional 8x8 IDCT circuit 2, 52 ... Input register 3, 55 ... First addition / subtraction circuit 4, 54 ... First intermediate value holding circuit 5, 57 ... Second addition / subtraction Circuits 6,56 ... Second intermediate value holding circuit 7,59 ... Third addition / subtraction circuit 8,58 ... Third intermediate value holding circuit 9,59 ... Multiply-adder circuit 10,60 ... Output register 15 ... Adder 16 ... Subtractor 20, 21, 22, 70, 71, 72 ... Multiplier 30 ... Multiplier 32 ... Accumulator 34, 36 ... ..Coefficient storage memory 74 ... Adder / subtractor

[Procedure amendment]

[Submission date] August 23, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an adder / subtractor circuit of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 3 is a signal flow graph when the first addition / subtraction circuit of the two-dimensional 8 × 8 DCT circuit according to the embodiment of the present invention performs the calculation of step 1.

FIG. 4 is a signal flow graph when the second addition / subtraction circuit of the two-dimensional 8 × 8 DCT circuit according to the embodiment of the present invention performs the calculation of step 2.

FIG. 5 is a configuration diagram of a multiply-add circuit of a two-dimensional 8 × 8 DCT circuit according to an embodiment of the present invention.

FIG. 6 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a block diagram of a circuit.

FIG. 7 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a block diagram of the multiplication-addition circuit of a circuit.

FIG. 8 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
6 is a signal flow graph when the second adder / subtractor circuit of the circuit performs the calculation of step 5.

FIG. 9 is a two-dimensional 8 × 8 IDCT according to an embodiment of the present invention.
It is a signal flow graph when the 3rd addition / subtraction circuit of a circuit performs the calculation of step 6.

FIG. 10 is a diagram showing a trigonometric function formula .

FIG. 11 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q1] of.

FIG. 12 is a diagram showing a determinant of the submatrix [Q1 ₁₁ ] of FIG. 11.

FIG. 13 is a diagram showing a determinant of the submatrix [Q1 ₁₂ ] of FIG. 11.

FIG. 14 is a diagram showing a determinant of the small matrix [Q1 ₁₃ ] of FIG .

FIG. 15 is a diagram showing a determinant of the small matrix [Q1 ₁₄ ] of FIG. 11.

FIG. 16 is a diagram showing a determinant of the submatrix [Q1 ₂₁ ] of FIG .

FIG. 17 is a diagram showing a determinant of the small matrix [Q1 ₂₂ ] of FIG .

FIG. 18 is a diagram showing a determinant of the small matrix [Q1 ₂₃ ] of FIG .

FIG. 19 is a diagram showing a determinant of the submatrix [Q1 ₂₄ ] of FIG .

FIG. 20 is a diagram showing a determinant of the submatrix [Q1 ₃₁ ] of FIG .

FIG. 21 is a diagram showing a determinant of the submatrix [Q1 ₃₂ ] of FIG .

22 is a diagram showing a determinant of the submatrix [Q1 ₃₃ ] of FIG .

FIG. 23 is a diagram showing a determinant of the submatrix [Q1 ₃₄ ] of FIG .

24 is a diagram showing a determinant of the submatrix [Q1 ₄₁ ] of FIG .

FIG. 25 is a diagram showing a determinant of the submatrix [Q1 ₄₂ ] of FIG. 11;

FIG. 26 is a diagram showing a determinant of the small matrix [Q1 ₄₃ ] of FIG .

27 is a diagram showing a determinant of the small matrix [Q1 ₄₄ ] of FIG. 11. FIG.

FIG. 28 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q2] of.

FIG. 29 is a diagram showing a determinant of the small matrix [Q2 ₁₁ ] of FIG. 28.

FIG. 30 is a diagram showing a determinant of the submatrix [Q2 ₁₂ ] of FIG. 28.

FIG. 31 is a diagram showing a determinant of the small matrix [Q2 ₁₃ ] of FIG. 28.

FIG. 32 is a diagram showing a determinant of the submatrix [Q2 ₁₄ ] of FIG. 28.

FIG. 33 is a diagram showing a determinant of the small matrix [Q2 ₂₁ ] of FIG. 28.

FIG. 34 is a diagram showing a determinant of the small matrix [Q2 ₂₂ ] of FIG. 28.

FIG. 35 is a diagram showing a determinant of the small matrix [Q2 ₂₃ ] of FIG. 28.

FIG. 36 is a diagram showing a determinant of the small matrix [Q2 ₂₄ ] of FIG. 28.

FIG. 37 is a diagram showing a determinant of the submatrix [Q2 ₃₁ ] of FIG. 28.

38 is a diagram showing a determinant of the submatrix [Q2 ₃₂ ] of FIG. 28.

FIG. 39 is a diagram showing a determinant of the sub-matrix [Q2 ₃₃ ] of FIG. 28.

FIG. 40 is a diagram showing a determinant of the submatrix [Q2 ₃₄ ] of FIG. 28.

41 is a diagram showing a determinant of the submatrix [Q2 ₄₁ ] of FIG .

42 is a diagram showing a determinant of the sub-matrix [Q2 ₄₂ ] of FIG. 28.

43 is a diagram showing a determinant of the submatrix [Q2 ₄₃ ] of FIG. 28.

FIG. 44 is a diagram showing a determinant of the small matrix [Q2 ₄₄ ] of FIG. 28.

FIG. 45 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q3] of.

FIG. 46 is a diagram showing a determinant of the submatrix [Q3 ₁₁ ] of FIG. 45.

47 is a diagram <br/> showing a determinant of the small matrix of FIG. 45 [Q3 _22].

48 is a diagram <br/> showing a determinant of the small matrix of FIG. 45 [Q3 _33].

49 is a view <br/> showing a determinant of the small matrix of FIG. 45 [Q3 _44].

FIG. 50 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [Q4] of.

51 is a diagram showing a determinant of the submatrix [Q4 ₁₁ ] of FIG. 50.

52 is a diagram showing a determinant of the small matrix [Q4 ₂₂ ] of FIG. 50.

FIG. 53 is a diagram <br/> showing a determinant of the small matrix of FIG. 50 [Q4 _33].

FIG. 54 is a diagram <br/> showing a determinant of the small matrix of FIG. 50 [Q4 _44].

FIG. 55 is a two-dimensional 8 × 8 DCT according to an embodiment of the present invention.
It is a figure which shows the small matrix of matrix [R] of.

FIG. 56 is a diagram showing a determinant of the small matrix [R ₁₁ ] of FIG. 55.

57 is a diagram showing a determinant of the small matrix [R ₁₂ ] of FIG. 55.

FIG. 58 is a diagram showing a determinant of the small matrix [R ₁₃ ] of FIG. 55.

FIG. 59 is a diagram showing a determinant of the small matrix [R ₁₄ ] of FIG. 55.

FIG. 60 is a diagram showing a determinant of the small matrix [R ₂₁ ] of FIG. 55.

FIG. 61 is a diagram showing a determinant of the small matrix [R ₂₂ ] of FIG. 55.

62 is a diagram showing a determinant of the small matrix [R ₂₃ ] of FIG. 55.

FIG. 63 is a diagram showing a determinant of the small matrix [R ₂₄ ] of FIG. 55.

64 is a diagram showing a determinant of the small matrix [R ₃₁ ] of FIG. 55.

FIG. 65 is a diagram showing a determinant of the small matrix [R ₃₂ ] of FIG. 55;

66 is a diagram showing a determinant of the small matrix [R ₃₃ ] of FIG. 55.

67 is a diagram showing a determinant of the small matrix [R ₃₄ ] of FIG. 55;

68 is a diagram showing a determinant of the small matrix [R ₄₁ ] of FIG. 55.

69 is a diagram showing a determinant of the small matrix [R ₄₂ ] of FIG. 55;

70 is a diagram showing a determinant of the small matrix [R ₄₃ ] of FIG. 55;

71 is a diagram showing a determinant of the small matrix [R ₄₄ ] of FIG. 55. FIG .

FIG. 72 is a two-dimensional 8 × 8 IDC according to an embodiment of the present invention.
It is a diagram showing a submatrix T matrix [Q1 ^t].

Shows the FIG. 73 determinant of submatrix Figure 72 [Q1 ^t _11]
It is a figure .

Shows the FIG. 74 determinant of submatrix Figure 72 [Q1 ^t _12]
It is a figure .

Shows the FIG. 75 determinant of submatrix Figure 72 [Q1 ^t _13]
It is a figure .

Shows the FIG. 76 determinant of submatrix Figure 72 [Q1 ^t _14]
It is a figure .

Shows the FIG. 77 determinant of submatrix Figure 72 [Q1 ^t _21]
It is a figure .

Shows the FIG. 78 determinant of submatrix Figure 72 [Q1 ^t _22]
It is a figure .

Shows the FIG. 79 determinant of submatrix Figure 72 [Q1 ^t _23]
It is a figure .

Shows the FIG. 80] determinant of submatrix Figure 72 [Q1 ^t _24]
It is a figure .

Shows the FIG. 81 determinant of submatrix Figure 72 [Q1 ^t _31]
It is a figure .

Shows the FIG. 82] determinant of submatrix Figure 72 [Q1 ^t _32]
It is a figure .

Shows the FIG. 83] determinant of submatrix Figure 72 [Q1 ^t _33]
It is a figure .

Shows the FIG. 84 determinant of submatrix Figure 72 [Q1 ^t _34]
It is a figure .

Shows the FIG. 85] determinant of submatrix Figure 72 [Q1 ^t _41]
It is a figure .

Shows the FIG. 86] determinant of submatrix Figure 72 [Q1 ^t _42]
It is a figure .

Shows the FIG. 87] determinant of submatrix Figure 72 [Q1 ^t _43]
It is a figure .

Shows the FIG. 88] determinant of submatrix Figure 72 [Q1 ^t _44]
It is a figure .

FIG. 89 is a two-dimensional 8 × 8 IDC according to an embodiment of the present invention.
It is a diagram showing a submatrix T matrix of [Q2 ^t].

Shows a determinant in Figure 90] submatrix 89 [Q2 ^t _11]
It is a figure .

Shows the FIG. 91] determinant of submatrix 89 [Q2 ^t _12]
It is a figure .

Shows a determinant in Figure 92] submatrix 89 [Q2 ^t _13]
It is a figure .

Shows a determinant in Figure 93] submatrix 89 [Q2 ^t _14]
It is a figure .

Shows a determinant in Figure 94] submatrix 89 [Q2 ^t _21]
It is a figure .

Shows a determinant in Figure 95] submatrix 89 [Q2 ^t _22]
It is a figure .

Shows a determinant in Figure 96] submatrix 89 [Q2 ^t _23]
It is a figure .

Shows the FIG. 97] determinant of submatrix 89 [Q2 ^t _24]
It is a figure .

Shows a determinant in FIG. 98 submatrix 89 [Q2 ^t _31]
It is a figure .

Shows a determinant in FIG. 99 submatrix 89 [Q2 ^t _32]
It is a figure .

[Figure 100] submatrix Figure 89 the determinant of [Q2 ^t _33] shows
It is a figure .

The Figure 101] determinant of submatrix 89 [Q2 ^t _34] shows
It is a figure .

[Figure 102] submatrix Figure 89 the determinant of [Q2 ^t _41] shows
It is a figure .

[Figure 103] submatrix Figure 89 the determinant of [Q2 ^t _42] shows
It is a figure .

[Figure 104] submatrix Figure 89 the determinant of [Q2 ^t _43] shows
It is a figure .

[Figure 105] submatrix Figure 89 the determinant of [Q2 ^t _44] shows
It is a figure .

FIG. 106 is a two-dimensional 8 × 8 ID according to an embodiment of the present invention.
It is a diagram showing a submatrix CT matrix of [Q3 ^t].

Submatrix Figure 107] Figure 106 determinant of [Q3 ^t _11]
FIG .

Submatrix Figure 108] Figure 106 determinant of [Q3 ^t _22]
FIG .

Submatrix Figure 109] Figure 106 determinant of [Q3 ^t _33]
FIG .

[Figure 110] submatrix Figure 106 determinant of [Q3 ^t _44]
FIG .

FIG. 111 is a two-dimensional 8x8 ID according to an embodiment of the present invention.
It is a diagram showing a submatrix CT matrix of [Q4 ^t].

Submatrix Figure 112] Figure 111 determinant of [Q4 ^t _11]
FIG .

Submatrix Figure 113] Figure 111 determinant of [Q4 ^t _22]
FIG .

Submatrix Figure 114] Figure 111 determinant of [Q4 ^t _33]
FIG .

Submatrix Figure 115] Figure 111 determinant of [Q4 ^t _44]
FIG .

FIG. 116 is a two-dimensional 8 × 8 ID according to an embodiment of the present invention.
It is a figure which shows the submatrix of matrix [R ^t ] of CT.

[Figure 117] submatrix Figure 116 determinant of [R ^t _11] shows
It is a figure .

[Figure 118] submatrix Figure 116 determinant of [R ^t _12] shows
It is a figure .

[Figure 119] submatrix Figure 116 determinant of [R ^t _13] shows
It is a figure .

[Figure 120] submatrix Figure 116 determinant of [R ^t _14] shows
It is a figure .

[Figure 121] submatrix Figure 116 determinant of [R ^t _21] shows
It is a figure .

[Figure 122] submatrix Figure 116 determinant of [R ^t _22] shows
It is a figure .

[Figure 123] submatrix Figure 116 determinant of [R ^t _23] shows
It is a figure .

[Figure 124] submatrix Figure 116 determinant of [R ^t _24] shows
It is a figure .

[Figure 125] submatrix Figure 116 determinant of [R ^t _31] shows
It is a figure .

[Figure 126] submatrix Figure 116 determinant of [R ^t _32] shows
It is a figure .

[Figure 127] submatrix Figure 116 determinant of [R ^t _33] shows
It is a figure .

[Figure 128] submatrix Figure 116 determinant of [R ^t _34] shows
It is a figure .

[129] submatrix Figure 116 determinant of [R ^t _41] shows
It is a figure .

[Figure 130] submatrix Figure 116 determinant of [R ^t _42] shows
It is a figure .

[Figure 131] submatrix Figure 116 determinant of [R ^t _43] shows
It is a figure .

[Figure 132] submatrix Figure 116 determinant of [R ^t _44] shows
It is a figure .

[Explanation of Codes] 1 ... Two-dimensional 8x8 IDCT circuit 2, 52 ... Input register 3, 55 ... First addition / subtraction circuit 4, 54 ... First intermediate value holding circuit 5, 57 ... Second addition / subtraction circuit 6,56 ... Second intermediate value holding circuit 7,59 ... Third addition / subtraction circuit 8,58 ... Third intermediate value holding circuit 9,59 ... Adder circuit 10, 60 ... Output register 15 ... Adder 16 ... Subtractor 20, 21, 22, 70, 71, 72 ... Multiplier 30 ... Multiplier 32 ... Accumulation 34, 36 ... Coefficient storage memory 74 ... Adder / subtractor

Claims (12)

[Claims] 1. A first constant matrix ([Q1]), a second constant matrix ([Q2]), a third constant matrix ([Q3]), and a factor whose factors are +1, -1, or 0, respectively. Fourth
Constant matrix ([Q4]) and a fifth matrix ([R]) containing an irrational number defined by the 8x8 discrete cosine transform are sequentially subjected to matrix operation on matrix-format input data.
A discrete cosine transform circuit, comprising: a first constant matrix [Q1], a first adder / subtractor circuit that performs addition / subtraction corresponding to an inner product of the input data in a matrix format, and the first constant matrix [Q1]. A second addition / subtraction circuit that performs addition / subtraction corresponding to an inner product operation with the operation result in the first addition / subtraction circuit, and an inner product operation between the second constant matrix [Q2] and the operation result in the second addition / subtraction circuit The first addition / subtraction corresponding to
A second addition / subtraction corresponding to an inner product operation of the third constant matrix [Q3] and the operation result of the first addition / subtraction, and an operation result of the fourth constant matrix [Q4] and the second addition / subtraction And a third addition / subtraction circuit that performs a third addition / subtraction corresponding to an inner product operation with the fifth matrix [R] and an operation result in the third addition / subtraction circuit that corresponds to an inner product operation. A two-dimensional 8x8 discrete cosine transform circuit having a multiply-add circuit. 2. The first constant matrix [Q1] has 6 rows of 8 columns in the vertical direction and 8 columns of the horizontal direction, each having a factor of 8 rows and 8 columns.
The constant submatrix composed of four constant submatrices is the constant submatrix in the horizontal direction N (1 ≦ N ≦ 8) column of the first stage in the vertical direction. The eight factors in the Nth row are “1, 1, 1, 1 , 1, 1, 1,
1 "and the other factors are 0. The constant small matrix in the horizontal N (1 ≦ N ≦ 8) column of the second vertical column is that the eight factors in the Nth row are“ 1, −1, -1,1,1,-
1, -1, 1 "and the other factors are 0, and the constant submatrix in the horizontal N (1 ≤ N ≤ 8) column of the third stage in the vertical direction is 0,1, -1,0,0, -1,
1, 0 "and the other factors are 0. The constant small matrix in the horizontal Nth column (1≤N≤8) in the fourth vertical column is that the eight factors in the Nth row are" 1,0 ". , 0, -1, -1, 0,
0, 1 "and the other factors are 0. The constant small matrix in the horizontal Nth column (1≤N≤8) in the fifth vertical column is that the eight factors in the Nth row are" 0,0 ". , 0, 1, -1, 0,
0, 0 "and the other factors are 0. The constant small matrix in the horizontal N (1 ≤ N ≤ 8) column in the sixth vertical row is that the eight factors in the Nth row are" 0, 0 , 1, 0, 0, -1,
0, 0 "and the other factors are 0. The constant small matrix in the horizontal Nth column (1≤N≤8) in the seventh vertical column is that the eight factors in the Nth row are" 0,1 ". , 0, 0, 0, 0,-
1, 0 "and the other factors are 0. The constant submatrix in the Nth horizontal direction (1≤N≤8) column of the eighth row in the vertical direction is that the eight factors in the Nth row are" 1,0 ". , 0, 0, 0, 0, 0,
-1 "and the other factors are 0, and the first addition / subtraction circuit, the second addition / subtraction circuit, and the third addition / subtraction circuit are configured by 1 or a plurality of adders and subtractors, The two-dimensional 8x8 discrete cosine transform circuit according to claim 1, wherein addition / subtraction corresponding to an inner product with the input data is performed. 3. The first adder / subtractor circuit, the second adder / subtractor circuit, and the third adder / subtractor circuit include an adder that performs addition between a first input and a second input;
The two-dimensional 8x according to claim 2, further comprising a unit circuit configured by a subtractor that subtracts the second input from the input of the unit, and the unit circuit is configured to perform the operation by a combination of one or a plurality of the unit circuits.
8 Discrete cosine transform circuit. 4. The multiplying / adding circuit includes a multiplier, a coefficient holding circuit, and an accumulator, the coefficient holding circuit records a predetermined coefficient, and the multiplier has an input and a coefficient holding circuit. Multiplies the recorded coefficient and outputs the multiplication result to the accumulator. The accumulator holds the multiplication result input from the multiplier, and the addition and subtraction of this multiplication result and the previously held multiplication result. The two-dimensional 8x8 discrete cosine transform circuit according to claim 2 or 3, wherein 5. The multiplying / adding circuit includes a multiplier, a coefficient holding circuit, a first accumulator and a second accumulator, and the coefficient holding circuit records a predetermined coefficient, The multiplier multiplies the input by the coefficient recorded in the coefficient holding circuit, outputs the multiplication result to the first accumulator and the second accumulator, and outputs the multiplication result to the first accumulator and the second accumulator. The two-dimensional 8x8 discrete unit according to claim 2 or 3, wherein the calculator holds the multiplication result input from the multiplier and performs addition and subtraction of the multiplication result and the previously held multiplication result. Cosine conversion circuit. 6. The matrix operation, wherein the first addition / subtraction circuit is the first stage, the second addition / subtraction circuit is the second stage, the third addition / subtraction circuit is the third stage, and the multiplication circuit is the fourth stage 4 The two-dimensional 8 according to any one of claims 1 to 5, which is performed by a stage pipeline system.
x8 discrete cosine transform circuit. 7. A first matrix which is a transposed matrix of a matrix ([R]) containing an irrational number defined by an 8 × 8 discrete cosine transform.
Matrix ([R ^t ]), and a constant matrix ([Q4]) and a constant matrix ([Q
3]), a constant matrix ([Q2]), and a constant matrix ([Q
1]), the second constant matrix [Q4 ^t ], the third constant matrix [Q3 ^t ], the fourth constant matrix [Q2 ^t ] and the fifth constant matrix [Q1 ^t ] are sequentially arranged. An 8 × 8 discrete cosine inverse transform circuit for performing a matrix operation on matrix-format input data, the multiply-add circuit for performing a multiplication / addition corresponding to an inner product of the first matrix [R ^t ] and the matrix-format input data. And a first addition and subtraction corresponding to an inner product operation of the second constant matrix [Q4 ^t ] and the operation result in the multiplication and addition circuit, and an operation of the third constant matrix [Q3 ^t ] and the first addition and subtraction. A first addition / subtraction corresponding to an inner product operation with the result, and a third addition / subtraction corresponding to an inner product operation of the fourth constant matrix [Q2 ^t ] and the operation result of the second addition / subtraction a subtraction circuit, said fifth constant matrix and [Q1 ^t], said first adder A second adder circuit for performing addition and subtraction corresponding to the inner product computation of the computation result of the road, the fifth constant matrix and [Q1 ^t], addition and subtraction corresponding to the inner product computation of the calculation result in the second addition and subtraction circuit A two-dimensional 8x8 discrete cosine inverse transform circuit having a third adder / subtractor circuit for performing. 8. The fifth constant matrix [Q1 ^t ] is composed of 64 constant small matrices of 8 columns in the vertical direction and 8 columns in the horizontal direction, each having a factor of 8 columns and 8 rows, and a constant number N in the vertical direction. In the constant small matrix in the first column in the horizontal direction of (1 ≦ N ≦ 8) stages, the eight factors in the Nth column are “1,1,1,1,1,1,1,1,
1 "and the other factors are 0. The constant small matrix in the second column in the horizontal direction at the Nth stage in the vertical direction (1 ≦ N ≦ 8) is that the eight factors in the Nth column are“ 1, −1, -1,1,1,-
1, -1, 1 "and the other factors are 0. The constant submatrix in the third column in the horizontal direction at the Nth vertical direction (1≤N≤8) is 8 factors in the Nth column. 0,1, -1,0,0, -1,
1, 0 "and the other factors are 0, and the constant small matrix in the fourth column in the horizontal direction at the N-th (1 ≦ N ≦ 8) vertical direction is that the eight factors in the N-th column are“ 1,0 ”. , 0, -1, -1, 0,
0,1 "and the other factors are 0. The constant small matrix in the fifth column in the horizontal direction at the Nth stage (1≤N≤8) in the vertical direction is that the eight factors in the Nth column are" 0,0 ". , 0, 1, -1, 0,
0,0 "and the other factors are 0. The constant small matrix in the sixth column in the horizontal direction at the Nth vertical direction (1≤N≤8) is that the eight factors in the Nth column are" 0,0 ". , 1, 0, 0, -1,
0, 0 "and the other factors are 0. The constant small matrix in the horizontal seventh column of the Nth vertical direction (1≤N≤8) is the eight factors in the Nth column being" 0,1 ". , 0, 0, 0, 0,-
1, 0 "and the other factors are 0. The constant submatrix in the eighth column in the horizontal direction at the Nth stage (1≤N≤8) in the vertical direction is that the eight factors in the Nth column are" 1,0 ". , 0, 0, 0, 0, 0,
-1 "and the other factors are 0, and the first addition / subtraction circuit, the second addition / subtraction circuit, and the third addition / subtraction circuit are configured by 1 or a plurality of adders and subtractors, 8. The two-dimensional 8 × 8 discrete cosine inverse transform circuit according to claim 7, wherein addition / subtraction corresponding to an inner product with the input data is performed. 9. The first adding / subtracting circuit, the second adding / subtracting circuit, and the third adding / subtracting circuit include an adder that adds the first input and the second input, and a first adder.
9. The two-dimensional 8x according to claim 8, further comprising a unit circuit configured by a subtractor that subtracts the second input from the input of the unit, and the unit circuit is configured to perform the operation by a combination of one or a plurality of the unit circuits.
8 Discrete Cosine Inversion Circuit. 10. The multiplying / adding circuit includes a multiplier, a coefficient holding circuit, and an accumulator, the coefficient holding circuit records a predetermined coefficient, and the multiplier has an input and a coefficient holding circuit. Multiplies the recorded coefficient and outputs the multiplication result to the accumulator. The accumulator holds the multiplication result input from the multiplier, and the addition and subtraction of this multiplication result and the previously held multiplication result. The two-dimensional 8 × 8 discrete cosine inverse transform circuit according to claim 8 or 9, wherein 11. The multiplication / addition circuit includes an adder / subtractor, a multiplier, a coefficient holding circuit, and an accumulator, and the adder / subtractor adds or subtracts a first input and a second input. The input of 1 and the second input are subtracted, the addition result or the subtraction result is output to the accumulator, the coefficient holding circuit holds a predetermined coefficient, and the multiplier holds the input and the coefficient from the adder / subtractor. Multiplies the coefficient recorded in the holding circuit and outputs the multiplication result to the accumulator. The accumulator holds the multiplication result input from the multiplier, and this multiplication result and the previously held multiplication result. The two-dimensional 8x8 discrete cosine inverse transform circuit according to claim 8 or 9, which performs addition and subtraction with and. 12. The matrix operation comprises:
A second stage, the second addition / subtraction circuit is the third stage, and the third addition / subtraction circuit is the fourth stage. 4
The two-dimensional 8x8 discrete cosine inverse transform circuit according to any one of claims 7 to 11, which is performed by a stage pipeline system.