JPH06163565A - Transistor element - Google Patents

Abstract

(57) [Summary] [Purpose] To improve the breakdown voltage of a transistor. [Structure] FIG. 1 (a) is a plan view of a lateral PNP transistor, FIG. 1 (b) is a sectional view taken along line AA ', and FIG. 1 (c) is a sectional view taken along line BB'. The emitter 1 of the transistor has a structure surrounded by a collector diffusion layer 3, and a thick insulating layer 4 is formed where the emitter wiring 2 crosses the collector diffusion layer 3. With this structure, in the operation diagram showing the reverse bias of FIG. 1 (d), the relationship between the collector active layer 3 and the base layer 6 is in the PN reverse bias state, and the depletion layers 7 and 8 are formed around the collector active layer 3. You can At this time, the potential of the emitter wiring 2 increases the carrier concentration in the vicinity of the surface of the epitaxial layer 6 immediately below the insulating layer due to the electrostatic effect, but the thick insulating layer 4 causes only a slight influence of the emitter wiring 2 and thus the depletion layer. No. 8 does not cause electric field concentration and does not lower the withstand voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a transistor element, and more particularly to wiring arrangement.

[0002]

2. Description of the Related Art Conventionally, in a two-dimensionally arranged semiconductor device in which a substrate such as an IC is formed by a planar process technique, wiring connecting circuit elements is formed on an insulating film having a uniform thickness formed on a semiconductor substrate. Has been done. Since this wiring is laid out in a plane, in the case of a lateral transistor used in an IC or the like, the collector surrounds the emitter due to its characteristics. Therefore, the wiring for the P-type emitter is located above the P-type collector active layer. Is formed so as to cross. In the case of the conventional example, in the lateral PNP transistor, the emitter wiring 21 is close to the collector active layer 22 via the thin insulating layer 23 as shown in FIG. At times, the depletion layer 24 formed near the surface around the active layer 22 is considerably narrowed, and the breakdown voltage becomes lower than the normal breakdown voltage. Therefore, in order to guarantee the breakdown voltage in consideration of this, the dimensions have been designed with a margin such as a large depth of the collector diffusion layer or a space between the emitter and the collector.

[0003]

However, when the potential of the wiring that crosses the upper part of the collector active layer of the transistor element is reverse bias having a larger difference than the potential of the collector active layer, the electrostatic effect of the wiring is reduced. Due to the influence, the concentration of carriers, that is, electrons or holes, which contribute to the electric conduction of the base layer around the collector active layer, increases. As a result, the depletion layer between the collector and the base generated by the reverse bias is narrowed in the vicinity of the surface immediately below the insulating layer, and electric field concentration occurs. Therefore, at that portion, breakdown occurs at a voltage lower than the original avalanche breakdown voltage, which causes a problem that the withstand voltage of the semiconductor substrate decreases. A structure in which the collector of the lateral transistor is U-shaped and the collector under the wiring for the emitter is eliminated is implemented. However, the U-shape does not cause the above problem, but the emitter-
There is a problem that the injection efficiency between collectors is reduced. Therefore, an object of the present invention is to improve withstand voltage characteristics without deteriorating the performance of a transistor element.

[0004]

SUMMARY OF THE INVENTION According to the structure of the invention for solving the above problems, in a transistor element formed on a semiconductor substrate, an emitter active region of the transistor element is a collector via a base active region. In a planar arrangement surrounded by active regions, an electrode wiring of the emitter active region crosses an upper portion of the collector active region on an insulating layer formed on the semiconductor substrate, and the electrode wiring is In a semiconductor device in which a voltage is applied and a width of a depletion layer formed in a junction region between the base active region and the collector active region is narrowed in a surface region, an insulating layer below the electrode wiring is connected to the collector active region. It is characterized in that the portion that crosses the region is thicker than the thickness of the insulating layer in the normal portion.

[0005]

When the insulating layer at the position where the wiring crosses the collector active layer becomes thicker, for example, when the insulating layer becomes three times thicker,
Since the electric field generated by the wiring weakens almost in proportion to the distance, the influence on the junction region between the base active region and the collector active region under the insulating layer is also reduced to 1/3, and the concentration of carriers is relaxed.

[0006]

As a result, the breakdown voltage reliability of the semiconductor substrate is improved because the reduction of the dielectric breakdown voltage due to the electric field concentration of the depletion layer generated in the junction region between the collector active layer and the base layer under the emitter wiring is suppressed. In addition, the structure of the lateral transistor may be the collector shape that is the same as the shape that surrounds the emitter, so the injection efficiency does not change, and since there is no need to provide a design margin, the semiconductor device size can be reduced slightly without lowering the breakdown voltage. You can

[0007]

EXAMPLES The present invention will be described below based on specific examples. 1 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 1 (a) is a plan view of a lateral PNP transistor formed on a semiconductor substrate, and FIG. 1 (b) is FIG. 1 (a). A-
It is a sectional view of A '. Also, FIG. 1 (c) is shown in FIG. 1 (a) B-
It is a sectional view of B '. It should be noted that none of the figures shows the isolation region of the substrate from other elements. As shown in this figure, the emitter 1 of the transistor has a structure surrounded by a collector diffusion layer 3, and a thick insulating layer 4 is formed at a position where the emitter wiring 2 connected to the emitter 1 crosses the collector diffusion layer 3. Has been formed.

With such a structure, in the operation diagram showing the reverse bias of FIG. 1D, the relation between the collector active layer 3 and the base layer 6 which is the epitaxial layer of the substrate is PN.
Because of the reverse bias state, depletion layers 7 and 8 are formed around the collector active layer 3. The spread of the depletion layers 7 and 8 is determined by the degree of reverse bias, the impurity concentration of the semiconductor substrate epitaxial layer 6, and the impurity concentration of the collector active layer 3. At this time, the potential of the emitter wiring 2 increases the carrier concentration in the vicinity of the surface of the epitaxial layer 6 immediately below the insulating layer due to the electrostatic effect, but the thick insulating layer 4 causes only a slight influence of the emitter wiring 2 and thus the depletion layer. No. 8 does not cause electric field concentration and does not lower the withstand voltage.

The formation of the thick insulating layer structure of the present invention can be realized by forming an ordinary insulating layer and then repeatedly stacking the insulating layer forming process using a mask, which can be incorporated into a conventional manufacturing process. Laminates in a step-like manner from the emitter electrode to the thick insulating layer so that the wiring is secure. Alternatively, after forming a thick insulating layer from the beginning, so-called mesa etching that leaves a necessary portion may be performed to reduce the thickness.

As another example of the present invention, as shown in FIG. 3, a multilayer wiring structure may be used for forming a thick insulating layer. That is, even if the intended emitter wiring is not formed on the first layer wiring on the thin insulating layer 23, the flattening interlayer insulating layer 31 is formed, and the second layer wiring 30 thereon is formed as the emitter wiring, the same result is obtained. The effect is obtained. This method can also be directly incorporated in a multilayer wiring type semiconductor substrate as part of the manufacturing process.

The present invention is not limited to the lateral transistor, and if any circuit element has a structure which adversely affects by the electrostatic effect of the reverse bias as the problem here, a thick insulating layer structure is applied to obtain the same effect. Bring Further, since the breakdown voltage is increased, there is also an effect that the design which has been taking safety until then can be omitted.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional embodiment.

FIG. 3 is a schematic sectional view showing another embodiment of the present invention.

[Explanation of symbols]

 1 Emitter 2 Emitter Wiring 3 Collector Diffusion Layer 4 Thick Insulating Layer 5 Emitter Diffusion Layer 7, 8 Depletion Layer Region Near Surface 20 Emitter 21 Emitter Wiring 22 Collector Diffusion Layer 23 Thin Insulation Layer 24, 25 Depletion Layer Region Near Surface 30 Two-layer wiring emitter wiring 31 Flattening interlayer insulation layer

Claims (1)

[Claims] 1. A transistor element formed on a semiconductor substrate, wherein the emitter active region of the transistor element is a planar arrangement surrounded by a collector active region via a base active region, and the transistor active region is formed on the semiconductor substrate. A structure in which the electrode wiring of the emitter active region crosses the upper portion of the collector active region on the insulating layer formed on the substrate, and a voltage is applied to the electrode wiring to connect the base active region and the collector active region. In a semiconductor device in which the width of the depletion layer formed in the junction region is narrowed in the surface region, the insulating layer below the electrode wiring is thicker than the normal insulating layer at the portion crossing the collector active region. A transistor element characterized in that