JPH061836B2 - Thin film transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor preferably used as a switching means for each pixel in, for example, an active matrix driving type liquid crystal device.

2. Description of the Related Art In recent years, the area of liquid crystal display devices has been increasing, and so-called active matrix driving method using a switching element has been adopted instead of the time-division driving method used so far. As a result, a display device having a pixel number exceeding tens of thousands of pixels, such as a so-called liquid crystal television receiver, is possible. In such an active matrix driving method, it is necessary to form a switching element such as a transistor in each pixel, and in particular, in a transmissive display device using a twisted nematic liquid crystal material, for example, glass or molten glass is used. It is necessary to form thin film switching means on a transparent amorphous substrate such as quartz.

Conventionally, when a thin film transistor is used as such a thin film switching element, an oxygen group compound (chalcogenide), hydrogenated amorphous silicon, polycrystalline silicon, or the like has been considered as a material for forming an active layer thereof. It is known that among such materials, polycrystalline silicon is superior in terms of so-called transistor characteristics and operational stability. In particular, as described above, in an active matrix drive type liquid crystal display device or the like, when forming a thin film circuit including a drive circuit of a switching transistor, polycrystalline silicon excellent in drive speed is considered important. . That is, polycrystalline silicon has an operating speed of about 10 times or more that of amorphous silicon, for example.

On the other hand, as a technique for forming a thin film transistor of polycrystalline silicon, a metal-oxide film-semiconductor large-scale integrated circuit (hereinafter abbreviated as MOS-LSI) manufacturing technique has been conventionally applied. Since the optimum temperature in 1 reaches about 1000 ° C., therefore, it is necessary to use expensive fused silica as an amorphous substrate, and in order to use a glass substrate that is cheaper and can easily be made large in area,
For example, a thin film transistor manufacturing technique that can be realized in a low temperature range of 600 ° C. or less has been desired.

Problems to be Solved by the Invention Problems that occur when the polycrystalline silicon thin film transistor is formed in the low temperature region as described above will be described below. When the MOS-LSI manufacturing technique as described above is used for manufacturing a polycrystalline silicon thin film transistor, impurities to be doped are doped by a diffusion method or an ion implantation method in order to form a gate electrode with polycrystalline silicon. To lower the resistance of the polycrystalline silicon used as the gate electrode.

As described above, the desired low temperature manufacturing method technology cannot use the diffusion method which requires heat treatment at about 1000 ° C. Moreover, if the ion implantation method is used,
It is necessary to activate the implanted impurities by heat treatment in a temperature range of about 600 ° C. or lower. However, 60
In the heat treatment at 0 ° C. or lower, the efficiency of activating the implanted impurities cannot be sufficiently increased, and there is a limit in reducing the resistance of the gate electrode. For this reason, it is difficult to realize a gate electrode using polycrystalline silicon in a low temperature region.

Since the selection range of the electrode material is expanded in the low temperature region heat treatment, a low resistance conductor such as a metal, a metal-silicon alloy and a metal-silicon compound can be used as the gate electrode. Low resistance can be achieved.

These conductive materials have good adhesiveness to the gate insulating film formed between the gate electrode and the active layer, workability,
Further, it is required that the selective workability for the gate insulating film be good. When the above-mentioned MOS-LSI manufacturing technique is used, a silicon dioxide SiO ₂ film is usually used as a gate insulating film. At this time, in general, a metal having a higher reactivity with silicon dioxide has a better adhesion to silicon dioxide. Aluminum Al or aluminum-silicon alloys, for example, have very good adhesion to silicon dioxide, but they react at temperatures above about 500 ° C., for example. Therefore, a gate electrode made of such a single material of metal or alloy has low resistance to heat treatment, etc., and is a so-called cell alignment method (that is, a gate electrode is first formed, and the formed gate electrode is used as a mask to form a drain electrode and a source. It cannot be used in the process of forming a thin film transistor using a manufacturing method of forming electrodes and the like).

Refractory metals such as molybdenum Mo and tungsten W have low reactivity with silicon dioxide but have low adhesion to silicon dioxide, and these refractory metals cannot be used. Also. The above-described self-alignment manufacturing technique is suitable for improving the manufacturing yield by aiming at the characteristics of the transistor. Therefore, the source region and the drain region formed by ion implantation are subjected to heat treatment during impurity activation. Tolerance is required.

Therefore, an object of the present invention is to solve the above-mentioned problems, to be manufactured by a manufacturing technique in a relatively low temperature range, to have low resistance, to be easily and inexpensively manufactured, and to obtain a gate insulating film and a conductor material. An object of the present invention is to provide a thin film transistor having good adhesion and improved reliability with use.

Means for Solving the Problems The present invention relates to a polycrystalline semiconductor active layer having source / drain regions formed on one surface of a base material made of an insulating material, and a polycrystalline semiconductor active layer covering the polycrystalline semiconductor active layer. The first insulating layer and the polycrystalline semiconductor active layer on the first insulating layer are selectively formed at positions corresponding to the polycrystalline semiconductor active layer. A thickness of a polycrystalline silicon layer which is composed of a body layer and is not doped with impurities, dp, a thickness of the first insulating layer is di, a dielectric constant of a polycrystalline silicon layer which is not doped with εp, When the dielectric constant of the first insulating layer is εi, (εp / εi) di >> dp, a gate electrode layer, a second insulating layer that covers the first insulating layer and the gate electrode layer, and The polycrystalline semiconductor penetrating the first and second insulating layers, A thin film transistor including a source electrode and a drain electrode electrically connected to an active layer.

According to the present invention, the thin film transistor has a polycrystalline active layer formed on one surface of a base material made of an insulating material, and covers the active layer to form a first insulating layer. A gate electrode layer including a polycrystalline silicon layer to which no impurity is added and a conductor layer is formed from the first insulating layer side at a position on the first insulating film corresponding to the polycrystalline active layer. It An element having a different number of valence electrons from the element forming the polycrystalline active layer is ionized and implanted into the polycrystalline active layer to form source / drain regions. A second insulating layer is formed by covering the first insulating layer and the gate electrode layer, and penetrates the first and second insulating layers to electrically connect with the polycrystalline active layer. A source electrode and a drain electrode are formed.

Therefore, for example, even when the treatment is performed in a relatively low temperature range of 600 ° C. or lower, the gate electrode layer is formed including the conductor layer, so that the resistance of the entire electrode layer can be suppressed and The manufacturing process is also simplified, and the reliability associated with use can be improved.

Further, in the present invention, a polycrystalline silicon layer to which impurities are not added is used, and the film thickness dp thereof has a value equal to or less than a certain value that satisfies the second formula described later, thereby improving the operation speed. Can be achieved.

Example FIG. 1 is a sectional view of a thin film transistor 1 for explaining the principle of the present invention. The thin film transistor 1 has a polycrystalline semiconductor active layer, for example, a polycrystalline silicon active layer 3, on a substrate such as a glass substrate 2. A gate insulating film 4 which covers the active layer 3 and is a first insulating layer made of silicon dioxide or the like.
To form. A gate electrode layer formed of a polycrystalline silicon layer 5 containing no impurities and a conductor layer 6 of a metal or a metal-silicon alloy or a metal-silicon compound at a position corresponding to the active layer 3 on the gate insulating film 4. 7 is formed. An insulating film 8 serving as a second insulating layer is formed so as to cover the gate electrode layer 7 and the first insulating layer. Next, a source electrode 9 and a drain electrode 10 which penetrate the first and second insulating films 4 and 8 and are electrically connected to the active layer 3 are formed.

The polycrystalline silicon layer 5 to which impurities are not added usually has a specific resistance of 10 ⁶ Ωcm or more, which is higher than the specific resistance of impurity-added polycrystalline silicon, for example, 2 to 5 Ωcm. It is considered that the operation speed of such a thin film transistor is reduced. Further, such high resistance polycrystalline silicon layer 5 may be depleted, and the potential difference applied to the gate insulating film 4 may be reduced. In this case, the density of carriers generated with the application of voltage is reduced, and thus the operating speed may be reduced.

However, according to the present invention, it is possible to avoid the problem that the operation speed is lowered by appropriately selecting the thickness of the polycrystalline silicon layer 5. That is, if the capacitance of the polycrystalline silicon layer 5 is sufficiently larger than the capacitance of the gate insulating film 4, most of the voltage applied to the gate electrode layer 7 will be applied to the gate insulating film 4. Become. That is, with respect to the voltage applied to the electrode layer 7, the divided voltages of the polycrystalline silicon layer 5 and the gate insulating film 4 are inversely proportional to their respective capacities.

Here, the film thickness and the dielectric constant of the polycrystalline silicon layer 5 are set to dp. If εp, the minimum capacitance of the polycrystalline silicon layer 5 is εp / dp per unit area, and if the film thickness and the dielectric constant of the gate insulating film 4 are di and εi, respectively, the unit of the gate insulating film 4 is The capacity per area is εi / d
i. Therefore, the relationship of the following formula may be established between these capacities per unit area.

[epsilon] p / dp >> [epsilon] i / di (1) By paying attention to the film thicknesses dp and di in the first expression, the following expression is obtained.

(Εp / εi) di >> dp (2) When the capacitance of the gate insulating film 4 is charged, when the capacitance between the gate insulating film 4 and the polycrystalline silicon layer 5 and the resistance of the polycrystalline silicon layer 5 are determined. The degree of voltage fluctuation having a constant is about the voltage applied to the polycrystalline silicon layer 5. Therefore, under the condition that the second equation is satisfied, the degree of voltage fluctuation is sufficiently small, so that it can be practically ignored. Becomes

On the other hand, the time constant at the time of gate capacitance discharge is determined by the capacitance of the gate insulating film 4 and the resistance of the polycrystalline silicon layer 5, and is represented by τ in the following equation.

τ = (εi / di) (dp / σp) = (dp / di) (εi / σp) (3) σp: Permittivity of polycrystalline silicon layer 5 Here, if the first equation is satisfied, the time constant is τ is εp / σp
Will be much smaller than That is, the dielectric constant σp of the polycrystalline silicon layer 5 to which impurities are not added is 10
^-6 (Ωcm) ^-1 and assuming that the relative permittivity of polycrystalline silicon is 11.9, which is the same as that of single crystal silicon, εi / σp
Is 1 μsec, and a sufficiently high speed response can be performed.

Further, in the operation of the frequency of σp / εp or more, the resistance component of the polycrystalline silicon film is generally negligible as compared with the capacitance component. This is because, considering the conductance of the resistance component and the capacitance component, the capacitance component has a conductance proportional to the frequency of the applied voltage, and the conductance of the resistance component does not depend on the frequency. That is, as the conductance of the capacitance component increases, the value of the resistance component that maintains a constant value relatively decreases and can be ignored. Therefore, the polycrystalline silicon layer 5 can be regarded as an insulator rather, and as long as the first formula is satisfied, there is no hindrance in operation.

As described above, in the thin film transistor 1 shown in FIG. 1, the gate electrode layer 7 has a two-layer structure including, for example, the polycrystalline silicon layer 5 and the conductor layer 6, so that the adhesion of the gate insulating film 4 is excellent. Moreover, a thin film transistor capable of maintaining stable quality can be realized. It is desirable that the electrode layer 7 has a low resistance, but since it is composed of the conductor layer 6 and the polycrystalline silicon layer 5 to which no impurity is added, the polycrystalline silicon layer 5 has a high resistance. Also, by forming the polycrystalline silicon layer 5 thinly so as to satisfy the condition of the first formula, the thin film transistor 1 which can be used without any trouble as described above and which is capable of sufficiently high-speed response in terms of operating speed. Obtainable.

2 and 3 are cross-sectional views for explaining the characteristics of the electrode layer 7 having the two-layer structure described with reference to FIG. The present inventors conducted the following experiments in order to verify the characteristics of the above-mentioned gate electrode having a two-layer structure. The acid-cleaned N-type single crystal silicon wafers 11a and 11b are thermally oxidized in a dry oxygen atmosphere at 900 ° C.
a and 12b were formed. Next, on the oxide film 12a, a low pressure chemical vapor deposition method (hereinafter referred to as a CVD method) using nitrogen-diluted monosilane SiH ₄ is performed at 620 ° C. for about 5 minutes.
A 00Å polycrystalline silicon film 13 was formed.

An aluminum-silicon alloy is sputtered on these silicon wafers 11a and 11b by sputtering.
A resist pattern for forming a 0.8 mmφ circular electrode having a so-called guard ring was formed by photolithography with a film thickness of 0 Å. Next, the aluminum-silicon alloy thin film is etched with a phosphoric acid-based etching solution, and the polycrystalline silicon film 13 is formed on the silicon wafer 11a having the polycrystalline silicon film 13 by a plasma etching method using sulfur hexafluoride SF ₆ gas. Etched. These silicon wafers 11a,
Two sets of 11b are prepared.

One of the pair of silicon wafers 11a was heat-treated at 440 ° C. for 30 minutes in a hydrogen atmosphere, and the other was also heat-treated at 500 ° C. for 75 minutes in a hydrogen atmosphere. Further, similar heat treatment was performed on the other set of silicon wafers 11b. For each pair of silicon wafers 11a and 11b that have been heat-treated in this manner,
The current-voltage characteristics, the voltage dependence of the high frequency capacity and the voltage dependence of the quasi-static capacity were measured, and the breakdown voltage of each capacitor, the flat band voltage, and the thermal oxide film / single crystal silicon interface level were evaluated. The evaluation results are shown in Table 1 below.

As is clear from Table 1 above, in the electrode 14b made of the aluminum-silicon alloy single layer, the aluminum of the electrode 14b and the silicon dioxide of the oxide film 12b react with each other by the heat treatment at 500 ° C. or more, and the silicon substrate 11b and the alloy are formed. The electrode 14b is short-circuited.

On the other hand, when the polycrystalline silicon film 13 is interposed, such a short circuit phenomenon between the metal electrode 14 and the silicon substrate 11 is prevented. Further, when such a polycrystalline silicon film 13 is interposed, the interface state is reduced and the capacitor characteristics are improved. Further, no significant change in the flat band voltage due to the addition of the polycrystalline silicon film 13 is detected. As described above, by using the metal electrode 14 having a two-layer structure of aluminum-silicon alloy / polycrystalline silicon, it is possible to form a good MOS structure that can withstand the heat treatment at 500 ° C.

Such an experiment was similarly performed on molybdenum Mo and tungsten W as the material of the metal electrode 14. Hereinafter, description will be given with reference to FIG. The tungsten formed directly on the oxide film 12b was peeled off without adhering to the oxide film 12b, and the capacitor was not formed. Further, regarding molybdenum, although peeling could be prevented by devising the conditions for sputtering when forming the metal electrode 14b, it was confirmed that the adhesion to the oxide film 12b is relatively low.

However, as in the structure shown in FIG.
4a and the oxide film 12a, when the polycrystalline silicon layer 13 is formed, regardless of whether sputtering is performed using molybdenum or tungsten to form the metal electrode 14a, regardless of the sputtering conditions. Adhesion is not improved. Regarding the capacitor characteristics, as seen in the case of the aluminum-silicon alloy as described above, in the case where the polycrystalline silicon film 13 is present, the interface state is slightly smaller and good MOS characteristics are obtained. . This is considered to be the result of the radiation damage during sputtering being reduced by the presence of the polycrystalline silicon film 13.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the thin film transistor 1 shown in FIG. A manufacturing process of the thin film transistor 1 will be described with reference to FIGS. 1 and 4.
For example, glass substrate 2 made of borosilicate glass or the like is organically washed, then acid-washed, and then polycrystalline silicon is formed in a volume of 1000 Å by a vacuum deposition method. The formation conditions are as follows: substrate temperature 500 ° C., vacuum degree 3 × 10 ⁻⁵ Pa, film formation rate 1 A / se.
c. The active layer 3 was formed on the polycrystalline silicon thus formed by a photolithography method and a plasma etching method using a sulfur hexafluoride gas, and the remaining portion was removed. The cross section at this stage is shown in Fig. 4 (1).
Shown in.

Next, the surface of the glass substrate 2 and the active layer 3 were covered to form a silicon dioxide film. This formation is performed by using the atmospheric pressure CVD method using monosilane gas and oxygen gas, and the substrate temperature is 420.
At a temperature of 1000 ° C., a silicon dioxide film thickness of 1000 liters was formed to form the gate insulating film 4. This sectional view is shown in FIG. 4 (2).

At the position corresponding to the active layer 3 on the surface of the gate insulating film 4, a polycrystalline silicon film is deposited by 500 Å using the vacuum deposition method under the same conditions as described above, and then an aluminum-silicon alloy is deposited by the sputtering method. After depositing 5000 Å, the polycrystalline silicon layer 5 and the conductor layer 6 forming the electrode layer 7 are left by a photolithography method,
The remaining part was removed by etching. This cross section is the fourth
It is shown in Figure (3).

A 500 Å silicon dioxide film 15 is formed by a normal pressure CVD method to prevent contamination during ion implantation, which will be described later, and boron ions (B ⁺ ) at 70 keV are 3 × 10 ¹⁵ / cm ²
Only the active layer 3 was injected. A cross section at this stage is shown in FIG.

After the surface of the silicon dioxide film 15 was etched to a depth of 200Å, a silicon dioxide film serving as an interlayer insulating film was formed as a second insulating film 8 with a film thickness of 5000Å by atmospheric pressure CVD. Then, in order to activate the boron implanted in the active layer 3, furnace annealing was performed at 500 ° C. for 1 hour in a nitrogen atmosphere. A cross section at this stage is shown in FIG.

Next, in order to form the source electrode and the drain electrode, through holes 16 and 17 penetrating the second insulating film 8 and the gate insulating film 4 and reaching the surface of the active layer 3 are formed by a photolithography method. After that, after depositing an aluminum-silicon alloy film at a thickness of 5000 Å, the source electrode 18 and the drain electrode 19 were formed into a desired shape by the photolithography method again. A sectional view in this state is shown in FIG. 4 (6). After that, annealing was performed at 440 ° C. for 30 minutes in a hydrogen atmosphere.

The manufacturing process of the thin film transistor 1 as described above is all performed in a temperature range of 500 ° C. or less, and the source electrode 18 is formed by the self-alignment method as described above while using the aluminum-silicon alloy for the gate electrode layer 7. And the drain electrode 19 was formed. Therefore, the wiring resistance of the gate electrode layer 7 can be suppressed to be sufficiently small, and unlike the case where the gate electrode layer 7 is formed of a single substance of polycrystalline silicon, the channel region 20 in the active layer 3 (double hatched line in FIG. 4) is used. It is possible to suppress the radiation damage to (), and to realize good MOS characteristics.

FIG. 5 is a graph showing the gate voltage dependence of the source / drain current of the thin film transistor 1 manufactured by the manufacturing process described above. Please refer to FIG. 4 and FIG. Here, in the thin film transistor 1 manufactured by the manufacturing process shown in FIG. 4, the channel length is 4 μm.
m, the channel width is 6 μm, and the bias voltage of the drain electrode 19 with respect to the source electrode 18 is −0.8V. FIG. 5 is a graph showing the gate voltage dependence under this condition. As shown in FIG. 5, the source-drain current ratio associated with the on / off switching of the thin film transistor 1 is
It has a value of about 10 ⁶ . Also, the mobility is 8.6 cm ² / Vs.
ec, which shows extremely good characteristics.

In the above-described embodiment, for example, in forming the conductor layer 6,
Although aluminum-silicon alloy was used, other titanium Ti, molybdenum, tungsten, tantalum T
Metals such as a, zirconium Zr, and aluminum, alloys containing these metals as main components, or materials having high conductivity such as compounds of these metals and silicon may be used. In addition, although the electrode layer 7 has a two-layer structure in the above-described embodiments, it is not limited to such a two-layer structure and may have a three-layer structure such as molybdenum / molybdenum silicide / polycrystalline silicon. Also,
As the gate insulating film 4, although the silicon dioxide film is formed by the normal thickness CVD method in the above-described embodiment, the silicon oxide film SiO _x formed by the plasma CVD method, the low pressure CVD method, the photo CVD method, the sputtering method, etc. Silicon nitride film SiN _x , silicon oxynitride film SiO _x Ny,
Alumina Al ₂ O ₃ or aluminum nitride AlN may be used. Further, the present invention does not limit the types of polycrystalline silicon and conductors used and the manufacturing method.

Further, the present invention does not limit the presence or absence of doping in the channel portion in the manufacture of transistors or the like, the amount of impurities implanted into the source and drain electrodes, and the type of the implanted impurity element with respect to the gate electrode structure.

EFFECTS OF THE INVENTION As described above, according to the present invention, the gate electrode layer of the thin film transistor is configured by a plurality of layers including a polycrystalline silicon layer containing no impurities and a conductor layer. Therefore, the resistance of the gate electrode can be reduced and the adhesion with the gate insulating film can be improved, and since such a manufacturing process can be performed in a relatively low temperature range, the material of the conductor layer used. The range of selection can be remarkably expanded, and the reliability of the semiconductor device due to the use of the material of the conductor layer used can be remarkably improved.

Further, the response speed can be improved by including, in the electrode layer, a polycrystalline silicon layer having a predetermined film thickness or less and to which impurities are not added. In the operation of charging / discharging at a predetermined frequency or higher, the high resistance polycrystalline silicon layer to which impurities are not added can be regarded as an insulator, and no operational problem occurs.

[Brief description of drawings]

FIG. 1 is a sectional view of a thin film transistor 1 according to an embodiment of the present invention, FIGS. 2 and 3 are sectional views for explaining the principle of the present invention, and FIG. 4 is a process for manufacturing the thin film transistor 1. A sectional view and FIG. 5 are graphs for explaining the dependence of the source / drain current of the thin film transistor 1 on the gate voltage. DESCRIPTION OF SYMBOLS 1 ... Thin film transistor, 2 ... Glass substrate, 3 ... Polycrystalline silicon active layer, 4 ... Gate insulating film, 5 ... Polycrystalline silicon layer containing no impurities, 6 ... Conductor layer, 7 ... Gate electrode layer, 9 ... Source electrode 10 ... Drain electrode, 20 ... Channel region

Claims (1)

[Claims] 1. A polycrystalline semiconductor active layer having source / drain regions formed on one surface of a base material made of an insulating material; a first insulating layer covering the polycrystalline semiconductor active layer; A first insulating layer, a polycrystalline silicon layer not doped with impurities and a conductor layer, and The thickness of the undoped polycrystalline silicon layer is dp, the thickness of the first insulating layer is di, the dielectric constant of the undoped polycrystalline silicon layer is εp, and the dielectric constant of the first insulating layer is When the ratio is εi, (εp / εi) di >> dp, a gate electrode layer, a second insulating layer that covers the first insulating layer and the gate electrode layer, and the first and second insulating layers. Through the layer and electrically connect to the polycrystalline semiconductor active layer, respectively. Thin film transistor comprising a source electrode and a drain electrode passing.