JPH0618436A - Inspection unit of printed circuit board - Google Patents

Abstract

PURPOSE:To detect a defect in and around a through hole aright without a large memory capacity. CONSTITUTION:A forbidden area image signal FS being obtained by operating a logical product (OR) of a pattern image signal PS of a printed circuit board 1 to be a reference, a reference image signal MS being secured by operating a logical sum (OR) of a hole image signal HS and an expanded hole image signal EHS which is lowered in the picture element density of the hole image signal HS, is used for setting a forbidden area in a comparison inspection at a comparing check part 21. Any defect in and around the through hole 4 will in no case be overlooked without requiring a large memory capacity for a forbidden are memory 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board inspection apparatus for inspecting a wiring pattern on a printed circuit board for defects.

[0002]

2. Description of the Related Art FIG. 9 is a partial perspective view of a printed circuit board. The printed circuit board 1 has a conductive wiring pattern 3 on the surface of the insulating substrate 2 or both front and back surfaces. The printed board 1 is provided with through holes 4 for the purpose of mounting circuit components or connecting wiring patterns on the front and back. The wiring pattern 3 includes a line portion 5 and a land 6 formed around the through hole 4. Note that, in FIG. 9 and other drawings described later, the shape of the land 6 is a quadrangle for convenience of illustration, but other shapes such as a circle are also common.

FIG. 10 is a plan view of the land 6 and its surroundings. The printed circuit board 1 is, as shown in FIG.
The through hole 4 is designed to be located at the center of the land 6. However, the printed circuit board 1 as a product
Is, for example, as shown in FIG.
The position is usually deviated from the designed position to some extent. By the way, when the through-hole 4 is a small-diameter through-hole called a mini via hole, the positional deviation of the small-diameter through-hole 4 does not hinder the function of the printed circuit board 1. Therefore, the printed circuit board 1 should not be determined to be defective. In the following description, the mounting through-hole and the conduction through-hole will be simply referred to as the through-hole 4 without distinction.

A comparison method is known as one of the methods for inspecting the wiring pattern 3 of the printed circuit board 1. In this comparison method, an image of the printed circuit board 1 (first printed circuit board) to be used as a reference and an image of the printed circuit board 1 (second printed circuit board) to be inspected are superposed and compared, and a predetermined level or more is determined. When there is a difference, it is a method of determining the difference portion as a defect.

In order to exclude the above-mentioned displacement of the through hole 4 from the defect detection target, the conventional printed circuit board inspection apparatus excludes the region corresponding to the through hole 4 in the image of the printed circuit board 1 from the inspection target. A method for setting a prohibited area is adopted (for example, Japanese Patent Laid-Open No. 1-1804).
No. 04 publication). In the inspection apparatus based on the comparison method described above, it is necessary to set this prohibited area in both images of the printed circuit board 1 to be the reference and the printed circuit board 1 to be inspected. Therefore, in the inspection apparatus based on the comparison method, an image signal (reference image signal) representing an image of the printed circuit board 1 to be used as a reference (reference image signal) and an image signal representing a prohibited area in the reference image (inhibited area image signal) Must also be stored in memory.

At this time, if the image resolution in the prohibited area image signal is set to be the same as the image resolution in the reference image signal, the prohibited area having the same capacity as the memory (storage capacity) for storing the reference image signal. It becomes necessary to prepare a memory for storing the image signal. This results in a significant cost of the inspection device.

Therefore, for example, Japanese Patent Laid-Open No. 1-180404
In the conventional inspection apparatus described in Japanese Patent Laid-Open Publication No. 2004-242242, a method is adopted in which the image resolution of the prohibited area image signal is made coarser than that of the reference image signal to save the storage capacity of the memory for storing the prohibited area image signal. In this inspection apparatus, in the reference image including the wiring pattern 3 and the through hole 4 shown in FIG. 11, each rectangular area surrounded by the dotted line in the drawing is set as the minimum unit (pixel) of the image, and as an image corresponding to the through hole 4. The prohibited area 7 is set. The pixels in the prohibited area 7 are coarser than the pixels in the wiring pattern 3 and the through holes 4, so that the prohibited area 7 occupies an area outside the through hole 4 as shown by the hatched area in the drawing.

[0008]

In recent years, the density of the wiring patterns 3 has been increased, and the spacing between the adjacent wiring patterns 3 tends to be narrowed. For this reason,
For example, as shown in FIG. 11, the line portion 5 a disposed adjacent to the through hole 4 may overlap the prohibited area 7. On the other hand, as a result of increasing the density of the wiring patterns 3, as shown in FIG.
In, for example, the pattern short-circuit portion 8 which is one kind of defect is easily generated between the land 6 and the adjacent line portion 5a. When comparing the image of the printed circuit board 1 to be inspected (image to be inspected) with the reference image, if the prohibited area 7 partially overlaps the line portion 5a as described above, the pattern short-circuit portion 8 concerned. Is prohibited area 7
Therefore, it is excluded from the defect detection target. That is, the conventional inspection device has the through hole 4
There is a problem that defects such as the pattern short-circuit portion 8 in the vicinity of are missed.

The present invention is intended to solve the above-mentioned drawbacks of the conventional device, does not require a large storage capacity, does not miss defects in the vicinity of the through hole, and is It is an object of the present invention to provide a printed circuit board inspection device that does not determine a positional deviation as a defect.

[0010]

A printed circuit board inspection apparatus according to the present invention compares the image of a first printed circuit board to be a reference with the image of a second printed circuit board to be inspected, and A printed circuit board inspection device for detecting a defect in a wiring pattern of a second printed circuit board, comprising: (a) reading an image of the first printed circuit board to determine a wiring pattern of the first printed circuit board; A first which represents an image and has a binary signal on a pixel-by-pixel basis
And a first hole image signal that expresses an image of a through hole included in the first printed circuit board and has a binary signal in the pixel unit,
By reading the image on the second printed circuit board,
Representing the image of the wiring pattern of the printed circuit board of
A second pattern image signal having a binary signal in the pixel unit, and a second hole image signal having a binary signal in the pixel unit that expresses an image of a through hole included in the second printed circuit board; And (c) first logical sum calculating means for calculating a logical sum of the first pattern image signal and the first hole image signal to obtain a reference image signal, and (c) ) Pixel density conversion means for converting the first hole image signal into an enlarged hole image signal having a binary signal in a pixel unit having a lower density than the pixel,
(D) first storage means for storing the reference image signal,
(E) second storage means for storing the enlarged hall image signal, and (f) reading the reference image signal from the first storage means and reading the enlarged hall image signal from the second storage means. A logical product calculating means for calculating a logical product of the reference image signal and the enlarged hole image signal to obtain a prohibited area image signal, (g) the second pattern image signal and the second hole Second logical sum calculating means for calculating a logical sum with the image signal to obtain an inspection target image signal; and (h) calculating an exclusive logical sum of the reference image signal and the inspection target image signal, Get the difference image signal,
Further, in the image area represented by the difference image signal, a predetermined area is excluded in the area excluding the first forbidden area represented by the forbidden area image signal and the second forbidden area represented by the second hole image signal. If there is a part that includes an operator that includes the number of pixels of, it is determined that the part is defective,
A comparison inspection unit that outputs a determination signal indicating a defect.

[0011]

In the inspection apparatus according to the present invention, the reference image signal obtained by calculating the logical sum of the first pattern image signal of the first printed circuit board and the first hole image signal to be the reference, and the first image signal The prohibited area image signal obtained by calculating the logical product of the expanded hole image signal in which the pixel density of the hole image signal is lowered is used for setting the prohibited area in the comparison inspection by the comparison inspection means. Therefore, the defect in the vicinity of the through hole is not overlooked.

In the inspection apparatus according to the present invention, further, the logical sums of the pattern image signal and the hole image signal on both the first printed circuit board to be the reference and the second printed circuit board to be inspected are compared and inspected. Moreover, the prohibited area also includes areas corresponding to both through holes. Therefore, the displacement of the through hole is not mistakenly determined to be a defect.

In the inspection apparatus according to the present invention, the first
Since the enlarged hole image signal in which the pixel density of the hole image signal is converted to reduce the pixel density is used for setting the prohibited area, the storage capacity of the second storage means provided for setting the prohibited area is set to the reference image signal. Can be set smaller than the storage capacity of the first storage means for storing

[0014]

【Example】

<1. Image Reading Unit> FIG. 1 is an overall block diagram of a printed circuit board inspection apparatus according to an embodiment of the present invention.
This printed circuit board inspection device executes the inspection of the printed circuit board 1 by comparing the inspection target image of the printed circuit board 1 with the reference image thereof.

The printed circuit board 1 is placed on a carrier table 10 having a horizontally moving mechanism. The optical head 11 scans as the transport table 10 moves,
The surface of the printed circuit board 1 having the wiring pattern 3 and the through holes 4 is optically read. The optical head 11 outputs the analog electric signals PSa and HSa, which are significantly different in intensity depending on the presence or absence of the wiring pattern 3 and the through hole 4 in accordance with the scanning, and transmit the analog electric signals PSa and HSa to the A / D converters 12 and 13. The A / D conversion units 12 and 13 convert these analog electric signals PSa and HSa into digital electric signals for each minute region (pixel) arranged along the scanning direction, and the binarization processing unit 14 and, respectively. Send to 15. The binarization processing units 14 and 15 compare these digital electric signals with a predetermined threshold value, respectively, and have a digital pattern image having two values "1" and "0" based on the result. The signal PS and the hall image signal HS are converted. As a result, the pattern image signal PS has the value “1” in the area where the wiring pattern 3 exists,
It has the value "0" in non-existing regions. Similarly, the hole image signal HS has a value “1” in the area where the through hole 4 exists and a value “0” in the area where it does not exist. As a result, the pattern image signal PS and the hole image signal HS represent the read images of the wiring pattern 3 and the through holes 4, respectively. Details of a device for reading the image of the printed circuit board 1 to obtain the pattern image signal PS and the hole image signal HS are disclosed in, for example, Japanese Patent Application Laid-Open No. 4-76444 by the same applicant.

<2. Processing of Printed Circuit Board Image to be Referenced> When the image of the printed circuit board 1 to be used as a reference is read, both the data selectors SEL1 and SEL2 are connected to the contact a. As a result, the pattern image signal PS and the hole image signal HS are input to the OR operation unit 16 (first OR operation unit), and the hole image signal HS is simultaneously input to the pixel density conversion unit 17 (pixel density conversion unit). Is also entered. FIG. 2A is a plan view showing an example of the wiring pattern 3 and the through hole 4 of the printed circuit board 1 to be the reference. In this example, the through hole 4 is eccentric from the center position of the land 6. The pattern image signal PS and the hole image signal H obtained for the printed circuit board 1 of this example
2B and 2C are plan views of a portion of the image represented by S corresponding to FIG. 2A, respectively. In the following figures depicting an image, the shaded areas represent areas where the corresponding image signal has the value "1", and the other areas represent the area having the value "0".

The logical sum operation unit 16 receives the pattern image signal P.
The logical sum of S and the hall image signal HS is calculated and output as the reference image signal MS. FIG. 3A shows a reference image signal M
It is a top view which shows the image which S represents. Reference image signal M
S is a value "in a region where at least one of the pattern image signal PS and the hole image signal HS has a value" 1 ".
1 ″. The output standard image signal MS is stored in the reference image memory 18 (first storage unit).

The pixel density conversion unit 17 converts the input Hall image signal HS into an image signal having a binary signal for each pixel having a density lower than the pixel density of the Hall image signal HS, and an enlarged Hall image signal. Output as EHS. As a result, the image represented by the enlarged hall image signal EHS is shown in FIG.
It becomes as shown in (b). In FIG. 3B, each rectangle surrounded by a dotted line represents a pixel of the enlarged hall image signal EHS. The pixel density of the enlarged hall image signal EHS is set coarser than the pixel density of the hall image signal HS. Therefore, the through hole 4 having the value "1" in the image represented by the enlarged hole image signal EHS
The area EHI corresponding to the area occupies an area protruding outside the through hole 4. The enlarged hall image signal EHS is stored in the prohibited area memory 19 (second storage means).

Reference image memory 18 and prohibited area memory 1
As the storage medium 9, a writable storage medium having a high writing and reading speed, such as a so-called RAM, is preferably used. As described above, the enlarged hall image signal EHS
Since the pixel density of is set lower than the pixel density of the standard image signal MS, the prohibited area memory 19 has an advantage that the storage capacity may be smaller than that of the reference image memory 18. For example, the pixel density of the enlarged hall image signal EHS is set to one tenth of the pixel density of the reference image signal MS. In this case, the storage capacity of the prohibited area memory 19 may be one tenth of the reference image memory 18. Therefore, the cost for newly providing the prohibited area memory 19 in addition to the reference image memory 18 can be ignored compared to the cost of the reference image memory 18 itself.

<3. Processing of Printed Circuit Board Image to be Inspected> After reading the image of the printed circuit board 1 to be used as a reference, the printed circuit board 1 to be inspected is transferred to the transport table 10.
Place it on the top and read it again. At this time, the data selectors SEL1 and SEL2 are both connected to the contact b. The pattern image signal P of the printed circuit board 1 to be inspected
S and the Hall image signal HS are processed by the logical sum operation unit 20 (second
And the hall image signal HS is simultaneously input to the comparison inspection unit 21 (comparison inspection means).

As an example, in the printed circuit board 1 to be inspected, the wiring patterns 3 and the through holes 4 are shown in FIG. 12 in the part to be compared with the part shown in FIG. 2 (a) of the printed circuit board 1 to be the reference. Suppose it is on the street. In this example, the printed circuit board 1 has a pattern short circuit portion 8 as a defect, and at the same time, the position of the through hole 4 in the land 6 is the reference of the printed circuit board 1 shown in FIG.
It is eccentric to a position different from the part shown in (a). 4A and 4B are plan views of a portion corresponding to FIG. 12 of an image represented by the pattern image signal PS and the hole image signal HS obtained on the printed circuit board 1 of this example, respectively. Shown in.

The logical sum operation unit 20 receives the pattern image signal P
The logical sum of S and the hall image signal HS is calculated and output as the inspection target image signal OS. FIG. 5 is a plan view showing an image represented by the inspection target image signal OS. The inspection target image signal OS has the value “1” in the area where at least one of the pattern image signal PS and the hole image signal HS has the value “1”. Output inspection target image signal OS
Is input to the comparison inspection unit 21.

<4. Comparison inspection unit and its peripheral part> The comparison inspection unit 21 compares the inspection target image signal OS with the reference image signal MS and if there is a difference of a predetermined value or more, determines that portion as a defect and responds to the determination result. The defect determination signal JS having the specified value is output. In synchronization with the scanning of the printed circuit board 1 to be inspected by the optical head 11, the inspection target image signal OS is input to the comparison inspection unit 21, and at the same time, the standard image signal MS is compared and inspected from the reference image memory 18. Part 2
1 and the logical product calculation unit 22 (logical product calculation means), and the enlarged hall image signal E from the prohibited area memory 19.
HS is input to the logical product calculation unit 22.

The logical product calculating section 22 calculates the logical product of the reference image signal MS and the enlarged hall image signal EHS, and outputs the calculation result as the prohibited area image signal FS. FIG. 6 is a plan view showing an image (prohibited area image) represented by the prohibited area image signal FS. In the prohibited area image signal FS, both the reference image signal MS and the enlarged hall image signal EHS have values "
The area having the value "1" has the value "1". Therefore, the prohibited area image signal FS has the value "0" in the area where neither the wiring pattern 3 nor the through hole 4 exists. The area image signal FS is input to the comparison inspection unit 21. In the comparison inspection unit 21, the area where the inhibition area image signal FS has the value "1" (inhibition area F as described later).
The inspection is prohibited in (D1, first prohibited area).

The inspection object image signal OS and the reference image signal MS input to the comparison inspection unit 21 are input to the difference detection unit 23. The difference detection unit 23 calculates the exclusive OR of the input inspection object image signal OS and the reference image signal MS, and outputs the calculation result as the difference image signal DIS. Figure 7
FIG. 6 is a plan view showing an image DII represented by the differential image signal DIS. The differential image signal DIS is the inspection target image signal O
It has the value "1" in the region where the value differs between S and the reference image signal MS. The position of the through hole 4 and the presence or absence of the pattern short-circuit portion 8 are different between the portion of the printed board 1 to be the reference shown in FIG. 2A and the portion of the printed board 1 to be inspected shown in FIG. . Therefore, in the differential image signal DIS, the portion where the through hole 4 protrudes from the land 6 and the pattern short-circuit portion 8 have the value “1”. Difference image signal D shown in FIG.
In the area having the value “1” in IS, the pattern short-circuit portion 8 is the only portion to be determined as a defect.

The differential image signal DIS is supplied to the inspection prohibition setting section 24.
Is input to. The prohibited area image signal FS input to the comparison inspection unit 21 and the hole image signal HS of the printed circuit board 1 to be inspected are also input to the inspection inhibition setting unit 24 at the same time. The inspection prohibition setting unit 24 calculates the logical product of three signals of the inversion signal of the prohibited area image signal FS, the inversion signal of the hall image signal HS, and the difference image signal DIS, and outputs the operation result as the corrected difference image signal MDIS. To do. The corrected differential image signal MDIS is the value of the differential image signal DIS shown in FIG.
In the area having 1 ”, the restricted area FD1 and the area where the hole image signal HS of the printed circuit board 1 to be inspected has the value“ 1 ”(the prohibited area FD2, the second prohibited area) are excluded. As a result, the corrected differential image signal MDIS has the value “1” only in the pattern short-circuit portion 8. The corrected differential image signal MDIS is input to the determination unit 25. .

The determination section 25 applies the operator OP (FIG. 8) to the input corrected difference image signal MDIS to determine the presence / absence of a defect. That is, the determination unit 25 determines that in the area having the value “1” in the corrected difference image signal MDIS,
If there is a portion included in the operator OP, which is a cluster (cluster) of a predetermined number of pixels (for example, 3 pixels × 3 pixels), this portion is determined as a defect. In the example shown in FIG. 8, since the pattern short-circuit portion 8 includes the operator OP,
The pattern short section 8 is determined to be defective. Judgment unit 25
Outputs a defect determination signal JS having a value corresponding to the determination result. The defect determination signal JS has two values of “1” and “0”, respectively, corresponding to the presence or absence of a defect.

The details of the difference detecting section 23 and the determining section 25 are described in, for example, Japanese Patent Laid-Open No. 62-1 of the same applicant.
It is disclosed in Japanese Patent No. 40009.

As described above, the comparison inspection unit 21 excludes the prohibited area FD1 and the prohibited area FD2 from the objects of the comparison inspection. Therefore, the inspection apparatus of this embodiment does not determine the positional deviation of the through hole 4 as a defect. Further, the prohibited area FD1 is processed by the AND operation unit 22 into the reference image signal M
Since it is obtained from the logical product of S and the enlarged hole image signal EHS, the area between the through hole 4 and the line portion 5a adjacent thereto is not included. Therefore, the device of this embodiment is
It is possible to determine a defect in the vicinity of the through hole 4 on the printed circuit board 1 to be inspected, for example, a defect without missing the pattern short-circuit portion 8. Further, since the pixel density of the enlarged hall image signal EHS is set lower than the pixel density of the standard image signal MS, the storage capacity of the prohibited area memory 19 to be additionally provided in the reference image memory 18 is the reference image memory 18. It should be sufficiently small compared to. That is,
In the device of this embodiment, a large storage capacity to be newly added is not required, the displacement of the through hole 4 is not judged as a defect, and the defect in the vicinity of the through hole 4 is not overlooked.

[0030]

According to the inspection apparatus of the present invention, the reference image signal obtained by calculating the logical sum of the first pattern image signal of the first printed circuit board and the first hole image signal to be the reference, The forbidden area image signal obtained by calculating the logical product of the enlarged Hall image signal of which the pixel density of the No. 1 hole image signal is low is used for setting the forbidden area in the comparison inspection by the comparison inspection means. Therefore, the defect in the vicinity of the through hole is not overlooked.

In the inspection apparatus of the present invention, further, the logical sums of the pattern image signal and the hole image signal on both the first printed circuit board to be the reference and the second printed circuit board to be inspected are compared and inspected. Moreover, the prohibited area also includes areas corresponding to both through holes. Therefore, the displacement of the through hole is not mistakenly determined to be a defect.

Further, in the inspection apparatus of the present invention, the enlarged hole image signal in which the pixel density of the first hole image signal is converted to lower the pixel density is used for setting the prohibited area, so that the prohibited area is set. The storage capacity of the provided second storage means can be set smaller than the storage capacity of the first storage means for storing the reference image signal.

That is, the inspection apparatus of the present invention does not require a large storage capacity, prevents the defect near the through hole from being overlooked, and prevents the misalignment of the position of the through hole from being erroneously determined as a defect. have.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a partial plan view showing a printed circuit board to be a reference and an image thereof.

FIG. 3 is a partial plan view showing an image of a printed circuit board to be a reference.

FIG. 4 is a partial plan view showing a printed circuit board to be inspected and its image.

FIG. 5 is a partial plan view showing an image of a printed circuit board to be inspected.

FIG. 6 is a partial plan view showing an image of a printed circuit board to be a reference.

FIG. 7 is a partial plan view showing an image represented by a differential image signal.

FIG. 8 is a partial plan view showing an image represented by a corrected difference image signal.

FIG. 9 is a partial perspective view of a printed circuit board.

FIG. 10 is a partial plan view showing a land and its periphery.

FIG. 11 is a partial plan view showing an image of a printed circuit board to be a reference.

FIG. 12 is a partial plan view of a printed circuit board to be inspected.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 printed circuit board 3 wiring pattern 4 through hole 16 logical sum operation part (first logical sum operation means) 17 pixel density conversion part (pixel density conversion means) 18 reference image memory (first storage means) 19 prohibited area memory ( Second storage means) 20 Logical sum calculation section (second logical sum calculation means) 21 Comparison inspection section (comparison inspection means) 22 Logical product calculation section (logical product calculation means) PS pattern image signal HS Hall image signal MS reference Image signal EHS Enlarged hall image signal FS Prohibited area image signal OS Inspection target image signal DIS Differential image signal FD1 Prohibited area (First prohibited area) FD2 Prohibited area (Second prohibited area) OP Operator JS Defect judgment signal

Claims (1)

[Claims] 1. A defect in a wiring pattern of the second printed circuit board is detected by comparing an image of a first printed circuit board to be a reference with an image of a second printed circuit board to be inspected. A printed circuit board inspection apparatus, comprising: (a) a first printed circuit board image is read to represent an image of a wiring pattern of the first printed circuit board, and a binary signal is provided for each pixel. And a first hole image signal that expresses an image of a through hole included in the first printed circuit board and that has a binary signal in the pixel unit. A second pattern image signal having a binary signal for each pixel, which is obtained by expressing the image of the wiring pattern of the second printed circuit board by reading the image;
An image reading unit that expresses an image of a through hole included in the second printed circuit board and obtains a second hole image signal having a binary signal for each pixel, and (b) the first pattern image signal. And (1) a first OR image calculating means for obtaining a reference image signal by calculating a logical OR of the first hole image signal and the first hole image signal, and (c) the first hole image signal having a lower density than the pixel. Pixel density conversion means for converting into a magnified Hall image signal having a binary signal on a pixel-by-pixel basis, (d) first storage means for storing the reference image signal, and (e) storing the magnified Hall image signal. Second storage means,
(F) The reference image signal is read from the first storage means, the enlarged hall image signal is read from the second storage means, and the logical product of the reference image signal and the enlarged hall image signal is obtained. A logical product calculating means for calculating and obtaining a prohibited area image signal; and (g) calculating a logical sum of the second pattern image signal and the second hole image signal to obtain an inspection target image signal. And (h) an exclusive logical sum of the reference image signal and the inspection target image signal to obtain a difference image signal, and further to calculate an image area of the image region represented by the difference image signal. Among them, an operator including a predetermined number of pixels is included in an area excluding the first forbidden area represented by the forbidden area image signal and the second forbidden area represented by the second hole image signal. If there is a part Determines the portion as a defect inspection apparatus of a printed board and a comparison inspection means for outputting a determination signal indicating a defect.