JPH06188428A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device equipped with a memory transistor having excellent memory property. CONSTITUTION:The source region 41 of a memory transistor MTr 40 is made into triple diffusion structure by thickening the concentration of diffused impurities thereby forming an n-impurity diffused layer 41b, an n<+>-impurity diffused layer 41a, and n<+>-impurity diffused layer 41c from outside, and is put in the concentration of diffused impurities suitable for the outflow of charge. On the other hand, a drain region 42 is made into structure equipped with a p-type pocket, and is put in the concentration of diffused impurities suitable for injection of charge, different from the source region 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPRO.
The present invention relates to a semiconductor integrated circuit device including a plurality of nonvolatile memory elements such as M (Erasable Programmable Read On Memory) for storing information, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, various semiconductor integrated circuit devices, such as a flash EEPROM, having a non-volatile memory element for storing data by injecting and extracting charges have been proposed. FIG. 23 is a schematic sectional view schematically showing an example of the structure of a memory array according to a conventional semiconductor integrated circuit device. In FIG. 23, MA is a memory array and MTr is a flash memory transistor. The memory transistor MTr includes a P-type silicon substrate 1 and a P-type silicon substrate 1.
On the N-type source region 2 and the N-type drain region 3 formed at a predetermined interval on the surface layer portion of the type silicon substrate 1, and on the channel region 4 formed so as to be sandwiched between the source region 2 and the drain region 3, A tunnel oxide film 5 provided in a state of bridging the source region 2 and the drain region 3 and capable of tunneling charges generated in the channel region 4;
A floating gate 6 provided on the tunnel oxide film 5 for accumulating charges tunneled through the tunnel oxide film 5.
And an ONO (oxide-nitride-oxide) film 7 provided on the floating gate 6 for confining charges accumulated in the floating gate 6 for a long time, and a predetermined control when writing, reading and erasing data. And a control gate 8 to which a voltage is applied.

The source region 2 is composed of an N ⁺ impurity diffusion layer 2a and an N ⁻ type impurity diffusion layer 2b deeply formed so as to surround the N ⁺ type impurity diffusion layer 2a in order to improve the withstand voltage. It has a double diffusion structure. On the other hand, the drain region 3 has a single drain structure including only an N ⁺ -type impurity diffusion layer, and the bit line 9
Has been contacted. The bit line 9, the floating gate 6 and the control gate 8 are insulated from each other by an interlayer insulating film 10, and a passivation film 11 is laminated on the bit line 9.

That is, the memory transistor MTr
The floating gate 6 is the tunnel oxide film 5, ON
Surrounded by the insulating films of the O film 7 and the interlayer insulating film 10,
It is called a stack gate type or a floating gate type because it has no external connection and accumulates charges in the floating gate 6. FIG. 24 is an equivalent circuit diagram of the memory array. The memory array MA is
As shown in FIG. 24, it has a 1-cell / 1-transistor structure, and four memory cells including a memory cell MC1 surrounded by a dotted line are arranged. That is, the memory transistors MTr1, MTr2, MTr3, MTr4 are arranged in the row direction X.
And are arranged in a matrix in the column direction Y.

The word line WL1 is connected to the control gates of the memory transistors MTr1 and MTr2 arranged in the row direction X, and the word line WL2 is connected to the control gates of the memory transistors MTr3 and MTr4 arranged in the row direction X. ing. In addition, the memory transistors MTr1 and MT arranged in the column direction Y
The bit line BL1 is connected to the source of r3, and the memory transistors MTr2 and MTr4 arranged in the column direction Y are arranged.
The bit line BL3 is connected to the source of the. Furthermore, the memory transistors MTr1, which are adjacent in the row direction X,
The drain of MTr2 is connected in series, and the bit line BL2 is connected to the connection intermediate point. Similarly, memory transistors MTr3, which are adjacent in the row direction X,
The drain of MTr4 is connected in series, and the bit line BL2 is connected to the connection intermediate point. That is, the memory transistors MTr1, which are adjacent in the row direction X,
The drains of MTr2, MTr3, and MTr4 share the bit line BL2.

In the following description, the memory transistors MTr1, MTr2, MTr3, MTr4 are collectively referred to as "memory transistor MTr". Data write, erase and read operations in the memory array MA will be described mainly with reference to FIG. 24 and Table 1. In Table 1, it is assumed that the memory cell MC1 shown in FIG. 24 is selected when writing data.

[0007]

[Table 1]

<Write (WRITE)> 0 V is applied to the word line WL2, the bit line BL1 and the substrate SUB are grounded to the ground (GND), and the word line is selected in order to select the memory cell MC1 for writing data. 12V is applied to WL1 and a write voltage of 5V is applied to the bit line BL2. Then, FIG. 25 (a)
As shown in FIG. 5, electrons having high energy, so-called hot electrons are generated at the boundary between the channel region 4 and the drain region 3 of the memory transistor MTr1, and the hot electrons are injected into the floating gate 6,
The data “0” is written. <Erase> For data erasing, batch erasing is performed. That is, the word lines WL1 and WL2 and the bit line BL2 are opened, and the substrate SU
B is grounded to the ground, and bit lines BL1 and B
An erase voltage of 12 V is applied to L3. Then, as shown in FIG. 25B, the memory transistor MTr
Between the floating gate 6 and the source region 2 of
A tunnel current is generated, whereby the electrons accumulated in the floating gate 6 flow out to the source region 2 and are removed, and the erased state of the data, that is, the data "1".
The writing state becomes. <Read (READ)> Regarding data reading, line batch reading is performed for each word line. That is, 0V is applied to the word line WL2, the bit lines BL1 and BL3 and the substrate SUB are grounded, and the sense voltage of 5V is applied to the word line WL1 and the voltage of 2V is applied to the bit line BL2. Then, if electrons are accumulated in the floating gate of the memory transistor, no channel is formed in the memory transistor and the memory transistor does not conduct. On the other hand, if electrons are not accumulated in the floating gate of the memory transistor, a channel is formed in the memory transistor and the memory transistor becomes conductive. By sensing the conduction or non-conduction of the memory transistor, the data stored in the memory transistor is read.

[0009]

By the way, in the above-mentioned memory transistor, the impurity diffusion concentration of the N ⁺ type impurity diffusion layer 2a in the source region 2 and the drain region 3 are increased.
The impurity diffusion concentration of the N ⁺ -type impurity diffusion layer is
It is preferable to set a unique density from the viewpoint of favorably writing and erasing data.

However, in the manufacturing process of the memory transistor, the N of the source region 2 shown in FIG.
⁺ -Type impurity diffusion layer 2a, and the N ⁺ -type impurity diffusion layer of the drain region 3, to be formed at the same time, N ⁺ -type impurity diffusion layer 2a and the N ⁺ -type impurity diffusion layer of the drain region 3 of the source region 2 It has the same impurity diffusion concentration. Therefore, there are the following problems.

If the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer in the drain region 3 is lower than the concentration suitable for writing data, the generation efficiency of hot electrons is lowered and the writing speed becomes slow. On the other hand, if the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer in the drain region 3 is higher than the concentration suitable for data writing, the writing speed is increased, but so-called drain disturb occurs. . That is, for example, 0 V on the word line WL2
12 V is applied to the word line WL1 in order to select the memory cell MC1 for writing data by applying
When a write voltage of 5V is applied to the bit line BL2, hot electrons are injected into the floating gate 7 of the memory transistor MTr1. However, when the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer in the drain region 3 is higher than the concentration suitable for writing data, as shown in FIG. 26, it is arranged in the column direction together with the selected memory cell MC1. Unselected memory cell MC3
Since the write voltage 5V is applied also to the drain of the memory transistor MTr3, if electrons are accumulated in the floating gate 6 of the memory transistor MTr3, the electrons in the floating gate 6 are extracted to the drain region 3 and unselected. The write state of the memory cell MC3 changes.

If the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer 2a of the source region 2 is lower than the concentration suitable for erasing data, the erasing breakdown voltage increases but the erasing speed becomes slow.
On the other hand, if the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer 2a in the source region 2 is higher than the concentration suitable for erasing data, the erasing breakdown voltage decreases and the erasing speed increases, but so-called over-erasing (over erasing) is performed. erase) occurs. That is, the bit line BL1 is opened, the substrate SUB is grounded, and the word lines WL1, WL2 are grounded or opened, and the bit line BL1 is grounded.
When the erase voltage 12V is applied to 2 and BL3, respectively, the electrons accumulated in the floating gate 6 of the memory transistor MTr flow out to the source region 2, as shown in FIG. However, when the impurity diffusion concentration of the N ⁺ -type impurity diffusion layer 2a in the source region 2 is higher than the concentration suitable for erasing data, as shown in FIG. 27B, the electrons accumulated in the floating gate 6 are collected. Excessively flow into the source region 2, and as a result, holes are accumulated in the floating gate 6.

Since the junction depth of the source region and the drain region has become shallower with the miniaturization of the device, the influence of the increase in the diffusion resistance of the source line cannot be ignored. In view of the above, it is an object of the present invention to provide a semiconductor integrated circuit device having excellent memory characteristics without causing drain disturb and excessive erasing, and a method for manufacturing the same.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect, wherein a plurality of information storage devices are provided on a single semiconductor substrate for storing information based on a predetermined integrated circuit design. A memory array in which the nonvolatile memory elements are arranged in a matrix along the row direction and the column direction;
What is claimed is: 1. A semiconductor integrated circuit device, comprising: a peripheral circuit arranged around the memory array, the peripheral circuit causing each nonvolatile memory element to perform a predetermined operation, wherein each nonvolatile memory element is a surface of the semiconductor substrate. Charge accumulation that is provided on a source region and a drain region formed at a predetermined interval in a layer and a channel region formed so as to be sandwiched between the source region and the drain region, and accumulates charges generated in the channel region A layer, and a gate provided on the charge storage layer and to which a predetermined control voltage is applied, the word line is connected to the gates of the respective nonvolatile memory elements arranged in the row direction, and the word lines are arranged in the column direction. Bit lines are connected to the source region and the drain region of each nonvolatile memory element, and the peripheral circuit is configured to have a gate and a drain of each nonvolatile memory element. Means for injecting the charge into the charge storage layer by applying a predetermined voltage between the charge storage layer and the drain region of the channel region to generate a charge having high energy in the vicinity of the drain region of the channel region; And a means for causing a predetermined voltage to be applied to the source region of the non-volatile memory element to cause the charge stored in the charge storage layer to flow out to the source region and be removed. The impurity diffusion concentration is set to be suitable for the outflow of the charges, and the drain region is set to an impurity diffusion concentration that is suitable for the injection of the charges and is different from that of the source region. The semiconductor integrated circuit device according to claim 2 is the semiconductor integrated circuit device according to claim 1, wherein the source region of each nonvolatile memory element is opposite to the semiconductor substrate having a predetermined first conductivity type. A source diffusion layer of the second conductivity type and an outer diffusion layer of the second conductivity type that is deeply formed so as to surround the source diffusion layer and has an impurity diffusion concentration set lower than that of the source diffusion layer. And a drain region of each nonvolatile memory element, the drain region having a second conductivity type opposite to the first conductivity type, and a source region of the drain diffusion layer. A diffusion pocket of the first conductivity type bonded to the end.

A method for manufacturing a semiconductor integrated circuit device according to a third aspect is a method for manufacturing the semiconductor integrated circuit device according to the second aspect, wherein the semiconductor substrate having a predetermined first conductivity type is non-volatile. A step of sequentially forming a charge storage layer and a gate of the non-volatile memory element on the memory element forming region, a mask is applied to the entire surface of the non-volatile memory element except the source forming region, and the semiconductor substrate is provided with the first conductivity type. The first ion of the opposite second conductivity type is deeply implanted, and subsequently the second ion of the second conductivity type having a lower concentration than the first ion is shallowly implanted, and the source diffusion is performed in a self-aligned manner. A step of forming a source region having a double diffusion structure in which the layer is surrounded by an external diffusion layer, and the entire surface of the nonvolatile memory element excluding the drain forming region is subjected to a mask to form a semiconductor substrate of the first conductivity type. Injecting ON obliquely and shallowly, and then deeply implanting ions of the second conductivity type, the step of forming a drain region in which the diffusion pocket is joined to the end of the source region of the drain diffusion layer in a self-aligned manner is included. It is a waste.

[0016]

In the semiconductor integrated circuit device according to claim 1, when a predetermined voltage is applied between the gate and the drain region of the nonvolatile memory element by the peripheral circuit, the selected nonvolatile memory element: Charge having high energy is generated in the vicinity of the drain region of the channel region, and this charge is injected into the charge storage layer.

At this time, the same predetermined voltage as that of the selected nonvolatile memory element is applied to the drain region of the non-selected nonvolatile memory element arranged in the column direction together with the selected nonvolatile memory element. However, the drain region of the nonvolatile memory element has a different impurity diffusion concentration from the source region,
Since the impurity diffusion concentration is set to be suitable for charge injection, even if the charge is accumulated in the charge storage layer of the non-selected nonvolatile memory element, the charge in the charge storage layer is not extracted to the drain region. Absent. That is, the drain disturb does not occur in the non-selected nonvolatile memory element.

On the other hand, when a predetermined voltage is applied to the source region of the non-volatile memory element by the peripheral circuit, in the selected non-volatile memory element, the charges accumulated in the charge accumulation layer flow out to the source region. To be removed. At this time, since the source region of the non-volatile memory element has an impurity diffusion concentration suitable for the outflow of charges, the charges accumulated in the charge storage layer do not excessively flow to the source region and are excessive. Erasure can be prevented.

According to another aspect of the semiconductor integrated circuit device of the present invention,
The source region of the nonvolatile memory element is an external diffusion layer having an impurity diffusion concentration lower than that of the source diffusion layer, and has a high breakdown voltage structure surrounding the source diffusion layer. Can withstand high voltage. On the other hand, since the drain region of the non-volatile memory element has a diffusion pocket having a conductivity type different from that of the drain diffusion layer, which is joined to the end portion of the drain diffusion layer on the side of the source region, the difference in concentration between the drain diffusion layer and the diffusion pocket is caused. , The charge generation efficiency near the drain region is increased, and a sufficiently high charge injection rate can be obtained.

In the manufacturing method of the third aspect, since the source region and the drain region of the non-volatile memory element are formed separately, the source region and the drain region are suitable for injecting and outflowing charges. It is possible to set different impurity diffusion concentrations. Further, in forming the source region of the non-volatile memory element, ion implantation is performed twice by masking once to form the source region surrounding the source diffusion layer with the external diffusion layer. The number can be reduced. Even in the formation of the drain region of the non-volatile memory element, similarly, ion implantation is performed twice by masking once, and the drain having the diffusion pocket joined to the end of the drain diffusion layer on the source region side is formed. Since the region can be formed, the number of steps can be reduced.

[0021]

An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a block diagram showing an electrical configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. The electrical configuration of the semiconductor integrated circuit device according to this embodiment will be described with reference to FIG. Note that in FIG. 2, an overline attached to a symbol representing a signal or the like indicates that it is a negative logic, and the description of the overline is omitted in the specification.

The semiconductor integrated circuit device of this embodiment is a flash EEPROM, and is provided in the periphery of the memory array MA10 and a memory array MA10 having a plurality of memory transistors for storing data as shown in FIG. , Chip enable (CE), output enable (O
E), write enable (WE) buffer 20a, address buffer 20b, I / O buffer 20c, word line decoder 20d, Y gate decoder 20e, Y gate
Sense amplifier 20f, data load timing control circuit 20g, erase / write timing control circuit 20h, data pooling circuit 201, page data load latch circuit 20m, data line decoder 20n, timer (I) 20o, timer (II ) 20p, READY / B
It includes a USY buffer 20q and a power supply voltage detection circuit 20s.

In this semiconductor integrated circuit device, the CE
By latching all the signals, the OE signal, and the WE signal inside the EEPROM, the internal timer 20o,
With 20p, old data is automatically rewritten with new data. Then, when writing data, the data line decoder 20n is driven, when erasing data, the word line decoder 20d is driven, and when reading data, the Y gate decoder 20e and the Y gate sense amplifier 20f are driven.

The timers 20o and 20p calculate the data rewriting time inside the EEPROM, and automatically set the data loading time and the data writing and erasing times, respectively. Data pooling circuit 20l and R
The EADY / BUSY buffer 20q is provided for displaying the end of data rewriting. READY / B
The USY buffer 20q has a hardware function of indicating that the chip is in the data rewriting cycle, and displays the chip state by low level during data rewriting and by high impedance after rewriting.
The data pooling circuit 20l has a software-like function that does not use an output pin for display or an external circuit in particular, and can output data even if data is read during a data rewriting cycle. In this state, when the data at the last written address is read out, if the data does not match the actual data, it is determined during the write cycle, and if they match, the cycle completion is determined.

In the following description, CE, OE,
WE buffer 20a, address buffer 20b, I / O
Buffer 20c, word line decoder 20d, Y gate
Coder 20e, Y gate desense amplifier 20f, data load timing control circuit 20g, erase / write timing control circuit 20h, data pooling circuit 20l, page data load latch circuit 20m, data line decoder 2
0n, timer (I) 20o, timer (II) 20p, RE
The ADY / BUSY buffer 20q and the power supply voltage detection circuit 20s are collectively referred to as "peripheral circuit 20".

FIG. 1 is a schematic sectional view schematically showing the structure of a semiconductor integrated circuit device. The structure of the semiconductor integrated circuit device will be described with reference to FIG. In the semiconductor integrated circuit device, as shown in FIG. 1, on a single P-type silicon substrate 30, a flash memory transistor MTr40 that constitutes the memory array MA10, an N-channel MOS transistor Tr50 that constitutes the peripheral circuit 20, and A P-channel MOS type transistor Tr60 is built in. That is, the memory transistor MTr40, the N-channel MOS type transistor Tr50, and the P-channel MOS type transistor Tr60 are formed on the silicon substrate 3
The elements are separated by the field oxide film 31 formed on the surface of 0.

The P-type silicon substrate 30 has a specific resistance of 5 to 2
A relatively low impurity concentration of about 0 Ωcm is used. The field oxide film 31 is made of, for example, an insulating material such as SiO ₂ and is provided with a thickness of about 7,000 Å for element isolation. And the field oxide film 3
Immediately below 1 is the memory transistor MTr40 and N
Channel MOS transistor Tr50, P channel M
In order to prevent the formation of a parasitic channel under the field oxide film 31 by controlling the threshold value of the OS type transistor Tr60, a P ⁺ type impurity diffusion layer (hereinafter, referred to as “channel stopper”) having a high channel stop ion concentration is formed. 32) is formed.

The memory transistor MTr40 has a source region 41 and a drain region 42, which are formed in the surface layer portion of the silicon substrate 30 at predetermined intervals in the memory transistor forming region X separated by the field oxide film 31, and a source region. Provided on a channel region 43 formed so as to be sandwiched between 41 and the drain region 42,
A tunnel oxide film 44 capable of tunneling charges generated in the channel region 43, a floating gate 45 provided on the tunnel oxide film 44 and accumulating charges tunneled through the tunnel oxide film 44, and a floating gate 4
An ONO film 46 which is provided on the gate electrode 5 and keeps the charge accumulated in the floating gate 45 for a long time;
The control gate 47 is provided on the NO film 46 and is applied with a predetermined voltage when writing, erasing and reading data.

The source region 41 is the N ⁺ -type impurity diffusion layer 4
1a and an N ⁻ -type impurity diffusion layer 41b that is deeply formed so as to surround the N ⁺ -type impurity diffusion layer 41a and has an impurity diffusion concentration set lower than that of the N ⁺ -type impurity diffusion layer 41a.
If, shallower in N ⁺ -type impurity diffusion layer 41a, and the impurity diffusion concentration is composed of the N ⁺ -type impurity diffusion layer 41c that is set to be higher than N ⁺ -type impurity diffusion layer 41a. That is, the source region 41 has a triple diffusion structure, and as a whole, an FN tunnel current is generated between the source region 41 and the floating gate 45, and the charge accumulated in the floating gate 45 is transmitted to the source region 41. It has an impurity diffusion concentration suitable for flowing out and removing charges from the floating gate 45.

The drain region 42 includes the N ⁺ type impurity diffusion layer 42a and the source region 41 of the N ⁺ type impurity diffusion layer 34a.
It is composed of a P ⁻ type pocket 42b joined at the side end. Therefore, the drain region 42 as a whole has an impurity diffusion concentration suitable for generating charges having high energy at the boundary between the channel region 43 and the drain region 42 and for injecting the charges into the floating gate 45. is doing.

That is, the source region 41 is set to an impurity diffusion concentration suitable for the outflow of charges, and the drain region 42 is set to an impurity diffusion concentration suitable for the injection of charges and different from the source region 41. . Tunnel oxide film 4
Reference numeral 4 is made of an insulating material such as SiO ₂ and is connected to the field oxide film 31 in a state where the source region 41 and the drain region 42 are bridged. The film thickness of the tunnel oxide film 44 is set to be extremely thin, about 100 Å, in order to tunnel the charges generated in the channel region 34.

The floating gate 45 is made of a conductive material such as polysilicon whose resistance is reduced by doping phosphorus at a high concentration. The ONO film 46 is formed of, for example, Si ₃ N ₄
It has a structure in which a nitride film such as SiO _{2 is} sandwiched from above and below with an oxide film such as SiO ₂ . The bottom oxide film has a thickness of about 100Å, the nitride film has a thickness of about 150Å, and the top oxide film has a thickness of about 50Å.

The control gate 47 is made of a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce its resistance. On the source region 41 side and the drain region 42 side of the floating gate 45, the ONO film 46, and the control gate 47, a pair of side spacers 48, 49 made of an insulating material such as SiO ₂ is deposited.

N-channel MOS type transistor Tr50
In the N-channel MOS transistor formation region Y separated by the field oxide film 31 is formed on the surface layer portion of the P-type silicon substrate 30 at a predetermined interval.
Type source region 51 and N type drain region 52, and gate oxide film 54 provided on channel region 53 formed so as to be sandwiched between source region 51 and drain region 52.
And a gate 55 provided on the gate oxide film 54.

The source region 51 is the N ⁺ type impurity diffusion layer 5
1a and, N ⁺ -type impurity diffused layers 51a to surround so deeply formed, and N impurity diffusion concentration is set to be thinner than the N ⁺ -type impurity diffusion layer 51a ^- -type impurity diffusion layer 51b
It consists of and. Drain region 52, and the N ⁺ -type impurity diffusion layer 52a, N ⁺ -type impurity diffusion layer 52a is deeply formed so as to surround the, and N impurity diffusion concentration is set to be thinner than the N ⁺ -type impurity diffusion layer 52a ^- -type A so-called LDD (light doped) layer including the impurity diffusion layer 52b.
drain) structure.

The gate oxide film 54 is made of an insulating material such as SiO ₂ , and is connected to the field oxide film 31 in a state where the source region 51 and the drain region 52 are bridged. The film thickness of the gate oxide film 54 is provided as thin as about 300 Å. The gate 55 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce resistance, and the source region 51 side and the drain region 52 side of the gate 55 are made of an insulating material such as SiO _2. A pair of side spacers 56 and 57 are attached.

P-channel MOS transistor Tr60
Is formed in the P-channel MOS transistor formation region Z separated by the field oxide film 31 with an N well 61 formed in the surface layer portion of the P-type silicon substrate 30 and a predetermined gap in the N well 61. P
^{A +} type source region 62 and a P ⁺ type drain region 63,
The gate oxide film 65 is provided on the channel region 64 formed so as to be sandwiched between the source region 62 and the drain region 63, and the gate 66 is provided on the gate oxide film 65.

Source region 62 and drain region 63
Has a single diffusion structure. The gate oxide film 65 is
The source region 62 is made of an insulating material such as SiO _2.
The drain region 63 and the drain region 63 are connected to the field oxide film 31. The thickness of the gate oxide film 65 is
It is thinly installed at about 300Å. Gate 66
For example, it is made of a conductive material such as polysilicon that is doped with phosphorus at a high concentration to reduce resistance, and SiO ₂ is formed on the source region 62 side and the drain region 63 side of the gate 66.
Pair of side spacers 67, 68 made of insulating material such as
Is being worn.

Furthermore, the entire surface of the silicon substrate 30 is PSG (phospho-silicate glass) which is P-doped SiO _2.
BPSG (boron-phospho-silicate gl) with B mixed in
It is covered with an interlayer insulating film 33 made of an insulating material such as ass). Then, the interlayer insulating film 33 and the tunnel oxide film 4
In 5, the portion corresponding to the N ⁺ -type impurity diffusion layer 42a of the drain region 42 of the memory transistor MTr40, drain contact hole 34a is formed, the drain electrode wiring 35a through the drain contact hole 34a is N ⁺ -type impurity It is formed so as to contact the diffusion layer 42a. Further, in the interlayer insulating film 33 and the gate oxide film 54, a source contact hole 34b is formed in a portion of the source region 51 of the N-channel MOS transistor Tr50 corresponding to the N ⁺ type impurity diffusion layer 51a. Contact hole 3
The source electrode wiring 35b is formed so as to contact the N ⁺ -type impurity diffusion layer 51a through 4a. Similarly, a drain contact hole 34c is formed in a portion of the drain region 52 corresponding to the N ⁺ type impurity diffusion layer 52a, and the drain electrode wiring 35c contacts the N ⁺ type impurity diffusion layer 52a through the drain contact hole 34c. Is formed. Further, a source contact hole 34d is formed in a portion of the interlayer insulating film 33 and the gate oxide film 65 corresponding to the source region 62 of the P-channel MOS transistor Tr60.
The source electrode wiring 35d is formed so as to contact the source region 62 through the source contact hole 34d. Similarly, a drain contact hole 34e is formed in a portion corresponding to the drain region 63, and a drain electrode wiring 35e is formed so as to contact the drain region 63 through the drain contact hole 34e. Therefore, the electrode wirings 35a, 35b, 35c, 3
The layers 5d and 35e are insulated from each other by the interlayer insulating film 33. Although not shown, the source region 41 and the control gate 47 of the memory transistor MTr40, the gate 55 of the N-channel MOS type transistor Tr50, and the P-channel MOS type transistor Tr.
The gate 66 of 60 is also in contact with the electrode wiring.

Electrode wiring 35a, 35b, 35c, 35
d and 35e are made of a conductive material such as Al, and on the electrode wirings 35a, 35b, 35c, 35d and 35e, the memory transistor MTr40 and the N channel M are formed.
A passivation film 66 made of an insulating material such as silicon nitride (Si ₃ N ₄ ) for protecting the surfaces of the OS transistor Tr50 and the P-channel MOS transistor Tr60 and preventing the intrusion of contaminants from the outside is provided. , Are laminated on the entire surface.

FIG. 3 is an equivalent circuit diagram of the memory array.
The electrical configuration of the memory array MA10 will be described with reference to FIG. The memory array MA10 is shown in FIG.
As described above, it has a one-cell / one-transistor structure, and four memory cells including the memory cell MC71 surrounded by a dotted line are arranged. That is, the memory transistors MTr41, MTr42, MTr having the structure shown in FIG.
43 and MTr44 are arranged in a matrix in the row direction X and the column direction Y.

The control gates of the memory transistors MTr41, MTr42 arranged in the row direction X are connected to the word line WL1, and the control gates of the memory transistors MTr43, MTr44 arranged in the row direction X have the word line WL1 ,. WL2 is connected. The bit line BL1 is connected to the sources of the memory transistors MTr41 and MTr43 arranged in the column direction Y, and the bit line BL3 is connected to the sources of the memory transistors MTr42 and MTr44 arranged in the column direction Y. Further, the drains of the memory transistors MTr41 and MTr42 that are adjacent in the row direction X are connected in series, and are connected to the bit line BL2 at the connection intermediate point. Similarly, row direction X
Adjacent memory transistors MTr43, MTr44
Are connected in series, and the bit line BL2 is connected to the connection intermediate point. That is, the memory transistors MTr41, MTr that are adjacent in the row direction X
The drains of 42 and MTr43 and MTr44 share the bit line BL2.

In the following description, the memory transistors MTr41, MTr42, MTr43, MTr4.
4 are collectively referred to as "memory transistor MTr40".
Say. Here, mainly with reference to FIG. 3 and Table 2, data writing, erasing and reading operations in the memory array MA10 will be described. In Table 2, it is assumed that the memory cell MC71 shown in FIG. 3 is selected when writing data.

[0044]

[Table 2]

<Write (WRITE)> The data line decoder 20n of the peripheral circuit 20 shown in FIG. 2 is driven, 0 V is applied to the word line WL2, the bit line BL1 and the substrate SUB are grounded, and the data is written. 12V is applied to the word line WL1 and a write voltage 5V is applied to the bit line BL2 in order to select the memory cell MC1 in which the writing is performed.

Then, as shown in FIG. 4, a saturated channel current flows between the source region 41 and the drain region 42 of the memory transistor MTr41. Drain region 42
In the nearby pinch off region, electrons accelerated by a high electric field are ionized.
zation), hot electrons are generated, these hot electrons are injected into the floating gate 45, and a data “0” write state is set.

At this time, as shown in FIG. 5, the memory transistor MTr43 of the non-selected memory cell MC73 arranged in the column direction together with the selected memory cell MC71.
A write voltage of 5V is also applied to the drain region 42 of. However, the drain region 4 of the memory transistor MTr40
2 is set to an impurity diffusion concentration different from the impurity diffusion concentration of the source region 41 and suitable for the injection of charges,
Even if electrons are accumulated in the floating gate 45 of the memory transistor MTr43, the electrons in the floating gate 45 are not extracted to the drain region 42 and the write state of the non-selected memory cell MC73 does not change. That is, the occurrence of drain disturb can be prevented.

Further, since the drain region 42 has the P ^-- type pocket 42b joined to the end of the N ⁺ -type impurity diffusion layer 34a on the side of the source region 41, the N ⁺ -type impurity diffusion layer 34a and the P ^-- type pocket are formed. The difference in density with 42b is large. Therefore, the generation efficiency of hot electrons in the vicinity of the drain region 42 is increased, and a sufficiently high writing speed can be obtained.

The gate voltage required for conduction between the source and drain of the memory transistor changes depending on whether electrons are accumulated in the floating gate or not. That is, the threshold voltage V _TH for conducting between the source and the drain of the memory transistor has a high threshold value V1 (for example, 8 V) in the state where electrons are injected into the floating gate, and in the state where electrons have not been injected. Low threshold V
It takes 2 (for example, 2V). Thus, the threshold voltage V
_By setting _TH to two types, binary data of "0" or "1" can be stored in the memory transistor. <Erase> For data erasing, the word line decoder 20d of the peripheral circuit 20 is driven to perform batch erasing. That is, the word lines WL1 and WL2 and the bit line BL2 are opened, the substrate SUB is grounded, and the erase voltage 12V is applied to the bit lines BL1 and BL3, respectively.

Then, as shown in FIG. 6A, the floating gate 4 of the memory transistor MTr40 is formed.
5 and a source region 41 generate an FN tunnel current,
As a result, the electrons accumulated in the floating gate 45 flow out to the source region 41 and are removed, resulting in a data erased state, that is, a data “1” written state.

At this time, the memory transistor MTr40
Since the source region 41 has an impurity diffusion concentration suitable for the outflow of electrons, the electrons accumulated in the floating gate 45 excessively outflow into the source region 41 as shown in FIG. 6B. Without incident,
No holes are accumulated in the floating gate 45. That is, it is possible to prevent the overerasure.

[0052] The source region 41, N ^- because it has a high breakdown voltage structure surrounding the N ⁺ -type impurity diffusion layer 41a at -type impurity diffusion layer 41b, can withstand the high voltage at the time of erasing the data . <Read (READ)> For data reading, the Y gate decoder 20e and the Y gate sense amplifier 20f of the peripheral circuit 20 are driven to perform line batch reading for each word line. That is, the word line WL
2 is applied with 0 V, the bit lines BL1 and BL3 and the substrate SUB are grounded, and the word line W
A sense voltage of 5V is applied to L1 and a voltage of 2V is applied to the bit line BL2.

Then, as shown in FIG. 7A, if electrons are accumulated in the floating gates 45 of the memory transistors MTr41 and MTr42, the positive charge of the control gate 47 is the electrons injected into the floating gate 45. It is canceled and the influence of this positive charge does not reach the surface of the silicon substrate 30. Therefore, the memory transistor MTr4
1, no channel is formed in MTr 42, and no current flows from drain region 42 to source region 41. On the other hand, FIG.
As shown in (b), the memory transistors MTr41,
If electrons are not accumulated in the floating gate 45 of the MTr 42, the influence of the positive charge of the control gate 47 extends to the surface of the silicon substrate 30, a channel is formed in the memory transistors MTr 41 and MTr 42, and the drain region 42 changes to the source region 41. An electric current flows. If this state is sensed by the Y gate decoder 20e and the Y gate sense amplifier 20f, the data stored in the memory transistors MTr41, MTr42 can be read.

Here, the sense voltage is an intermediate voltage between two types of V1 and V2 of the above threshold voltage V _TH .
Therefore, when this sense voltage is applied, it depends on whether or not electrons are accumulated in the floating gate.
Conduction / non-conduction of the memory transistor is determined. By the way, the source region 41 of the memory transistor MTr40
As shown in FIG. 1, N ⁺ -type impurity diffusion concentration diffusion layer 41a forms a dense set N ⁺ -type impurity diffusion layer 41c than N ⁺ -type impurity diffusion layer 41a, N from the outside ^- Type impurity diffusion layer 41b, N ⁺ type impurity diffusion layer 41
a, as a triple diffusion structure of the N ⁺ -type impurity diffusion layer 41c,
Since the diffusion resistance is kept low, with the miniaturization of elements,
Even if the junction depth of the source region 41 becomes shallow, it is possible to suppress the drop of the electric field on the source line.

Further, the N-channel MOS of the peripheral circuit 20
Since the type transistor Tr50 has the LDD structure, even if the channel length of the transistor Tr50 becomes shorter due to miniaturization, the adverse effect due to the short channel effect can be prevented. 8 to 21 are schematic cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device in the order of steps. A method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. The memory transistor MTr40 shown in FIG. 1, the N-channel MOS type transistor Tr50 and the P-channel MOS transistor of the peripheral circuit 20 are shown.
The P-type silicon substrate 30 is formed in parallel with the type transistor Tr60.

First, an N well is formed. That is, the figure
As shown in FIG. 8 (a), a P-type silicon group is formed by thermal oxidation.
On the entire surface of the plate 30, silicon oxide (SiO 2₂) Grow film 80
Then, the P-channel MOS is formed by the lithography technique.
Type resist forming area Z
Form turn 81. Using the resist 81 as a mask,
SiO in this part₂The film 80 is removed by etching,
B which is an N-type impurity ⁺Etc. Resist putter
Ion-implanted B after removing⁺Heat dissipated etc.
Then, as shown in FIG. 8B, the N well 61 is formed.
To be done.

When the N well forming step is completed, element isolation is performed. That is, as shown in FIG. 8B, since the SiO ₂ film 80 grown to form the N well 61 has been used, the P-type silicon substrate 30 is removed to about 900 to 1000 after removal. Thermal oxidation is performed at a temperature of ℃ to form a pad oxide film 82 of about 1000 Å on the silicon substrate 30. Subsequently, a silicon nitride (Si ₃ N ₃ ) film is formed on the pad oxide film 82 by a CVD (chemical vapor deposition) method.
₄ ) Laminate the film 83 about 1000Å. And Si ₃ N
The memory transistor forming region X of the _four films 83, the N channel MOS type transistor forming region Y, and the P channel MO
A resist pattern 84 is formed on the S-type transistor formation region Z.
To form. The resist pattern 84 becomes a pattern that defines the region where each transistor will be formed.

After that, as shown in FIG.
Using the pattern 84 as a mask₃N_FourOne of the membranes 83
Etch the department. For this etching, for example
CF _Four/ O₂Of plasma etching is preferred
Yes. Next, using the same resist pattern 84 as a mask,
For example B⁺Channel stop ions such as 10¹³cm
^-2Inject about. At this point, the cash register used as the mask
Since the strike pattern 84 is already used, O₂Plasma treatment
As a result, the resist pattern 84 is ashed.
To do.

Then, as shown in FIG. 9B, the silicon substrate 30 is oxidized in a water vapor (H ₂ O) atmosphere at about 1000 ° C. for about 6 to 7 hours and is not covered with the Si ₃ N ₄ film 83. A field oxide film 31 of about 7,000 Å is grown on the surface of the silicon substrate 30 in a part. Then, the P-type channel stopper 32 is formed immediately below the field oxide film 31. Here, H ₂ O is used instead of dry oxygen because the oxidation rate is high and the oxidation time can be shortened.

When the element isolation process is completed, the memory device is
Transistor tunnel oxide and floating gate
Formation. That is, as shown in FIG.
Pad oxide film 82 and Si₃N_FourEtch film 83
And exposed to expose the surface of the silicon substrate 30. So
After that, N-channel MOS type transistor forming regions Y and P are formed.
Resist on the channel MOS transistor formation region Z
Pattern 85 is formed and resist pattern 85 is used as a mask
As an example, B with an injection energy of 40 keV⁺
Channel ion for memory transistor such as 1 × 10¹³
atoms / cm ²About the surface layer of the silicon substrate 30
To enter.

Next, as shown in FIG. 10B, after removing the resist pattern 85, the silicon substrate 30 is thermally oxidized to grow a silicon oxide (SiO ₂ ) film 86 of about 100 Å on the silicon substrate 30. . At this time, SiO
_{The second} film 86 is a bird's beak (birth) of the field oxide film 31.
d's beak). Then, as shown in FIG. 11A, polysilicon 87 is deposited on the entire surface by the CVD method, and P or the like is added to the polysilicon 87.

Thereafter, as shown in FIG. 11B, a resist pattern (not shown) is formed on the memory transistor forming region X of the polysilicon 87, and the polysilicon 87 and the SiO ₂ film are formed using the resist pattern as a mask. 8
6 is etched to form the floating gate 45 and the tunnel oxide film 44 of the memory transistor. Regarding the etching of the polysilicon 87 and the SiO ₂ film 86, it is important that the etching process is performed exactly according to the resist pattern.
n etching) is preferably used.

When the tunnel oxide film and floating gate forming process is completed, an ONO film 46 is formed on the floating gate 45, as shown in FIG. That is, a silicon oxide (SiO ₂ ) film is laminated on the entire surface by CVD to a thickness of about 250 Å,
The upper part of the _two films is thermally nitrided to about 150Å to form a silicon nitride (Si ₃ N ₄ ) film. Further, a silicon oxide (SiO ₂ ) film is thinly laminated on the Si ₃ N ₄ film to a thickness of about 50 Å by the CVD method. After that, the uppermost layer of SiO ₂
A resist pattern (not shown) is formed on the memory transistor formation region X of the film, and the SiO ₂ film, the Si ₃ N ₄ film, and the SiO ₂ film are sequentially stacked using the resist pattern as a mask.
₂ film is etched, and on the floating gate 45,
An ONO film 46 is formed by sandwiching a nitride film with a bottom oxide film and a top oxide film. Note that RIE is preferably used for etching the ONO film 46.

When the ONO film forming step is completed, the gate oxide films of the N-channel MOS type transistor and the P-channel MOS type transistor are formed. That is, as shown in FIG. 12B, the resist pattern used in the step of FIG.
0 is thermally oxidized at about 900 to 1000 ° C. to obtain N-channel MO.
About 30 on the silicon substrate 30 in the S-type transistor forming region Y and the P-channel MOS type transistor forming region Z.
Gate oxide films 54 and 65 of 0Å are grown respectively.
At this time, the gate oxide films 54 and 65 are connected to the bird's beak of the field oxide film 31.

Then, after removing the resist pattern formed in the step of FIG. 12A, as shown in FIG. 13A, the memory transistor forming region X and the P channel MOS are formed.
A resist pattern 88 is formed on the type transistor formation region Z, and using the resist pattern 88 as a mask, channel ions for N channel MOS type transistors such as B ⁺ are implanted into the surface layer portion of the silicon substrate 30.

Subsequently, as shown in FIG. 13B, after removing the resist pattern 88, a resist pattern 89 is formed on the memory transistor forming region X and the N-channel MOS type transistor forming region Y, and the resist pattern 89 is formed. As a mask, for example, P ⁺ channel MO such as B ⁺
Channel ion for S-type transistor, N-channel MO
It is implanted into the surface layer portion of the silicon substrate 30 at a concentration different from that of the channel ions of the S-type transistor. At this point, the resist pattern 89 is used and is removed.

When the gate oxide film forming step is completed,
Form the control gate of the memory transistor.
That is, as shown in FIG. 14A, the polysilicon 90 is deposited on the entire surface by the CVD method, and the polysilicon 9 is deposited.
For example, P or the like is added to 0. Thereafter, as shown in FIG. 14B, a resist pattern (not shown) is formed on predetermined portions of the N-channel MOS type transistor forming region Y, the N-channel MOS type transistor forming region Z and the memory transistor forming region X of the polysilicon 90. No.) is formed, and polysilicon 9 is used with the resist pattern as a mask.
The 0, the ONO film 46, and the floating gate 45 are etched to form the control gate 47 of the memory transistor. The polysilicon 90 and ONO
RIE is preferably used for the etching of the film 46 and the floating gate 45.

When the control gate forming step is completed, the source ions of the memory transistor are implanted.
That is, as shown in FIG.
A resist pattern 91 is formed on a predetermined portion of the S-type transistor formation region Y, the N-channel MOS type transistor formation region Z, and the memory transistor formation region X except the source region. And control gate 4
7. Using the ONO film 46 and the floating gate 45 as a mask, P ⁺ or the like is injected into the surface layer portion of the silicon substrate 30 at a dose of about 1 × 10 ¹⁴ atoms / cm ² with an implantation energy of 30 keV, and the N ⁻ type impurity is diffused in a self-aligned manner. The layer 41b is formed deep.

Subsequently, as shown in FIG. 15B, the resist pattern 91 used in the step of FIG. 15A is used as it is, and the control gate 47 and the ONO film 46 are used.
Also, using the floating gate 45 as a mask, for example, As.sup. ⁺ Is 3 × 1 with an implantation energy of 50 keV.
About 0 ¹⁵ atoms / cm ² is implanted into the surface layer portion of the silicon substrate 30, and the N ⁺ -type impurity diffusion layer 41a is formed shallow in the N ⁻ -type impurity diffusion layer 41b in a self-aligned manner.

As a result, the N ⁺ -type impurity diffusion layers 41a and N
^The- type impurity diffusion layer 41b means the N ⁺ type impurity diffusion layer 41.
The junction is performed so that a is surrounded by the N ⁻ type impurity diffusion layer 41b. Further, since the ion implantation for forming the N ⁺ -type impurity diffusion layer 41a and the N ⁻ -type impurity diffusion layer 41b is performed with high energy, the heat treatment for diffusing the impurity ions, that is, the high temperature annealing is not necessary, and the tunneling is performed. The oxide film 44 need not be adversely affected. Note that the resist pattern 91 is removed because it is used up.

When the source ion implantation step is completed,
Implant drain ions of the memory transistor. That is, as shown in FIG. 16A, a resist pattern 92 is formed on a predetermined portion of the N-channel MOS type transistor formation region Y, the P-channel MOS type transistor formation region Z and the memory transistor formation region X except for the drain region. To do. And the control gate 47,
By using the ONO film 46 and the floating gate 45 as a mask, 1 × 10 of B ⁺ or the like with an implantation energy of 60 keV is formed by oblique implantation.
^{About 13} atoms / cm ² is injected into the surface layer portion of the silicon substrate 30 to form the P ⁻ -type impurity diffusion layer 42b ′ in a self-aligned manner.

Next, as shown in FIG.
The resist pattern 92 used in the step 16 (a) is removed.
The control gate 47 and the ONO film 46 are used as they are.
And using the floating gate 45 as a mask
For example, with an injection energy of 50 keV⁺8 x 1 etc.
0¹⁴atoms / cm²Surface layer of silicon substrate 30
In a self-aligned manner,⁺Type impurity diffusion layer 42a
Form. At this time, P^-Type ions are injected at an angle
Therefore, N⁺Of the source impurity region 42a on the source region side
To P^-A mold pocket 42b is formed. That is, drain
Area 42 is N ⁺Type impurity diffusion layers 42a and P^-Type pocket
42b. The resist pattern 9
No. 2 is no longer needed and is removed.

When the drain ion implantation process is completed, the gates of the N-channel MOS type transistor and the P-channel MOS type transistor are formed. That is,
As shown in FIG. 17A, a resist pattern (not shown) is formed on predetermined portions of the memory transistor forming region X, the N channel MOS type transistor forming region Y, and the N channel MOS type transistor forming region Z, Using this resist pattern as a mask, the polysilicon 90 is removed by etching to form the gates 55 and 56. Regarding the etching of the polysilicon 90,
It is preferable to use RIE.

When the gate forming process is completed, LDD
Inject ions. That is, as shown in FIG.
To the memory transistor formation region X and the P channel M
A resist pattern 9 is formed on the OS type transistor formation region Z.
3 is formed, and using the gate 55 as a mask, for example, implantation
P with energy 40 keV⁺LDD ions such as 3
× 10¹³atoms / cm²Table of silicon substrate 30
It is injected into the layer portion and self-aligned to form an N-channel MOS transistor.
N in the source and drain regions of the transistor ^-impurities
Diffusion layers 51a and 52a are formed.

When the LDD ion implantation step is completed,
Source / drain ions of an N-channel MOS type transistor are implanted. That is, as shown in FIG. 18A, the silicon oxide (SiO ₂ ) film 94 is formed by the CVD method.
About 3000 Å is deposited on the entire surface. After that, FIG.
As shown in (b), by etching back the entire surface by RIE, a pair of side spacers 44 and 45 are provided on the source region side and the drain region side of the control gate 47, the ONO film 46, and the floating gate 45, and the source of the gate 55. A pair of side spacers 56 and 57 are provided on the region side and the drain region side, and a pair of side spacers 67 and 57 are provided on the source region side and the drain region side of the gate 66.
68 are formed respectively.

Then, as shown in FIG. 19A, a resist pattern 95 is formed on a predetermined portion of the P-channel MOS type transistor formation region and the memory transistor formation region X except the drain region, and the control gate 47 and ONO are formed. Using the film 46, the floating gate 45 and the side spacers 44 and 45, and the gate 55 and the side spacers 56 and 57 as masks, As ⁺ or the like is implanted into the silicon substrate 30 with an implantation energy of 50 keV, for example, at about 6 × 10 ¹⁵ atoms / cm 3. , In the N ⁺ impurity diffusion layer 41a in a self-aligned manner.
⁺ Impurity diffusion layer 41c is replaced with N ⁻ impurity diffusion layers 51b, 5
N ⁺ impurity diffusion layers 51a and 52a are formed in 2b, respectively. The resist pattern 95 is removed because it is used up.

That is, the drain region 52 of the N-channel MOS type transistor has the LDD structure. In addition, the side spacers 56 and 57 of the N-channel MOS type transistor
Along with the memory transistor, the side spacer 4
Since the regions 4 and 45 are formed, the source region 41 of the memory transistor has a triple diffusion structure. When the source / drain ion implantation process for the N-channel MOS transistor is completed, the source / drain ions for the P-channel MOS transistor are implanted. That is, FIG.
As shown in (b), a resist pattern 96 is formed on the memory transistor forming region X and the N-channel MOS type transistor forming region Y, and the gate 66 and the side spacers 67 and 68 are used as a mask with an implantation energy of 70 keV and BF ₂ Etc. 3 × 10 ¹⁵ atom
About s / cm is injected into the silicon substrate 30, and the P ⁺ impurity diffusion layers 62 and 63 are formed in a self-aligned manner. The resist pattern 95 is removed because it is used up.

When the source / drain ion implantation process for the P-channel MOS transistor is completed, an interlayer insulating film is formed. That is, as shown in FIG.
About 6000 Å of BPSG is deposited by the CVD method to form the interlayer insulating film 33. And reflow,
The surface of the interlayer insulating film 39 is flattened. Then about 9
Annealing is performed at 00 to 950 ° C.

When the step of forming the interlayer insulating film is completed, metallization is performed. That is, as shown in FIG. 20B, a resist (not shown) is applied to the entire surface for mask alignment, and a hole is formed in the resist only at the wiring outlet. Then, using the resist as a mask, the interlayer insulating film 33 and the underlying tunnel oxide film 44 and gate oxide films 54 and 65 are removed by etching by RIE, and the drain region 42 of the memory transistor and the source region 51 / of the N-channel MOS type transistor are formed. Drain region 52 and source region 62 / of P-channel MOS type transistor
Contact holes 34a, 34 are formed on the drain region 63.
b, 34c, 34d and 34e are opened respectively. Then, after stripping the resist, for example, Al or the like is deposited on the entire surface by, for example, sputtering or the like, and each electrode wiring 35a, 35b, 35c,
35d and 35e are patterned.

Finally, as shown in FIG. 21, a passivation film 46 is formed by depositing, for example, silicon nitride (Si ₃ N ₄ ) on the entire surface by the CVD method. As described above, since the source region and the drain region of the memory transistor are separately formed in different steps, the source region and the drain region of the memory transistor have different impurity diffusion concentrations suitable for electron injection and outflow. Can be set.

Further, the source region related to the memory transistor is
Area N⁺Type impurity diffusion layers 41a, N ^-Type impurity diffusion layer 4
In forming 1b, as shown in FIGS.
In addition, the ion implantation is performed twice with one masking.
Therefore, the number of steps can be reduced. Also memory
N of drain region related to transistor⁺Type impurity diffusion layer
42a, P^-Even in the formation of the mold pocket 42b, FIG.
Similarly, as shown in 6 (a) and (b), masking is performed once.
Since the ion implantation is performed twice at, the number of steps can be reduced.
You can

Further, in the step shown in FIG.
A side spacer 56 of a channel MOS transistor,
57 and side spacers 4 in the memory transistor
Since 8 and 49 are provided, by implanting LDD ions in the next step shown in FIG. 19A, the N-channel MOS transistor has an LDD structure and at the same time,
The source region 41 of the memory transistor can have a triple diffusion structure.

The present invention is not limited to the above embodiments, and it goes without saying that many changes and modifications can be made within the scope of the present invention. In the above example,
Although the case where the P-type silicon substrate is used is described,
The present invention may also be applied when using an N-type silicon substrate. Further, the present invention is also applied to a semiconductor integrated circuit device using a MNOS type or MONOS type memory transistor which eliminates a floating gate and accumulates charges in the top-up film 100 as shown in FIG. The effect of can be obtained.

[0084]

As is apparent from the above description, claim 1
In the semiconductor integrated circuit device described above, since the impurity diffusion concentrations of the source region and the drain region of the nonvolatile memory element are set to different concentrations suitable for injecting and outflowing charges, the occurrence of drain disturb and excessive erasure occurs. Can be prevented.

According to another aspect of the semiconductor integrated circuit device of the present invention,
Since the source region of the nonvolatile memory element can have a high withstand voltage structure, it can withstand a high voltage when removing charges from the charge storage film. On the other hand, in the drain region of the nonvolatile memory element, the concentration difference between the drain diffusion layer and the diffusion pocket is large, the charge generation efficiency in the vicinity of the drain region is increased, and a sufficiently high charge injection rate can be obtained. .

In the manufacturing method according to the third aspect, since the source region and the drain region of the non-volatile memory element are formed separately, the source region and the drain region are mutually suitable for injection and outflow of charges. Different impurity diffusion concentrations can be set. Further, in forming the source region and the drain region of the nonvolatile memory element, the number of steps can be reduced because the ion implantation is performed twice with one masking.

[Brief description of drawings]

FIG. 1 is a schematic sectional view schematically showing the structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a semiconductor integrated circuit device.

FIG. 3 is an equivalent circuit diagram of a memory array.

FIG. 4 is a diagram schematically showing a write operation of a memory transistor.

FIG. 5 is an equivalent circuit diagram of the memory array during writing.

FIG. 6 is a diagram schematically showing an erase operation of a memory transistor.

FIG. 7 is a diagram schematically showing a read operation of a memory transistor.

FIG. 8 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device in the order of steps.

FIG. 9 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, following FIG. 8 in order of steps.

FIG. 10 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 9, in step order.

11 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 10, in step order.

FIG. 12 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, following FIG. 11 in order of steps.

FIG. 13 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, which is subsequent to FIG. 12 in order of steps.

FIG. 14 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, following FIG. 13 in order of steps.

FIG. 15 is a schematic cross sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 14, in order of steps.

FIG. 16 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 15, in step order.

FIG. 17 is a schematic cross sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 16, in order of steps.

FIG. 18 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device following FIG. 17, in step order.

FIG. 19 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, which is subsequent to FIG.

FIG. 20 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, which is subsequent to FIG. 19 and is in the order of steps.

FIG. 21 is a schematic cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device, following FIG. 20 in order of steps.

FIG. 22 is a schematic cross-sectional view schematically showing the structure of a semiconductor integrated circuit device according to another embodiment.

FIG. 23 is a schematic cross-sectional view schematically showing the structure of a conventional memory array.

FIG. 24 is an equivalent circuit diagram of a memory array.

25A and 25B are diagrams schematically showing the operation of the memory transistor, in which FIG. 25A shows a write operation and FIG. 25B shows an erase operation.

FIG. 26 is an equivalent circuit diagram of a memory transistor at the time of writing, showing a state in which drain disturb occurs in the memory transistor.

FIG. 27 is a diagram schematically showing a state in which excessive erasing of a memory transistor occurs during erasing.

[Explanation of symbols]

MA10 memory array 20 peripheral circuit 30 P-type silicon substrate MTr40, MTr41, MTr42, MTr43, M
Tr44 memory transistor 41 source region 41a N ⁺ type impurity diffusion layer 41b N ⁻ type impurity diffusion layer 41c N ⁺ type impurity diffusion layer 42 drain region 42a N ⁺ type impurity diffusion layer 42b P ⁻ type pocket 43 channel region 44 tunnel oxide film 45 Rotating gate 46 ONO film 47 Control gate 48, 49 Side spacer Tr50 N-channel MOS type transistor 41 Source region 52 Drain region 52a N ⁺ type impurity diffusion layer 52b N ⁻ type impurity diffusion layer 53 Channel region 54 Gate oxide film 55 Gate 56 , 57 Side spacer Tr60 P-channel MOS transistor 61 N well 62 Source region 63 Drain region 64 Channel region 65 Gate oxide film 66 Gate 67,68 Side spacer 100 Trap film X memory transistor forming area Y N channel MOS type transistor forming area Z P channel MOS type transistor area MC71, MC73 memory cell WL1, WL2 word line BL1, BL2, BL3, BL4 bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 16/04

Claims (3)

[Claims] 1. A memory in which a plurality of nonvolatile memory elements for storing information are arranged in a matrix along a row direction and a column direction on a single semiconductor substrate based on a predetermined integrated circuit design. What is claimed is: 1. A semiconductor integrated circuit device, comprising: an array; and a peripheral circuit that is arranged around the memory array and that causes each nonvolatile memory element to perform a predetermined operation. The source region and the drain region are formed on the surface layer of the substrate with a predetermined space therebetween, and the channel region formed so as to be sandwiched between the source region and the drain region is provided, and charges generated in the channel region are accumulated. A charge storage layer and a gate provided on the charge storage layer and to which a predetermined control voltage is applied. The bit lines are connected to the source region and the drain region of each nonvolatile memory element that are connected to the column direction and are arranged in the column direction, and the peripheral circuit includes a gate and a drain region of each nonvolatile memory element. A means for injecting the charge into the charge storage layer by generating a charge having a high energy in the vicinity of the drain region of the channel region by applying a predetermined voltage to the source region of each nonvolatile memory element A means for applying a predetermined voltage to cause the charge stored in the charge storage layer to flow out to the source region and remove the charge, and the source region of each of the nonvolatile memory elements flows out of the charge. And the drain region is set to a different impurity diffusion concentration than the source region, which is suitable for injecting the charges. The semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the source region of each nonvolatile memory element has a second conductivity type opposite to the semiconductor substrate having a predetermined first conductivity type. And a second diffusion type outer diffusion layer that is deeply formed so as to surround the source diffusion layer and has an impurity diffusion concentration set lower than that of the source diffusion layer. A drain region of each nonvolatile memory element is joined to a drain diffusion layer having a second conductivity type opposite to the first conductivity type, and to a source region end of the drain diffusion layer, A semiconductor integrated circuit comprising: a diffusion pocket having a first conductivity type. 3. A method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein a nonvolatile memory element is formed on a nonvolatile memory element forming region of a semiconductor substrate having a predetermined first conductivity type. A step of sequentially forming the charge storage layer and the gate, applying a mask to the entire surface of the nonvolatile memory element except the source formation region, and forming a second conductive layer on the semiconductor substrate which is opposite to the first conductive type.
The first ion of the conductivity type is deeply implanted, followed by the first
Forming a source region having a double diffusion structure in which the source diffusion layer is surrounded by the outer diffusion layer in a self-aligned manner by shallowly implanting the second ion of the second conductivity type whose concentration is lower than that of the second diffusion layer. , And the entire surface of the nonvolatile memory element excluding the drain formation region is macerated, and ions of the first conductivity type are obliquely and shallowly implanted into the semiconductor substrate, and then ions of the second conductivity type are deeply implanted. And forming a drain region in which a diffusion pocket is joined to an end of the source region of the drain diffusion layer in a self-aligning manner.