JPH0619221Y2 - Analog digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A Field of Industrial Application The present invention relates to an analog digital conversion circuit, and is suitable for application to, for example, a time axis correction device of a video tape recorder (VTR).

B. Outline of the Invention The present invention is to obtain digital information with a small conversion error by clamping an input signal to an intermediate potential of a predetermined adjacent reference divided voltage in an analog digital conversion circuit.

C Prior Art Conventionally, in a VTR time axis correction device, the time axis is corrected by converting the video signal into digital information on the basis of the pedestal level of the video signal.

That is, as shown in FIG. 5, the video signal SVI is received by the clamp circuit 1, and the video signal SVI is clamped to the voltage set by the level adjusting variable resistor 2 at the timing of the clamp pulse CP, whereby the video signal SVI is clamped.
Clamp the pedestal level of the to a predetermined DC level.

As shown in FIG. 6, the analog digital conversion section 3 has
256 that operates in synchronization with the timing of the video signal SVC
Individual comparator circuits COM ₁ , COM _2, ... COM _K , COM
_{K + 1} ... Composed of a flash type analog digital conversion circuit in which COM ₂₅₅ and COM ₂₅₆ are connected in parallel, and the clamped video signal SVC is compared with each comparison circuit C.
OM ₁ , COM _2, ...... COM _K , COM _{K + 1} ...... CO
It is given to the inverting input terminals of M ₂₅₅ and COM ₂₅₆ , respectively.

Further, the analog digital conversion unit 3 uses the reference voltage V
A voltage _dividing resistor R ₁ in which a voltage dividing resistor having a resistance value R is connected in series between the reference power source 4 of _{ref and} the reference power source 4 and the ground,
R ₂ , R _3, ... R _K , R _{K + 1} , R _{K + 2} , ... R
₂₅₅ and R ₂₅₆ , the voltage dividing resistors R ₁ , R ₂ ,
R ₃ ... R _K , R _{K + 1} , R _{K + 2} , ... R reference voltages V _ref1 , V _ref2, ... V _refk , of the reference voltage V _ref obtained from the connection midpoints of R ₂₅₅ and R ₂₅₆ .
V _{refk + 1} ... V _{ref 255} and V _{ref 256}
Comparing circuits COM ₁ , COM _2, ... COM _k , COM
_When the DC level of the video signal SVC is changed so as to monotonically increase from the minimum value to the maximum value by being supplied to the non-inverting input terminals of the _{k + 1} ... COM ₂₅₅ , COM ₂₅₆ , for example. , Sequential comparison circuit C
OM ₁ , COM ₂ , ... COM _k , COM _{k + 1} , ..
The COM ₂₅₅ and the COM ₂₅₆ are turned on. That is, in these comparison circuits, COM ₁ performs the minimum level comparison, and as the DC level of the video signal increases, the comparison of the levels is performed by COM ₂ , COM ₃ ,
.. are arranged so that COM _k and COM _{k + 1} are sequentially performed and maximum level comparison is performed by COM ₂₅₆ .

Therefore, 256-bit digital information D whose logic level sequentially rises to logic "H" in accordance with the DC level of the video signal SVC via each of the comparison circuits COM _{1 to} COM _256.
S ₁ , DS ₂ ...... DS _k , DS _{k + 1} ...... DS ₂₅₅ ,
DS ₂₅₆ can be obtained.

The encoder circuit 7 uses the digital information DS ₁ , DS _2, ...
... DS _k , DS _{k + 1} ... DS ₂₅₅ , DS ₂₅₆ are received, and converted into digital information DS composed of 8-bit binary data and output.

Thus, the 8-bit digital information DS of the video signal SVC can be obtained at the timing of the video signal SVC clamped through the analog digital conversion section 3.

The memory circuit 8 sequentially stores the digital information DS and outputs the digital information DS through the read circuit 9 at the timing of the blanking pulse BL, which is a reference signal, so that the VTR jitter or the like is generated. Then, the digital information of the video signal SVI whose time axis has changed is corrected on the time axis at the timing synchronized with the blanking pulse BL.

Further, the read circuit 9 receives the blanking data DBL, and replaces the blanking data DBL with digital information during the period of the blanking pulse BL, so that the digital of the video signal SVI based on the blanking data DBL is used as a reference. The information is output to the digital analog conversion circuit 10.

Thus, the video signal SVO whose time axis is corrected at the timing of the blanking pulse BL can be obtained via the digital-analog conversion circuit 10.

However, in such an analog digital conversion circuit, the fluctuation of the clamp voltage in the clamp circuit 1 cannot be avoided, and therefore, the accurate video signal SVI of the analog digital conversion unit 3 is generated. There was a problem that the digital information DS could not be obtained.

That is, the signal level of the entire clamped video signal SVC varies with the variation of the clamp voltage. As a result, the digital information DS obtained via the encoder circuit 7
Error occurs in the input video signal SVI
On the other hand, there is a problem that the signal level of the video signal SVO output from the digital-analog conversion circuit 10 changes and an accurate video signal SVO cannot be obtained.

As one method for solving this problem, as shown in FIG. 7, a connection midpoint between the video signal SVC clamped at the timing of the clamp pulse CP and the voltage dividing resistors R _{k + 1} and R _{k + 2} using the error amplification circuit 11 is connected. Reference divided voltage V
The error voltage VE with _{respect to refk + 1} is detected, and the video signal SVI is clamped based on this error voltage VE, so that the DC level of the pedestal level is always used as the reference _divided voltage V _{refk + 1} of the comparison circuit COM _{k + 1} used for analog digital conversion. A method of clamping can be considered.

However, when the pedestal level of the video signal SVI is clamped to the reference _divided voltage V _{refk + 1} of the comparison circuit COM _{k + 1} in this way, the pedestal level of the digital information DS of the analog digital conversion output changes due to fluctuations in the clamp level or the like. It varies for one bit of the comparison output DS _{k + 1} of COM _{k + 1} (comparison output D
Digital information DS due to S _{k + 1} coming and going
The pedestal level of fluctuates by 1 bit of the minimum bit).

As a result, in the video signal SVO obtained through the digital-analog conversion circuit 10, the video signal whose signal level as a whole fluctuates according to the fluctuation of the digital information DS of the pedestal level is changed by a voltage corresponding to one bit. There is a problem that the SVO is obtained and the video signal SVO having the correct signal level cannot be reproduced.

On the other hand, pedestal level digital information DS
Although a method of compensating for the fluctuation of the digital information DS by comparing the data with the clamp voltage data is also possible, but there is a problem that the configuration of the entire analog digital conversion circuit becomes complicated.

The present invention has been made in consideration of the above points, and an object thereof is to propose an analog digital conversion circuit having a simple structure with a small conversion error with respect to an input video signal.

E Problems to be Solved by the Invention In order to solve the above problems, in the present invention, the input signal SVI is input to the reference _divided voltage V _ref1 ,
V _ref2 , ... V _refk , V _{refk + 1} , ... V
_A plurality of comparison circuits COM ₁ , COM _2, ... COM _k , COM _{k + 1,} ... C having different _ref255 and V _ref256.
OM ₂₅₅ and COM ₂₅₆ receive the comparison circuit COM ₁ ,
COM ₂ ...... COM _k , COM _{k + 1} ...... CO
M _255, compared to the output _DS 1 of _{COM 256,} DS ₂ ......
In the analog digital conversion circuit 15 adapted to convert the input signal SVI into the digital information DS based on DS _k , DS _{k + 1} ... DS ₂₅₅ , DS ₂₅₆ , adjacent predetermined reference voltages V _refk , V
Clamp circuits 1, 11, 16 for clamping the input signal SVI at the intermediate potential V _cp of _{refk + 1} are provided, and the input signal SVC obtained via the clamp circuits 1, 11, 16 is provided.
A plurality of comparison circuits COM ₁ , COM _2, ... COM _k , C
OM _{k + 1} ... Input to COM ₂₅₅ and COM ₂₅₆ .

The F action input signal SVI is applied to the intermediate potential V of the reference _divided voltages V _refk and V _{refk + 1} of the comparison circuits COM _k and COM _{k + 1.}
By clamping at _cp , if the level fluctuation of the clamped portion is within the value of the difference between the adjacent reference divided voltages, the output of the comparison circuit COM _{k + 1} does not change, and the pedestal level of the digital information DS is Fixed.

Thus, it is possible to obtain the analog digital conversion circuit 15 having a simple structure with a small conversion error.

G Embodiment One embodiment of the present invention will be described in detail with reference to the drawings.

(G1) First Embodiment In FIG. 1 in which parts corresponding to those in FIG. 6 are designated by the same reference numerals, 15 indicates an analog digital conversion circuit as a whole, and a reference divided voltage V of a comparison circuit COM _{k + 1.
The} level shift circuit 16 receives _{refk + 1} .

The level shift circuit 16 uses the reference voltage V of the reference power source 4.
_The following formula for _ref As shown by, the voltage of the reference _divided voltage V _{refk + 1} is set to V _ref / 512 [V] (that is, the comparison circuit COM _k
And COM _{k + 1} reference _divided voltages V _refk and V
The intermediate voltage V _cp of the reference _divided voltage V _refk and V _{refk + 1} obtained by shifting the voltage by half the potential difference of _{refk + 1} ) is input to the error amplification circuit 11.

As a result, the error amplification circuit 11 obtains an error voltage VE between the pedestal level DC voltage of the video signal SVC and the output voltage _Vcp of the level shift circuit 16, and the video signal SVC is clamped based on the error voltage VE. It Thus, the pedestal level of the video signal SVC is clamped to the intermediate voltage V _cp of the reference _divided voltages V _refk and V _{refk + 1} of the comparison circuits COM _k and COM _{k + 1} . Therefore, for example, even if the clamp level fluctuates, the fluctuation does not _{affect the} reference _divided voltages V _refk and V
If it is within the difference from _{refk + 1} , the comparison circuit COM _{k + 1}
Does not change, and the pedestal level of the digital information DS is fixed.

In the case of this embodiment, the pedestal level clamp voltage is set to the reference divided voltage V of the comparison circuit COM _{k + 1.}
Comparing circuits COM _k and COM for _{refk + 1
The} digital information DS is obtained by shifting to the reference _divided voltage V _{refk of k + 1} and the intermediate voltage V _cp of V _{refk + 1.}
Thus, the video signal obtained as a whole is in an offset state.

Therefore, for example, in the time axis correction device as shown in FIG. 5, the blanking data DBL to be replaced in the read circuit 9 is shifted by that amount to correct the offset and then output via the digital analog conversion circuit 10. By doing so, it is possible to obtain the video signal SVO having a correct signal level without offset as a whole.

According to the configuration of FIG. 1, since the conversion error can be reduced within 1 bit, it is possible to obtain an analog digital conversion circuit having a simple configuration with less conversion error than the conventional one.

Furthermore, the analog digital conversion circuit according to the embodiment of FIG. 1 is applied to a VTR for a high-definition television that is adapted to record the brightness signal by expanding the brightness signal on the time axis and dividing the brightness signal into two channels. If the pedestal level of the luminance signal is clamped, the variation of the digital information of the pedestal level between the channels can be made small, which is practically convenient.

(G2) Second Embodiment In FIG. 2, reference numeral 17 indicates the second embodiment of the analog digital conversion circuit according to the present invention as a whole, which is a reference _divided voltage V _refk and V _{refk + 1 of the} comparison circuits COM _k and COM _{k + 1. Is} received by the buffer circuits 20 and 21 via the resistors 18 and 19, and the reference _divided voltage V _refk
And a voltage V _cp at an intermediate potential between V _{refk + 1} and the resistor 22.
And 23, the voltage is added to obtain.

According to the configuration of FIG. 2, as in the case of FIG. 1, even if the clamp level fluctuates, the fluctuation is caused by the reference divided voltage V.
If it is within the difference between _refk and V _{refk + 1} , the output of the comparison circuit COM _{k + 1} does not fluctuate and the pedestal level of the digital information DS is fixed, so that the conversion error is small as in the case of the configuration of FIG. An analog digital conversion circuit can be obtained.

Further, in the configuration of FIG. 2, the intermediate voltage V _cp is applied to the resistors 18, 19, 22 and 23 and the buffer circuits 20 and 21.
The analog digital conversion circuit as a whole can have a simple structure because it can be obtained only by the resistor 1.
If 8, 19, 22, and 23 are selected to have the same resistance value R as that of the voltage dividing resistors R _{1 to} R ₂₅₆ , they can be integrated as a whole to obtain an analog digital conversion circuit with high conversion accuracy.

(G3) Third Embodiment In FIG. 3, reference numeral 20 indicates the third embodiment of the analog digital conversion circuit according to the present invention as a whole, in place of the voltage dividing resistance R _{k + 1} between the comparison circuits COM _k and COM _{k + 1.} , Two series resistors R having a resistance value R / 2 with a resistance value of 1/2
_{k + 1 (1)} and R _{k + 1 (2)} are provided, and the resistance R
The voltage V _cp of the intermediate potential of the reference _divided voltages V _refk and V _{refk + 1} is obtained from the connection midpoint of _{k + 1 (1)} and R _{k + 1 (2)} .

According to the configuration of FIG. 3, the reference _divided voltages V _refk and V _{refk + 1} of the comparison circuits COM _k and COM _{k + 1} have a simpler configuration than the configurations of FIGS.
_The video signal SVI can be clamped to _cp ,
Thus, it is possible to obtain an analog digital conversion circuit having a simple structure with less conversion error than the conventional one.

(G4) Fourth Embodiment In FIG. 4, reference numeral 30 indicates a fourth embodiment of the analog digital conversion circuit according to the present invention as a whole, which is a reference divided voltage V of the comparison circuit COM ₂ and the comparison circuit COM _255.
ref2 and V _ref255 are received by the buffer circuits 33 and 34 through the resistors 31 and 32, and the resistors 35 and 36 are received.
_Are used to add the voltages to obtain the reference _divided voltages V _refk and V of the comparison circuits COM _k and COM _{k + 1.}
The voltage V _cp of the intermediate potential of _{refk + 1} is obtained.

According to the configuration of FIG. 4, the video signal SVC is _divided into the reference _divided voltages V _refk and V _refk as in the configuration of FIG.
Since it can be clamped to the intermediate voltage V _cp of _{refk + 1} , the same effect as in the case of the configuration of FIG. 2 can be obtained.

Further, according to the configuration of FIG. 4, the input voltage of the error amplification circuit is freely set to the intermediate voltage V _cp of the desired reference divided voltage by selecting the voltage dividing ratio of the resistors 35 and 36 to a predetermined value. be able to.

Therefore, the analog digital conversion circuit can be integrated with a structure in which the resistors 35 and 36 are external components, and digital information with high versatility that can obtain digital information with a small conversion error based on a desired signal level. A conversion circuit can be obtained.

(G5) Other Embodiments In the above embodiments, the case where the digital information composed of 8-bit binary data is obtained by using the output of 256 comparison circuits has been described, but the present invention is not limited to this. For example, it is suitable for application to an analog digital conversion circuit of 4 bits, 16 bits or the like.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the analog digital conversion circuit of the video signal is described, but the present invention is not limited to this, and a predetermined signal level such as a chroma signal and a color difference signal is clamped to It can be widely applied to an analog digital conversion circuit adapted to convert into digital information on the basis of.

For example, when converting a chroma signal to digital information,
The voltage V _cp input to the error amplification circuit 11 is set to the reference voltage V
_By setting the vicinity of the intermediate potential of _ref as the reference divided voltage to the intermediate potential of two adjacent comparator circuits and clamping the potential of the chroma signal in the horizontal synchronizing period to the intermediate voltage V _cp , the chroma signal The conversion error when the signal level of 0 is zero level can be reduced within the range of 1 bit,
Thus, the chroma signal can be converted into digital information with a small conversion error.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the time axis correction device for the VTR has been described, but the present invention is not limited to this, and the video signal which is an analog signal is converted into digital information. It can be widely applied to analog digital conversion circuits.

H Effect of the Invention As described above, according to the present invention, an analog digital conversion circuit having a small conversion error and a simple structure can be obtained by clamping the input signal to the intermediate voltage of the adjacent reference divided voltage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an analog digital conversion circuit according to the present invention, FIG. 2 is a block diagram showing a second embodiment of an analog digital conversion circuit according to the present invention, and FIG. Is a block diagram showing a third embodiment of the analog digital conversion circuit according to the present invention, FIG. 4 is a block diagram showing a fourth embodiment of the analog digital conversion circuit according to the present invention, and FIG. 5 is a block diagram showing a time axis correction device. , FIG. 6 and FIG. 7 are block diagrams showing a conventional analog digital conversion circuit. 1 ... Clamp circuit, 3 ... Analog digital conversion unit, 15, 17, 20, 30 ... Analog digital conversion circuit, 7 ... Encoder circuit, 11 ... Error amplification circuit, COM ₁ , COM ₂ ... COM _k , COM _{k + 1} ...
... COM ₂₅₅ , COM ₂₅₆ ...... Comparison circuit, R ₁ , R
₂ , R ₃ ... R _k , R _{k + 1} , R _{k + 1 (1)} , R
_{k + 1 (2)} , R _{k + 2} ... R ₂₅₅ , R ₂₅₆ , 1
8, 19, 22, 23, 31, 32, 35, 36 ... Resistors, 20, 21, 33, 34 ... Buffer circuits.

Claims (1)

[Scope of utility model registration request] 1. An analog digital conversion circuit configured to receive an input signal into a plurality of comparison circuits having different reference divided voltages and to convert the input signal into digital information based on a comparison output of the comparison circuit. A clamp circuit is provided for clamping the input signal at an intermediate potential between adjacent predetermined reference divided voltages of the reference divided voltage, and an input signal obtained through the clamp circuit is input to the plurality of comparison circuits. An analog digital conversion circuit characterized in that