JPH0619315Y2 - Power MOS-FET switching power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a power MOS-FET switching power supply circuit, and particularly to a power MO that prevents destruction of the power MOS-FET and improves switching efficiency.
The present invention relates to an S-FET switching power supply circuit.

[Prior Art] An example of a conventional switching power supply circuit will be described with reference to FIGS. 2 to 3 of the accompanying drawings. In FIG. 2, (1) is a switching power supply circuit, which is of push-pull type. Further, (2) is a general commercial power source. Then, alternating current is converted to direct current by the rectifying diode (3) and the smoothing capacitors (4) and (4). Also, power line (5) (6)
Two switching elements (7) (8) such as transistor or power MOS-FET are connected in series between
(9) intermittently controls the switching elements (7) and (8) at a high frequency to stabilize the output. At this time, the switching elements (7) and (8) alternately repeat "on" and "off", the upper switching element (7) causes a current I ₁ to flow, and the lower switching element (8) causes a current I ₂ to flow. ing. Then, the high frequency transformer (10) is used for power conversion, and the diodes (11) and (11), the coil (12), and the capacitor (13) are used.
The output is stabilized by rectifying and smoothing.

Further, as shown in FIG. 3, in the operation of the switching elements (7) and (8), a dwell time t _{D at} which both of them are “off” is adjusted so that the driver circuit ( 9)
Is set to. This is to prevent the both becomes "on" at the same time the switching-element (7) (8), the power supply short-circuit current I _s shown in Figure 2 is generated. However, both of the switching elements (7) and (8) may be turned “on” at the same time due to a jump in power supply noise, a temperature characteristic of the switching power supply circuit (1), and the like. Various protection circuits have been devised as measures against this, but switching elements
(7) If (8) is a transistor, it is relatively durable against malfunction, so the switching power supply circuit (1) without a protection circuit with a sufficient dwell time t _D is also practical. Has been converted.

On the other hand, compared with a transistor, when using a power MOS-FET that operates thermally stable even at high voltage and large current as the switching elements (7) and (8) of the switching power supply circuit (1), 50 to 50 even at the switching-operation of about 100 KHz, it is necessary to set a longer pause time t _D. this is,
This is because the reverse recovery time of the switching characteristic of the power MOS-FET is relatively long, and further, the power MOS-FET
This is because unlike the transistor, when the power supply short-circuit current I _S flows over a certain value, the insulator of the gate electrode is instantly destroyed, so that this breakdown is prevented. However, if the pause time t _D is set to be long, the power supply efficiency will also decrease. Even if the dwell time t _D is set sufficiently, if the power supply short-circuit current I _S exceeding the limit value flows for some reason, the power M
The OS-FET is destroyed in an instant.

[Problems to be Solved by the Invention] When a power MOS-FET is used as a switching element in the above-mentioned conventional push-pull type switching power supply circuit, both power MOS-FETs are "off" to prevent destruction and malfunction. The rest period must be long enough. Therefore, the output efficiency is low,
Also, malfunction prevention was not sufficient. Therefore, power M
There is a technical problem to be solved in order to improve the efficiency of the OS-FET switching power supply circuit and eliminate the risk of malfunction and destruction of the power MOS-FET, and the present invention solves the problem. The purpose is to do.

[Means for Solving the Problem] The present invention has been proposed in order to achieve the above-mentioned object, and is a switching power supply circuit for performing inverter control by push-pull operating two power MOS-FETs. In a switching power supply circuit in which a coil is arranged between two power MOS-FETs connected in series between power supply lines and an output is taken out from an intermediate tap provided in the coil, the two MOS- Each FET is provided with a protection circuit, and the inductance between both terminals of the coil keeps the power supply short-circuit current below the breakdown level of the power MOS-FET until the protection circuit operates when the power supply line is short-circuited. A power MOS-FET switching power supply circuit having a limiting value is provided.

[Operation] In this invention, in a push-pull type switching power supply circuit using a power MOS-FET, a coil is arranged between two power MOS-FETs connected in series between power supply lines. That is, the drain of one power MOS-FET is connected to the + power supply line, and the power M
The source of the OS-FET is connected to one end of the coil. The other end of the coil is connected to the other power M.
Connected to the drain of OS-FET, this power MOS-
The source of the FET is connected to the-power supply line.

Then, the coil is provided with an intermediate tap, and the output is taken out from the intermediate tap. Therefore, the two power MO
When the S-FET performs the switching operation and the current flows to the output terminal, the inductance from the intermediate tap to the end of the coil acts, respectively. In addition, the two power MO
When the S-FETs malfunction and both are turned “on”, a power supply short-circuit current flows from the source of the power MOS-FET connected to the + power supply line side to the drain of the other power MOS-FET. In that case, the inductance between both ends of the coil acts, and the inductance value is four times the value from the intermediate tap to the end. This is because the inductance value is proportional to the square of the number of turns of the coil.

Therefore, when the power MOS-FET operates normally, the current consumption is small due to the low inductance, and when the power supply short-circuit current flows, it acts as a quadruple inductance to reduce the current. The inductance value of this coil is set to a value that limits the short-circuit current to the breakdown current level of the power MOS-FET or less until the protection circuit operates by detecting an overcurrent when the power supply is short-circuited.
Dielectric breakdown of the S-FET is prevented.

[Embodiment] An embodiment of the present invention will be described below in detail with reference to FIG. For convenience of description, technical matters that are conventionally known will be described at the same time. Further, the same reference numerals are used for the parts having the same configurations as those used in the conventional example. First
The figure shows an example in which power MOS-FETs (15) and (16) are applied to the output section of a fluorescent lamp inverter device (14) for simultaneously lighting a plurality of fluorescent lamps. A rectifying diode (3) is connected to the power source input lines (17) and (17) of the commercial power source, and DC135V is supplied to the power source lines (18) and (19). (4) is an electrolytic capacitor for current smoothing. Also, the power input line (1
A power transformer (20) is connected to 7) and 17)
-Driver circuit part that controls the operation of FET (15) (16)
Power is supplied to (9). And the power line (18) (1
A power MOS-FET (15) (16) is connected in series to 9) via a coil (22) having an intermediate tap (21) in the middle. The connection is the power MOS-FET (15) in the upper part of the figure.
Is connected to the power supply line (18), and the source (24) of the lower power MOS-FET (16) is connected to the power supply line (19). Then, the upper power MOS-FET (1
The source (25) of 5) and the drain (26) of the lower power MOS-FET (16) are connected via a coil (22), and an output is output from an intermediate tap (21) of the coil (22). I am taking it out. Although the gates (27) and (28) of the power MOS-FETs (15) and (16) are connected to the driver circuit section (9), respectively, the upper power MOS-FET (15) and the driver circuit section (9) are connected. ) And a pulse transformer (29) between both power MOS-
The FETs (15) and (16) are insulated. In this embodiment, the power MOS-FET controlled by the driver circuit section (9)
(15) The rest time t _D of (16) is set to 1 μs so that a very high speed switching operation is performed.

The inductance between the intermediate tap (21) of the coil (22) and both terminals (30) (31) is the operation of the protection circuit (34) (34) when the output terminals (32) (33) are short-circuited. The capacity should be such that the current can be limited only for the time required. In this embodiment, the current detection resistors (35) and (35) are set to 0.05Ω, the response speed of the protection circuits (34) and (34) is set to 1 μs or less, and the inductance of the coil (22) is set to the terminal (30). Between the intermediate tap (21) and the intermediate tap (21)
2.2 μH between the terminal and the terminal (31). Further, the diodes (36) and (36) act as a commutation diode, and the power MOS-
An ultrafast diode with a reverse recovery time of 100 ns is used to protect the FETs (15) and (16) from overvoltage. Capacitors (37) (37) connected in series with the diodes (36) (36)
Is for reducing the switching noise of the power MOS-FETs (15) and (16) and from the noise entering from the outside to the power MO.
It protects the S-FETs (15) and (16). The capacitor (38) and the resistor (39) are for absorbing noise, and the final stage capacitor (40) is for blocking direct current.

Here, the operation of the coil (22) will be described. The driver circuit portion Yotsute power MOS-FET (9) (15) (16) is actuated switching-when the flow is in the drawing currents I _R and I _F is suppressed current consumption as small as possible an output impedance Should. On the other hand, when the power supply short-circuit current I _S is generated for preventing destruction of the power MOS-FET (15) (16 ), and allowed large becomes impedance exists for power supply short-circuit current I _S. Therefore, when the current I _F flows, the coil (22) acts as an inductance between the intermediate tap (21) and the terminal (31), and when the current I _R flows, the terminal (3
It acts as an inductance between 0) and the intermediate tap (21). This inductance value is 2.2 μm as described above.
It is set to H. Then, when the power supply short-circuit current _IS is generated, the inductance between the terminal (30) and the terminal (31) acts. At this time, the inductance obtained by winding the conductor wire around the same magnetic core is proportional to the square of the number of turns. Therefore, the inductance value is 2.2 μH × 2 ² = 8.8 μH and the power supply short-circuit current I _S is reduced. The short circuit current is supplied to the power MOS until the protection circuits 34, 34 detect the overcurrent and operate.
-Limit to below the breakdown current level of the FET.

In addition, the power MOS-FET (15) (16) has a drain (23) (2
Capacitance C of parasitic capacitor fed back from 6) to gates (27) and (28)
_Although there is _{rss, the} effect of the parasitic capacitor capacitance C _rss is remarkably reduced by the current limiting action of the inductance described above to prevent malfunction. Then, the power supply short-circuit current I _S
Power MOS-FET (15) (16)
It is possible to prevent malfunction and destruction of and reduce heat generation. Further, it acts as a filter against switching noise and noise propagating to the output side, and exhibits a current limiting function when the output terminal is short-circuited.

Therefore, the present invention can be variously modified without departing from the spirit of the present invention, and it is obvious that the present invention covers the modified version.

[Effect of the Invention] Since the present invention relates to the configuration described in detail in the above one embodiment,
The short circuit current is supplied to the power MOS-FE until the protection circuit of the power MOS-FET detects overcurrent and operates when the power supply is short-circuited.
Power MOS-
Prevent malfunction and destruction of FET. Therefore, the down time at the time of switching can be shortened, the switching frequency can be increased, the power supply efficiency can be improved, and the heat generation can be reduced, so that the radiator can be made small and the device can be miniaturized. Then, the switching noise is reduced by the effect of suppressing the overcurrent, and various effects such as acting as a filter for the noise propagating to the output side are exhibited, and the power MOS-FE
This can contribute to the improvement of the performance and reliability of the T-switching power supply circuit.

[Brief description of drawings]

FIG. 1 is a power MOS-FET showing an embodiment of the present invention.
Circuit diagrams of the switching power supply circuit, FIGS. 2 and 3 show conventional examples, and FIG. 2 is a circuit diagram of the switching power supply circuit.
FIG. 3 is an explanatory diagram showing operation waveforms of the switching element. (1) …… Switching power supply circuit (9) …… Driver circuit section (14) …… Fluorescent lamp inverter device (15) (16) …… Power MOS-FET (18) (19) …… Power supply line, (21 ) …… Intermediate tap (22) …… Coil, (30) (31) …… Terminal (34) …… Protection circuit, (35) …… Resistance for current detection

Claims (1)

[Scope of utility model registration request] 1. A switching power supply circuit for performing inverter control by push-pulling two power MOS-FETs, wherein a coil is arranged between two power MOS-FETs connected in series between power supply lines. In a switching power supply circuit in which an output is taken out from an intermediate tap provided in the coil, the two power MOS-F
A protection circuit is provided in each ET, and the inductance between both terminals of the coil is such that the power supply short circuit current is supplied to the power MOS during the time until the protection circuit operates when the power supply line is short-circuited.
A power MOS-FET switching power supply circuit having a value that is limited to a level equal to or lower than the breakdown current level of the FET.