JPH06196631A - Input/output protecting circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] An input / output protection circuit used in a semiconductor integrated circuit device that can be connected to semiconductor integrated circuit devices or the like having different operating voltages without lowering the ESD (electrostatic discharge) withstand voltage. To get A PMOS type transistor 21 having a gate terminal and a drain terminal connected to an input pad 25, and a diode 26 having an anode terminal connected to a source terminal of the PMOS type transistor 21 are included. The cathode terminal of the diode 26 is connected to the power supply terminal.
The PMOS transistor 21 operates as a series circuit of two parasitic diodes whose anode terminals are opposed to each other.
When an electrostatic pulse is input from the input pad 25,
The parasitic diode of the PMOS transistor 21 breaks down and absorbs the electrostatic pulse, so that the internal circuit is protected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output protection circuit for semiconductor devices. That is, the present invention relates to an input / output protection circuit capable of eliminating electrostatic pulses that enter the semiconductor integrated circuit from the input pad or the output pad.

[0002]

2. Description of the Related Art As semiconductor integrated circuit devices have been miniaturized in recent years, there is a high possibility that an element will be destroyed by an electrostatic pulse entering from an input or output pad. Therefore, in recent semiconductor integrated circuit devices, a protection circuit for protecting an internal circuit is often provided along with each input or output pad.

FIG. 5 is a circuit diagram of an input / output protection circuit that protects an internal circuit from such an electrostatic pulse entering from the outside.
And shown in FIG.

FIG. 5 shows an electrostatic pulse (ESD: ElectroStatic Dessate) penetrating from the input pad 5.
charge, also called electrostatic discharge) is shown. This input protection circuit is provided between the input pad 5 and the input buffer 4, and PM
OS type transistor 1 and NMOS type transistor 2
And a protection resistor 3. The source terminal and the gate terminal of the PMOS transistor are connected to the power supply terminal, and the drain terminal is connected to the input pad 5. The source terminal and the gate terminal of the NMOS transistor 2 are both grounded, and the drain terminal is connected to the input pad 5. Further, one end of the protection resistor 3 is also connected to the input pad 5. The other end of the protection resistor 3 is connected to the input terminal of the input buffer 4.

With such a structure, the excessive current that enters from the input pad 5 is limited by the protective resistor 3.
The electrostatic pulse applied between the power supply terminal and the input pad 5 is absorbed by the breakdown of the PMOS transistor 1, and the electrostatic pulse applied between the ground terminal and the input pad 5 is absorbed by the NMOS transistor 2. Absorbed by. With the above configuration, the internal circuit connected to the output terminal of the input buffer 4 is protected from the electrostatic pulse from the outside.

FIG. 6 is a circuit diagram of the output protection circuit provided on the output pad 15. The output signal from the internal circuit is amplified by the pre-driver 14 and then applied to the gate of the open drain output NMOS transistor. The source terminal of this open drain output NMOS transistor is grounded, and the drain terminal is connected to the output pad 15. As a result, the output signal from the internal circuit is output from the output pad 15 as an open drain output. Also in FIG. 6, FIG.
Similarly, the PMOS type transistor 11 and the NMOS type transistor 12 are included in the output protection circuit. Figure 5
Similarly, the source terminal and the gate terminal of this PMOS transistor are both connected to the power supply terminal, and the drain terminal thereof is connected to the output pad 15. And NM
The source terminal and the gate terminal of the OS type transistor 12 are both grounded, and the drain terminal thereof is similarly the output pad 1
Connected to 5.

With such a configuration, also in FIG. 6, the electrostatic pulse applied between the power supply terminal and the output pad 15 is absorbed in the PMOS transistor 11 and the ground terminal and the output pad 15 in FIG. 6 as well. The electrostatic pulse applied between and is absorbed by the NMOS transistor 12.
As a result, the internal circuit is protected from the electrostatic pulse that enters from the outside.

[0008]

Since the conventional input / output protection circuit of the semiconductor integrated circuit device is constructed in this manner, it is possible to effectively protect the internal circuit from an electrostatic pulse intruding from the outside. It is possible.

However, in recent years, a reduction in voltage of semiconductor integrated circuit devices has been promoted. That is, in the past, the power supply voltage of the semiconductor integrated circuit device was generally 5 volts, but as the density of the semiconductor integrated circuit has been increased, the power supply voltage has been reduced. The reason for lowering the power supply voltage is to maintain the reliability of the device as the integrated circuit structure is miniaturized. Another reason is that the power consumption of the semiconductor integrated circuit that can be sealed in one package is limited, and it is necessary to reduce the power consumption as the density increases.

Under such a background, a semiconductor integrated circuit device which operates at, for example, 3 V or 3.3 V has been proposed. When such a semiconductor integrated circuit device of 3 volt operation and a conventional semiconductor integrated circuit device of 5 volt operation are connected, the input / output pad of 3 volt operation is connected to another semiconductor integrated circuit device of 5 volt operation. When 5 V is applied, a current due to the potential difference flows from the device operating at 5 V into the device operating at 3 V through the parasitic diode of the PMOS transistors 1 and 11 connected to the input / output pad. Such a current may cause a malfunction or latch-up of the semiconductor integrated circuit device.
Therefore, in order to eliminate such a current path, the PMO
If the S-type transistors 1 and 11 are removed, the ESD withstand voltage naturally lowers.

The present invention has been made in view of the above problems, and an object thereof is to maintain an ESD withstand voltage without causing malfunction or latch-up even when connected to semiconductor integrated circuit devices having different operating voltages. A semiconductor integrated circuit device that can be obtained is obtained.

[0012]

In order to solve the above-mentioned problems, the first invention is a diode having a cathode terminal connected to a power supply terminal, a base terminal and an emitter terminal connected to an input or output terminal, and a collector. A PNP transistor whose terminal is connected to the anode terminal of the diode, the PNP transistor being formed on an independent well which is not connected to another circuit, the input or output terminal This is an input / output protection circuit that absorbs the electrostatic pulse that has entered from.

In order to solve the above problems, the second aspect of the present invention is directed to a diode having a cathode terminal connected to a power supply terminal, a gate terminal and a source terminal connected to an input or output terminal, and a drain terminal connected to the anode of the diode. An P-channel FET connected to a terminal, the P-channel FET formed on an independent well that is not connected to other circuits, and an electrostatic pulse entering from the input or output terminal. It is an input / output protection circuit that absorbs.

[0014]

In the PNP transistor according to the first aspect of the present invention, when an electrostatic pulse enters the input or output terminal, a breakdown occurs between the emitter terminal and the collector terminal and absorbs the electrostatic pulse. On the other hand, if a voltage slightly higher than the power supply voltage to which the cathode terminal of the diode is connected is applied to the input or output terminal, PN
Since there is no electrical connection between the emitter terminal and the collector terminal of the P-type transistor, normal operation is not affected.

P-channel FET in the second invention
Also has the same operation as the PNP transistor in the first aspect of the present invention.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an input protection circuit which is a preferred embodiment of the present invention. The input protection circuit according to this embodiment includes a PMOS transistor 21 having a gate terminal and a drain terminal connected to an input pad 25,
The diode 26 has a cathode terminal connected to the power supply terminal and an anode terminal connected to the source terminal of the PMOS transistor 21 described above. The input protection circuit according to the present embodiment has a protection resistor 23 connected between the input pad 25 and the input buffer 24 as in the conventional case.
And an NMOS transistor 22 which is also connected to the input pad 25. These protection resistors 2
3 and the NMOS type transistor 22 have a conventional configuration, and their operation is also similar to that of the conventional one.

The characteristic configuration of this embodiment is the series circuit of the PMOS transistor 21 and the diode 26 described above. With this configuration, even if the semiconductor integrated circuit device having an operating voltage higher than the power supply voltage applied to the cathode terminal of the diode 26 applies a signal higher than the power supply voltage to the input pad 25, the PMOS transistor 21 does not become conductive. In addition, there is no possibility that an unexpected current will flow.

FIG. 2 shows a sectional view of the structure of the PMOS transistor 21 shown in FIG. 1 on the semiconductor substrate. As shown in FIG. 2, P in this embodiment is
The MOS transistor 21 is formed on the N well which is independent of other circuits. Two P + diffusion regions are provided on the N well. They are a source region 29 and a drain region 27. Further, a gate electrode 28 is provided between these two regions with an insulating film interposed. As shown in FIGS. 1 and 2, the source region 29 and the gate electrode 28 are both connected to the input pad 25. Also, the drain region 27 is connected to the anode of the diode 26 as shown in FIGS.

The characteristic of this embodiment is that the PMO
That is, the S-type transistor 21 is formed on the N-well independent of other circuits. With this configuration,
As shown in FIG. 2, one parasitic diode is formed between the source region 29 and the N well. Similarly, a parasitic diode is formed between the drain region 27 and the N well. Therefore, from the input pad 25,
In the circuit reaching the power supply terminal VDD, three diodes including the diode 26 are provided.

FIG. 3 shows how these three diodes are formed between the input pad 25 and the power supply terminal VDD. As shown in FIG. 3, three diodes are connected in series between the input pad 25 and the power supply terminal. Of these, the diode derived from the PMOS transistor 21 is connected with its anode terminals opposed to each other, and the diode 26 is connected between these two diodes and the power supply terminal with its cathode terminal facing the power supply terminal. Has been done.

As described above, since the three diodes are connected in series, for example, when a high voltage electrostatic pulse is applied to the input pad 25, the two diodes derived from the PMOS transistor 21 as described above. Of the parasitic diodes, the diode on the side of the drain region breaks down and absorbs this electrostatic pulse, so that the internal circuit connected to the input pad 25 can be protected from the electrostatic pulse.

When the semiconductor integrated circuit device is combined with other electronic components to form an electronic device, a signal having a voltage lower than the power supply voltage VDD may be applied to the input pad 25. is there. For example, when the power supply voltage is 3 V, the input pad 25 has about 0
A signal having a voltage value from the voltage up to a voltage close to 3 volts is input. In such a case, since the diode 26 is reverse biased, an unexpected current does not flow.

Further, in the case where the operating voltage of the semiconductor integrated circuit device according to this embodiment is, for example, 3 volts, when an output signal from another semiconductor integrated circuit device operating at 5 volts is applied to the input pad 25. , A signal with a voltage of approximately 0 V to a maximum of 5 V is applied to the input pad 25. In this case, one of the parasitic diodes derived from the PMOS transistor 21 is reverse-biased. Therefore, similarly, an unexpected current does not flow. A feature of this embodiment is that a diode opposite to the diode 26 having the conventional configuration is connected in series between the input pad 25 and the power supply terminal. With such a configuration, even if a semiconductor integrated circuit device or the like having an operating voltage higher than the operating voltage of the semiconductor integrated circuit device according to the present embodiment is connected and a voltage higher than the power supply voltage VDD is input to the input pad 25, A large current does not flow from the pad 25 to the power supply terminal.

As described above, according to this embodiment, it is possible to coexist with another semiconductor integrated circuit device or the like having a different power supply voltage, and an internal circuit can be obtained from an electrostatic pulse input via an input pad or the like. A semiconductor integrated circuit device that can be protected is obtained. It is also suitable to apply the protection circuit of the present invention to the output circuit.

FIG. 4 shows a circuit diagram of such an output protection circuit. As shown in FIG. 4, this output protection circuit is similar to the input protection circuit shown in FIG. 1 in that it has a PMOS transistor 31 whose gate terminal and drain terminal are connected to the output pad 35. , And a diode 36 having an anode terminal connected to the source terminal of the PMOS transistor 31. The cathode terminal of the diode 36 is connected to the power supply terminal. That is, P shown in FIG.
The MOS transistor 31 is the PM shown in FIG.
Corresponding to the OS type transistor 21, the diode 36 is
It corresponds to the diode 26 of FIG. Therefore, a series circuit composed of three diodes as shown in FIG. 3 is formed between the power supply terminal and the output pad 35, and as described above, the electrostatic pulse entering from the output pad 35 is effective. The output pad 35 is connected to a semiconductor integrated circuit device or the like having another operating voltage, so that an unexpected current flows even if a voltage higher than the power supply voltage VDD is applied to the output pad 35. Never.

The circuit shown in FIG. 4 has a pre-driver 34 for amplifying an output signal from the internal circuit and an output signal of the pre-driver 34 as an open drain output as in the conventional circuit shown in FIG. And an NMOS transistor 33 having an open drain output for converting to. Further, an NMOS transistor 32, which is a part of a protection circuit, is provided between the output pad 35 and the ground as in the conventional case of FIG. As described above, since the circuit shown in FIG. 4 is an output circuit having an open drain output, a voltage higher than the power supply voltage VDD is often applied to the output pad 35.

As described above, according to this embodiment, the semiconductor integrated circuit device is mixed with another semiconductor integrated circuit device having a different power supply voltage without lowering the withstand voltage against ESD (electrostatic discharge) breakdown. A semiconductor integrated circuit device capable of forming two electronic devices is obtained.

[0029]

As described above, according to the input / output protection circuit of the present invention, an electrostatic pulse from the outside is absorbed to cause ESD.
(EN) A semiconductor integrated circuit device capable of protecting an internal circuit from destruction due to (electrostatic discharge), which can be combined with another semiconductor integrated circuit device having a different operating voltage. it can.

Therefore, by using the semiconductor integrated circuit device to which the input / output protection circuit according to the present invention is applied, the withstand voltage against ESD (electrostatic discharge) can be reduced while reducing the power consumption and the density of electronic equipment. It is possible to prevent.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input protection circuit according to an embodiment.

2 is a cross-sectional structure diagram of a PMOS transistor 21 of FIG.

3 is a schematic circuit diagram from the input pad 25 of FIG. 1 to a power supply terminal.

FIG. 4 is a circuit diagram of an output protection circuit of this embodiment.

FIG. 5 is a circuit diagram of a conventional input protection circuit.

FIG. 6 is a circuit diagram of a conventional output protection circuit.

[Explanation of symbols]

 21 PMOS type transistor 22 NMOS type transistor 23 Protection resistor 24 Input buffer 25 Input pad 26 Diode

Claims (2)

[Claims] 1. A PNP transistor having a cathode terminal connected to a power supply terminal, a base terminal and an emitter terminal connected to an input or output terminal, and a collector terminal connected to an anode terminal of the diode. An input / output protection circuit that absorbs an electrostatic pulse that has entered from the input or output terminal, and a PNP transistor formed on an independent well that is not connected to another circuit. 2. A P-channel FET having a cathode terminal connected to a power supply terminal, a gate terminal and a source terminal connected to an input or output terminal, and a drain terminal connected to an anode terminal of the diode. An input / output protection circuit that absorbs an electrostatic pulse that has entered from the input or output terminal, including a P-channel FET formed on an independent well that is not connected to other circuits.