JPH06196664A - Gate-array type semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Objective] In a gate array semiconductor integrated circuit device including a basic cell including the same number of PMOS type transistors and NMOS type transistors, when a memory cell of a RAM is configured, it becomes unused. A semiconductor integrated circuit device using a PMOS transistor as a ROM is obtained. In the memory section 20 including memory cells, R
Remaining unused P when AM memory cells are configured
The MOS type transistor is used as a memory cell of the ROM. That is, the gate terminal of this unused PMOS transistor is connected to the newly provided ROM WORD line 22b, the source terminal is connected to the power supply terminal, and the drain terminal is connected to the BIT line according to the stored data. Connect or disconnect. This WORD line for ROM has R
The selection signal is supplied only when the ROM is selected by the AM / ROM switching signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device. In particular, it relates to a basic cell of a gate array type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices are generally designed and developed by a gate array method because the development period thereof is short. In this gate array method, a master slice in which basic cells are spread is prepared in advance, and wiring in the basic cells and wiring between the basic cells are performed according to the design data of the designer. In this way, a desired electronic circuit is designed and manufactured. In the conventional CMOS gate array type semiconductor integrated circuit device, generally, the same number of P
A MOS type transistor and an NMOS type transistor are included in the basic cell. A so-called CMOS type circuit is configured by using these PMOS type transistors and NMOS type transistors. As is well known, this CMOS type circuit has excellent properties such as low power consumption.

In such a gate array type semiconductor integrated circuit device, it is not uncommon for an internal RAM to be provided at the request of the designer. The memory cell of this RAM is generally composed of a circuit as shown in FIG. As shown in FIG. 2, the memory cell of the RAM is composed of two inverter circuits 10a and 10b and pass transistors 12a and 12b for connecting their data lines to the BIT line or the inverted BIT line. ing. The output terminals of the inverters 10 (a, b) are connected to the input terminals of the other inverter circuits 10 (a, b), forming a flip-flop circuit. That is,
Data is externally written to and read from the flip-flop circuit portion. At the time of reading or writing, a selection signal is supplied to the WORD line, and this selection signal is applied to the gate of the pass transistor 12 (a, b). By this, pass transistor 1
2 (a, b) becomes conductive, and the BIT line and the inverted BI
The data on the T line is written in the above-mentioned flip-flop circuit, or the state of the flip-flop circuit is read out as data on the BIT line and the inverted BIT line.

As described above, one memory cell of the RAM is composed of two PMOS type transistors and four NMOS type transistors. On the other hand, as described above, one basic cell of the gate array type semiconductor integrated circuit device has the same number of PMOS transistors and NMs.
Since an OS type transistor is included, if a conventional gate array type semiconductor integrated circuit device is used to construct a RAM, the PMOS type transistor is generally left over. For example, as a basic cell, two PMOS
Type transistor and two NMOS type transistors are included, two basic cells are used to form one RAM memory cell and two PMOS cells.
Type transistors are unused.

[0005]

As described above, since the basic cell of the conventional gate array type semiconductor integrated circuit device includes the same number of PMOS type transistors and NMOS type transistors, it constitutes a memory cell of RAM. If this is attempted, there is a problem that the PMOS type transistor is unused. In the above-mentioned example, the unused P when configuring one memory cell
Although the number of MOS type transistors is two, the capacity of a RAM is generally very large, and therefore the number of unused PMOS type transistors is not negligible.

The present invention has been made in view of the above problems, and an object thereof is to use a surplus PMOS type transistor for another purpose when a memory cell of a RAM is constituted in a gate array type semiconductor integrated circuit device. Another object of the present invention is to provide a gate array type semiconductor integrated circuit device.

[0007]

In order to solve the above-mentioned problems, the present invention provides an NMOS type transistor and a PMOS.
Gate array type semiconductor integrated circuit including a basic cell including the same number of type transistors, wherein the basic cell includes a flip-flop unit including two NMOS type transistors and two PMOS type transistors. A first NMOS-type transistor connecting one output terminal of the flip-flop unit and a bit line,
A second NMOS transistor that connects the other output end of the flip-flop unit and an inverted bit line, and further has a gate terminal connected to a word line, a source terminal connected to a power supply terminal, and a hold And a PMOS PMOS transistor in which the bit line is connected or not connected to the drain terminal according to the data to be supplied, and when a selection signal is supplied to the word line The data is output to the bit line, which is a gate array type semiconductor integrated circuit device.

[0008]

The ROM PMOS transistor of the present invention stores digital data depending on whether its drain terminal is connected to the bit line or not.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a partial block diagram of a semiconductor integrated circuit device according to a preferred embodiment of the present invention.
FIG. 1 shows a memory unit 20 including a RAM memory cell and a ROM memory cell, and a RAM WORD of the memory unit 20.
A circuit diagram is shown which includes line 22a and ROM WORD line 22b and a controller 30 which sends a select signal to them. Further, FIG. 1 shows the BI of the memory unit 20.
A precharge section 40 for precharging the T line and the inverted BIT line is shown.

A feature of this embodiment is that the memory section 20 includes a memory cell of a ROM. The basic cell used in this embodiment is a basic cell including two PMOS type transistors and two NMOS type transistors in one basic cell, and as shown in FIG. A RAM memory cell using four NMOS transistors is configured by two basic cells. Then, as described in the conventional technique, the two PMOS type transistors are unused. In this embodiment, the two unused PMOS transistors are used as the ROM memory cell. As shown in FIG. 1, the source terminals of these two PMOS type transistors are commonly connected to the power supply terminal, and the gate terminals thereof are commonly connected to the ROM WORD line 22b. The drain terminal is connected or disconnected from the BIT line according to the digital data to be held. Note that FIG. 1 shows an example in which the drain terminal is connected to the BIT line.

In this embodiment, the unused P
The memory cell of the ROM was constructed using the MOS type transistor. The ROM supplied to the memory cell of this ROM
The work WORD line 22b is provided separately from the RAM WORD line 22a supplied to the memory cells of the RAM.
RAM WORD supplied to RAM memory cells
The line 22a is supplied with a selection signal generated by decoding the address signal as in the conventional case. First, the address signal is decoded by the decoder 32, and the decoded selection signal is sent to the selector 34a and the driver 36a.
Is supplied to the WORD line 22a for RAM via the.
The selection signal output from the decoder 32 is also supplied to the ROM WORD line 22b newly added in the present embodiment via the selector 34b and the driver 36b. And switching between RAM and ROM is RA
It is switched by the M / ROM switching signal. That is, this RAM / ROM switching signal is sent to the selector 34.
The RAM / ROM signal supplied to a and inverted is supplied to the selector 34b. That is, selector 3
One of 4a and 34b is selected, and only one outputs a selection signal. In this way, RAM / R
The OM switching signal is controlled so that the selection signal is output only to one of the RAM and the ROM.

As described above, according to this embodiment, the memory unit 2
Since the ROM is constructed by using the PMOS type transistor which has not been used in the prior art, the ROM can be provided without increasing the area of the memory section 20. Further, in the control unit 30, a new selector 34b is added.
It is possible to newly create the WORD line 22b for ROM simply by providing the driver 36b and the inverter 38. This newly added configuration is required for the number of WORD lines, but since the area occupied by the control unit 30 is extremely smaller than that of the memory unit 22 described above, there is almost no effect on the increase in area in the semiconductor integrated circuit device. Does not affect

In this embodiment, since the memory cell of the ROM is constructed by using the PMOS type transistor,
It is desirable that the precharge level is "L" level when reading the data held in the ROM.
In this case, it is possible to change the level of the precharge voltage by switching the precharge circuit using the RAM / ROM switching signal described above. In such a configuration, the precharge unit 40 has a precharge circuit for precharging to the “H” level in case the RAM memory cell is accessed, and a precharge circuit for accessing the ROM memory cell. It is necessary to switch to a precharge circuit that precharges to the “L” level, which increases the circuit area accordingly.

Therefore, in this embodiment, the precharge section 40 is composed of only one precharge circuit. As shown in FIG. 1, the precharge section 40 in the present embodiment is configured by using three PMOS type transistors, the respective gate terminals are commonly connected, and the precharge signal is commonly supplied. What is characteristic of the precharge section 40 in this embodiment is that the precharge level is VDD / 2. That is, in the present embodiment, the precharge level is set to half the power supply voltage so that the common precharge level is applied when the RAM memory cell is accessed and when the ROM memory cell is accessed. Is what you are doing. With such a configuration, the common precharge circuit can be used regardless of which memory cell is accessed, and the circuit area does not increase compared to the conventional case.

As described above, even if another precharge circuit is prepared for the case where the ROM is accessed, the area occupied by the precharge section 40 is larger than that of the memory section 20 described above. Since it is extremely small, the area of the entire semiconductor integrated circuit device does not increase significantly.

As described above, according to this embodiment, N
When a RAM memory cell is configured by using basic cells including the same number of MOS transistors and PMOS transistors, unused PMOS transistors are used as ROM memory cells. Therefore, since the PMOS type transistor which has not been used conventionally is used as the ROM, the ROM can be newly provided without increasing the area of the memory section 20. Further, at that time, the configuration of the control unit 30 is increased by only one selector, one driver and one inverter for each WORD line.

Furthermore, in the present embodiment, the precharge level is set to half the power supply voltage. Therefore, the common precharge section 40 is used when the RAM memory cell is accessed and when the ROM memory cell is accessed. It can be used, and there is no increase in the configuration of the precharge unit 40. Therefore, according to the present embodiment, it is possible to configure the memory cells of the ROM to have the same capacity in the portion where the memory cells of the conventional RAM are configured without increasing the area of the semiconductor integrated circuit. As a result, a semiconductor integrated circuit device can be obtained which can include a ROM without increasing the area of the semiconductor integrated circuit device.

In this embodiment, two unused PMOS type transistors are connected in parallel and
I configured the memory cell of the bit ROM.
It is also preferable to prepare two ORD lines 22b and use them as different ROM memory cells. However, in that case, R
Since the OM capacity doubles, a new address of 1
One address line is required, and one selector, one driver, and one inverter are required for each WORD line. However, even in that case, the memory unit 20
Since the area of the semiconductor integrated circuit device does not increase at all, the increase in the area of the entire semiconductor integrated circuit device can be suppressed to an extremely small value.

[0020]

As described above, according to the present invention, the RO can be realized without increasing the chip area of the semiconductor integrated circuit device.
An effect is obtained that a gate array type semiconductor integrated circuit device capable of incorporating M is obtained.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a gate array type semiconductor integrated circuit device according to a preferred embodiment of the present invention.

FIG. 2 is a configuration circuit diagram of a memory cell of a RAM in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 20 memory unit 22a, 22b WORD line 30 control unit 32 decoder 34a, 34b selector 36a, 36b driver 38 inverter 40 precharge unit

Claims (1)

[Claims] 1. A gate array semiconductor integrated circuit comprising a basic cell including the same number of NMOS type transistors and PMOS type transistors, wherein the basic cell includes two NMOS type transistors and two PMOS type transistors. Type transistor, a first NMOS-type transistor connecting one output terminal of the flip-flop section and a bit line, the other output terminal of the flip-flop section, and an inverted bit A second NMOS-type transistor for connecting to a line, and a gate terminal connected to a word line, a source terminal connected to a power supply terminal, and the bit line connected to a drain terminal according to the data to be held. Or P for ROM not connected
A MOS transistor, and when a selection signal is supplied to the word line,
A gate array type semiconductor integrated circuit device, characterized in that it outputs data according to the connection or non-connection state to the bit line.