JPH0619681A - Redundant binary/binary conversion circuit including rounding processing - Google Patents

Abstract

PURPOSE:To provide a redundant binary/binary conversion circuit including a rounding processing only by the addition of a few circuits and the increase of a few delay to the redundant binary/binary conversion circuit. CONSTITUTION:An addition necessary for the rounding processing is operated based on a redundant numerical expression by a redundant binary adder 1 for the rounding processing. The transmission of a carry can be limited by the addition operated based on the redundant numerical expression, so that a high parallel property can be realized without necessitating a large-scaled carry preparing circuit indispensable to a binary high speed parallel adder. Then, the redundant binary expression is converted into a binary by a redundant binary/binary conversion circuit 2, and the number of the digits necessary for the rounding processing is limited by a number of digit limiting circuit 3 for the rounding processing based on the binary expression. The characteristic of the round-down of the digits of the redundant numerical expression is different from that of the binary due to the redundancy, and then the round-down of the digits of the redundant numerical expression is operated after the redundant numerical expression is converted into the binary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant binary / binary conversion circuit including digital type rounding processing.

[0002]

2. Description of the Related Art A redundant binary number system is a kind of binary weighted number system, and a normally used binary number system represents each digit by a binary value of {0, 1}, whereas each digit is a code. With {-1,
It is characterized in that it is expressed by three values of 0, 1}, and because of its redundancy, carry propagation that limits the speed of ordinary binary number operations can be limited to only one stage, so that highly parallel operations can be realized.

Conventionally, in redundant binary / binary conversion, each digit is {-
Redundant binary number consisting of 1,0,1} with each digit {0,1}
It is known that it can be realized by dividing into a positive number consisting of and a negative number consisting of {−1,0} for each digit and adding based on a binary number.

Further, it is known that the rounding process can be realized by adding 1 to the digit immediately below the least significant digit of the required digit and then truncating the digits below that digit.

Therefore, redundant binary / 2 including rounding processing
The decimal conversion can be realized by sequentially performing these. FIG. 4 shows this configuration.

[0006]

However, in the redundant binary / binary conversion circuit including the rounding processing configured by using the conventional technique, both the conversion and the rounding processing are realized by using a binary adder, Since each carry propagates, two large-scale carry-look-ahead parallel adders are required to realize a high-speed circuit. Therefore, redundant binary / 2
The addition of the rounding function to the binary conversion circuit doubles the hardware, and also increases the delay due to the increase in the number of gate stages.

An object of the present invention is to provide a redundant binary / binary conversion circuit including a rounding process with a small addition of a circuit and a slight increase in delay. is there.

[0008]

A redundant binary / binary conversion circuit including rounding processing according to the present invention is necessary for rounding processing in a circuit that performs rounding processing and conversion from redundant binary number representation to binary number representation. The addition is performed based on a redundant number expression, conversion into a binary number is performed, and the number of digits required for rounding processing is limited based on the binary number expression.

[0009]

Operation: Rounding processing consists of addition and rounding down of digits. Since addition in the redundant number representation can limit carry propagation,
High parallelism can be realized without requiring a large-scale carry generation circuit which is indispensable for a binary high-speed parallel adder. Therefore, the rounding process is not performed after the conversion to the binary number, but the addition necessary for the rounding process is performed as it is in the redundant number representation, whereby the addition in the rounding process can be realized quickly and compactly. The digit truncation is performed after the conversion to the binary number because the property is different from the digit truncation in the binary number due to its redundancy in the redundant number expression. By this procedure, the redundant binary / binary conversion including the rounding process is added to the redundant binary / binary conversion circuit by adding one parallel adder based on the redundant number system and increasing the delay of one stage of the redundant number full adder. It can be achieved in a certain degree.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Adder 1 adds redundancy required for rounding processing as is 2
Based on the base number system, and then the conversion circuit 2 is used to provide redundancy 2.
The addition for binary / binary conversion is performed, and finally, the digit number limiting circuit 3 limits the number of digits necessary for rounding processing by rounding down the digits.

FIG. 2 shows another embodiment of the present invention. The adder 4 performs the addition required for the rounding processing as it is based on the redundant binary number system, and then the conversion circuit 5 performs the addition for the redundant binary / binary conversion and limits the number of digits required for the rounding processing. ing. By performing the limitation of the number of digits together with the redundant binary / binary conversion, circuits for sum generation other than the carry signal generation circuit can be deleted in the limited digits, so that the embodiment of FIG. Hardware can be reduced in comparison.

FIG. 3 shows another embodiment of the present invention. An adder 6 converts the redundant binary number into a redundant number represented by the following equation and performs addition necessary for rounding processing based on this redundant number system. Here, X is n digits.

[0014]

Next, the conversion circuit 7 converts the redundant number system to the binary number system and limits the number of digits necessary for the rounding process. Redundant binary / binary conversion can be considered as interposing the redundant number system.

[0016]

1 is a redundant binary number system, and 3 is a binary number system (in 2's complement representation). Here, the range of X is 2 of 3
The range can be expressed in the base system. The adder 6 includes a conversion circuit 8 and a conversion circuit 9. Redundancy 2 of 1 in the conversion circuit 8
Conversion from the base number to the redundant number of 2 and linear addition for rounding are performed, and then the conversion circuit 9 compresses the dynamic range for obtaining the output of the redundant number of 2. The conversion from the redundant binary number of 1 to the redundant number of 2 is x at each digit.
(2) _i = x (1) _i + 1 may be calculated. Redundancy 2
In the case of implementing a radix operation by a logic circuit, the value of each digit is usually represented by a 2 bit two's complement number. That is, -1 is 1
1, 0 is represented by 00 and 1 is represented by 01. Replace each digit with {0, 1,
In the 2 redundant number system expressed by 2}, if each digit is expressed as 00, 1 as 01 and 2 as 10, to convert the redundant binary number of 1 into the redundant number of 2, 1 = (1
1) to 0 = (00), 0 = (00) to 1 = (01)
Then, 1 = (01) may be replaced with 2 = (10), and the first bit can be realized by logical inversion 12, and the second bit can be realized by the exclusive OR 11 of both bits. Therefore, this conversion can be realized by adding a few circuits, and since propagation of carry does not occur, it can be realized in high parallel. In the linear addition for rounding, at the digit k for adding 1, in the conversion from the redundant binary number of 1 to the redundant number of 2, −1 = (11)
1 = (01), 0 = (00) 2 = (10) and 1
This can be realized by converting = (01) into 3 = (11), which is the logical inversion 13 of the second bit while the first bit remains unchanged.
You can do it only. This conversion is easy and adds little circuitry and delay. By this linear addition, each digit becomes {0, 1,
2, 3}. The compression of the dynamic range to {0,1,2} can be realized as follows.

[0018]

Since s _i only depends on the i digit and the (i-1) digit, this operation can be performed in a highly parallel manner. Generation of c _i and w _i in step 1 can be performed with c _i = 0 w _i = x _i x _i <2 c _i = 1 w _i = x _i −2 x _i ≧ 2. In the redundant number representation of 2, the operation consisting of the above two steps can be realized only by the half adder.
The circuit is added by the number of digits of the half adder, and the increase in delay is only for one stage of the half adder.

The conversion from the redundant number of 2 to the binary number of 3 performed by the conversion circuit 7 is performed from {0, 1, 2} to {0,
Compression of the dynamic range to 1} and 1 to the least significant digit
This can be done by adding, and the carry input C _-1 of the least significant digit is 1
Can be realized by the parallel adder 10 of. If a carry lookahead type is used as the parallel adder, the first bit of x (2) _i can be used as the carry propagation signal p _i and the second bit can be used as the carry generation signal g _i without modification. The number of circuits to generate can be reduced.

This circuit reduction is due to the redundancy 2 of the above-mentioned 1
Responsible for adding a circuit for conversion from the base number to the redundant number of 2, and as a whole, the addition of the circuit is the number of digits of the half adder, and the increase of the delay is one half adder. .

The addition of 1 to the least significant digit for conversion from the redundant number of 2 to the binary number of 3 is realized assuming that the least significant digit of the adder has a carry input in this embodiment. However, if the rounding addition is not performed on the least significant digit, the least significant digit is the same as the digit for adding 1 for rounding.
It can also be realized by converting the redundant binary number of 2 to the redundant number of 2.

[0023]

When the redundant binary / binary conversion circuit including the rounding processing of the present invention is used, in addition to the redundant binary / binary conversion circuit in the configuration using the conventional technique, a large-scale binary number is used. Although the parallel adder was required, in the example of FIG. 3, the rounded conversion output is obtained only by increasing the number of circuits in the half adder by the number of digits and increasing the delay by one stage of the half adder. Obtainable.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a redundant binary / binary conversion circuit including rounding processing according to the present invention.

FIG. 2 is a diagram showing an embodiment of a redundant binary / binary conversion circuit including another rounding process of the present invention.

FIG. 3 is a diagram showing an embodiment of a redundant binary / binary conversion circuit including another rounding process of the present invention.

FIG. 4 is a diagram showing an example of a redundant binary / binary conversion circuit including rounding processing configured by using a conventional technique.

[Explanation of symbols]

1,4 Redundant binary number rounding adder 2,17 Redundant binary / binary conversion circuit 3,19 Rounding processing digit number limiting circuit 5 Redundant binary / binary conversion circuit including rounding processing digit number limitation 6 Redundant number rounding adder with weight 2 in which each digit takes {0,1,2} 7 Redundant / binary with weight 2 in which each digit including rounding digit limit includes {0,1,2} Conversion circuit 8 Redundant binary including linear addition for rounding / each digit is {0,
Redundancy conversion circuit of weight 2 taking 1, 2, 3} 9 Redundancy of weight 2 in which each digit takes {0, 1, 2, 3} / Redundancy of weight 2 in which each digit takes {0, 1, 2} Conversion circuit 10 Binary carry look-ahead parallel adder 11 Exclusive OR gate 12,13 Logical inversion gate 14,15,16 Half adder 18 Binary rounding adder

Claims (1)

[Claims] 1. A circuit that performs rounding processing and conversion from redundant binary number representation to binary number representation, performs addition necessary for rounding processing based on redundant number representation, and performs conversion to binary number A redundant binary / binary conversion circuit including a rounding process, wherein the number of digits required for the rounding process is limited based on the expression.