JPH0619702B2 - Full adder circuit - Google Patents

Description

The present invention relates to a full adder circuit, and more particularly to a full adder circuit suitable for being configured by a field effect transistor (hereinafter abbreviated as FET).

[Conventional technology]

A full adder circuit configured by combining CMOS logic gates is often used. The multi-bit full adder circuit can be configured by a 1-bit full adder whose number is equal to the number of bits.

FIG. 2 is a logic circuit diagram showing an example of such a conventional 1-bit full adder.

In FIG. 2, 31.34.35.38 are NOR gates, 32.36.39 are NAND gates, and 33.37 are NOT gates. The two parts surrounded by the broken line are each a 1-bit half adder.
A 1-bit full adder can be configured with a bit half adder and one NAND gate.

In the conventional example shown in FIG. 2, the input data signals A and B and the input carry signal C _i are input, and the addition data signal S and the output carry signal C ₀ are output.

FIG. 3 is an explanatory diagram showing the input / output relationship of the conventional example shown in FIG. 2, that is, the input / output relationship of a general 1-bit full adder.

The input / output relationship shown in FIG. 3 is also expressed by two logical expressions: S = (A • + • B) • ▲ ▼ + (A • B + •) • C _i ……… (1) C ₀ = A・ B + B ・ C _i + C _i・ A ... (2)

As is well known, the NOR gate and the NAND gate of CMOS each require 4 FETs.
Since the T gate requires 2 FETs, the conventional example shown in FIG. 2 requires 32 FETs. The 16-bit full adder configured in the conventional example shown in FIG. 2 requires 512 FETs.

[Problems to be solved by the invention]

As described above, the conventional full adder circuit has a large number of required FETs per bit, so that it is expensive, consumes a large amount of power, and has complicated wiring and long wiring. There is.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a full adder circuit which requires a small number of FETs, is therefore economical, consumes less power, has simple wiring, and has a high operation speed.

[Means for solving problems]

The full adder circuit of the present invention comprises first, second, third, fourth, fifth, sixth and seventh switch means, and a first conductivity type field effect type first, second ,. Third, fourth, fifth, sixth and seventh transistors, and field effect type eighth, ninth, tenth, eleventh, which is a second conductivity type different from the first conductivity type. Twelfth, thirteenth, fourteenth, fifteenth and sixteenth transistors, wherein the sources of the first and second transistors are common to the first terminal of the power supply and the gate is The first and second switch means are connected to the first terminal of the power supply, and the drain is connected to the second terminal of the power supply via the third and fourth switch means, and the third A fourth transistor and the fifth, sixth, and seventh transistors are connected in series and parallel, and the sources of the third and fifth transistors are connected to the first of the power source. Commonly connected to a terminal, the drains of the fourth and seventh transistors are commonly connected to the addition data signal terminal through the fifth switch means, and the eighth and ninth transistors and the tenth An eleventh transistor and the twelfth and thirteenth transistors are connected in series and parallel, and the drains of the eighth, tenth and twelfth transistors are commonly connected to the gate of the first transistor. The sources of the ninth, eleventh, and thirteenth transistors are commonly connected to the second terminal of the power source, and the fourteenth, fifteenth, and sixteenth transistors are connected in series. The drain of the fourteenth transistor is connected to the gate of the second transistor through the sixth switch means, and the source of the sixteenth transistor is connected to the second terminal of the power supply. The 5th and 5th The gate of any one of the seventh set of transistors and the fourteenth, fifteenth, and sixteenth set of transistors is commonly used for the first input data signal terminal One gate of each of the two transistors is commonly connected to the second input data signal terminal, and the other gate of each of the two transistors is commonly connected to the input carry signal terminal.
Of the three groups of the tenth, eleventh, twelfth, and thirteenth transistors divided into groups of two transistors that are not connected in series with each other, one of the two gates of the first group is the first group. Common to the input data signal terminal of, two gates of the remaining two sets are commonly connected to the second input data signal terminal, the other two gates are commonly connected to the input carry signal terminal, One of the gates of the third and fourth transistors is connected to the gate of the first transistor and the other is connected to the drain of the second transistor, and the drain of the first transistor is output as a carry signal. It comprises a 1-bit full adder connected to the terminal and connecting the addition data signal terminal to the second terminal of the power supply via the seventh switch means.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a circuit diagram showing an embodiment of the full adder circuit of the present invention.

The embodiment shown in FIG. 1 is a 2-bit full adder circuit. It has a 1-bit full adder 1 for lower bits and a 1-bit full adder for upper bits.
And a bit full adder 2. The 1-bit full adder 1 receives the input data signals A ₁ and B ₁ , the input carry signal C _i1 , the precharge signal P, and the enable signal E ₁ and _2, and adds the addition data signal ₁ and the output carry signal. The signal C ₀₁ is output. The 1-bit full adder 2 receives the input data signals A ₂ and B ₂ , the input carry signal C _i2 , the precharge signal P, and the enable signal E ₁ and _2, and adds the added data signal ₂ and the output carry signal. The signal C ₀₂ is output. The terminal of the output carry signal C ₀₁ is connected to the terminal of the input carry signal C _i2 .

The 1-bit full adder 1 includes P-type FETs P _{1 to} P ₁₀ and N-type FETs N _{1 to} N ₁₃ . FET
The sources of P ₁ and P ₃ are connected to the power supply voltage _VDD terminal, and the gates are connected to the precharge signal terminal. FETN
_The sources of ₇ · N ₁₂ · N ₁₃ are connected to the terminals of the power supply voltage V _SS , and the gates thereof are connected to the terminals of the precharge signal P. FET
The drain of P ₁₀ is the terminal of the addition data signal ₁ and the FET
The gate is connected to the drain of N ₁₃ and the terminal of the enable signal ₂ . The drain of FETN ₁₁ is FET
The drain of P ₃ is connected to the gate of the enable signal E ₁ . The source of FETP ₂ · P ₄ is the terminal of power supply voltage V _DD , the gate is the drain of FETP ₁ · P ₃ ,
The drain is connected to the drains of FETs N ₇ and N ₁₂ . FETP ₅ .P ₆ and FETP ₇ , P ₈ and P ₉ are connected in series and parallel, and the source of FETP ₅ and P ₇ and FETP ₅ and P _{6 are connected.}
And a drain connected to the source terminal and FETP ₁₀ of the power supply voltage V _DD, a gate of FETP ₅ ~P ₉ is FETP ₂
Of the gate, the drain of the FET P ₄ , the terminal of the input data signal B ₁ , the terminal of the input signal A ₁ , and the terminal of the input carry signal C _i1 . FETN ₁・ N ₂ and FETN ₃・ N ₄ and FE
TN ₅ and N ₆ are connected in series and in parallel, and FET N ₁ N ₃ N ₅
Source and the drains of FETs N ₂ , N ₄ and N ₆ are the power supply voltage V
It is connected to the terminal of _SS and the gate of FETP ₂ , and FETN ₁
・ Gate of N ₆ and FET N ₃・ N ₅ and FET N ₂・ N
The gate of ₄ is connected to the terminal of the input data signal A ₁ , the terminal of the input data signal B _{1 and} the terminal of the input carry signal C _i1 . FETN _{8 to} N ₁₀ are connected in series, and FETN
The drain of the _eighth source and FETn ₁₀ of being connected to the source terminal and FETn ₁₁ of the power supply voltage V _SS, FETN ₈ ~N ₁₀
The gate of the input data signal B ₁ · input data signal A ₁ ·
It is connected to the terminal of the input carry signal C _i1 . FETP
The drain of ₂ is also connected to the terminal of the output carry signal C ₀₁ .

The 1-bit full adder 2 has the same configuration as the 1-bit full adder 1, and the input data signal A ₂ , the input data signal B ₂ , the input carry signal C _i2 , the addition data signal _2, and the output carry signal C _02. Corresponds to the input data signal A ₁ , the input data signal B ₁ , the input carry signal C _i1 , the addition data signal _1, and the output carry signal C ₀₁ of the 1-bit full adder 1.

Since the 1-bit full adders 1 and 2 perform the same operation, the operation of the 1-bit full adder 1 will be described.

FIG. 4 is a time chart for explaining the operation of the 1-bit full adder 1.

As shown in FIG. 4, the precharge signal P is a signal that periodically takes a logical value “1” in the section a and takes a logical value “0” in the sections b and c ... is there. The precharge signal is the precharge signal P as indicated by the reference numeral.
And the opposite phase signal. The timings of the start and end of the section a are set to timings t ₅ and t ₁ . Enable signal E ₁ is a logical value "1" from logic "0" at the earliest timing t ₂ later than the timing t ₅ the timing t _1, changed to a logic "0" from logic "1" with the timing t ₅ It is a signal. The enable signal ₂ changes from the logical value “1” to the logical value “0” at the timing t ₃ which is later than the timing t _{2 and} earlier than the timing t ₅ .
It is a signal that changes from a logical value “0” to a logical value “1” at timing t ₅ .

First, the operation in the section a will be described.

The input data signals A ₁ and B ₁ and the input carry signal C _i1 are set to the section logical value “0”. As a result, FETs N _{1 to} N ₆ and N ₈
~ N ₁₀ is turned off. Since the FET P ₁ is ON and the FETs N _{1 to} N ₆ are OFF in this section, the gate of the FET P ₂ is charged to the power supply voltage V _DD (voltage of logical value “1”). As a result, the FET P ₂ is turned off and the FET N ₇ is turned on, so that the drain of the FET P ₂ is charged to the power supply voltage V _SS (voltage of logical value “0”). Therefore, the output carry signal C ₀₁ has the logical value “0”. FETP ₃ is on,
FETn ₈ to N ₁₀ is because it is off, the gate of the FETP ₄ is charged to the supply voltage V _DD. As a result FET
Since P ₄ is off and FETN ₁₂ is on, F
The gate of ETP ₆ is charged to the power supply voltage V _SS . F
Since ETP ₁₀ is off and FETN ₁₃ is on,
The drain of FET P ₁₀ is charged to the power supply voltage V _SS . Therefore, the addition data signal ₁ also has the logical value "0". As described above, in the section a, the gates of the FETs P ₂ and P ₄ are set to the power supply voltage V _DD , the drains of the FETs P ₂ and P _{10 and} the FET P _{6 are connected.}
And the gate of is precharged to the power supply voltage V _SS and set to the initial state of the operation cycle. FETP ₁・ P
_{3 · N 7 · N 12 ·} N 13 is operating as a switch for controlling the precharge operation.

The section b is a calculation section when the input data signal A ₁ , the input data signal B _1, and the input carry signal C _i1 have the logical values “1”, “0”, and “1”. After timing t ₁ , FETP ₁
Is turned off and the FETs N ₁ and N ₂ are turned on, so that the gate of the FET P ₂ becomes the power supply voltage V _SS , and as a result, the FET P ₂ is turned on. On the other hand, since FETN ₇ is turned off, FETP ₂
Drain voltage rises, the logic value "1" is outputted as an output carry signal C _01. After timing t ₂ , FETP ₃ is turned off, FETN ₁₁ is turned on, but FETN ₈ is turned off, so the gate of FETP ₄ remains unchanged at the power supply voltage V _DD , and as a result, the gate of FETP ₆ is turned on at the power supply voltage V _SS. And FETP ₆ is on. The gate of the FETP ₅ is a gate the same voltage as the FETP ₂ FETP ₂
At the same time it is turned on. On the other hand, since the FET N ₁₃ is off, when the FET P ₁₀ is turned on after the timing t ₃ , the drain voltage of the FET P ₁₀ rises and a logical value “1” is output as the addition data signal ₁ . After the timing t ₃ , the addition data signal ₁ and the output carry signal C ₀₁ are sampled at the timing t ₄ which is before the timing t ₅ .
That is, the timing t ₄ is the read timing of the 1-bit full adder 1.

The section C is a calculation section when the input data signal A ₁ , the input data signal B _1, and the input carry signal C _i1 are logical values “0”, “0”, and “1”. In this case, FETN ₁ · N ₃ · N
_{Since 5} · N ₆ is off, the gate of the FET P ₂ remains at the power supply voltage V _DD , that is, the FET P ₂ remains off, so that the output carry signal C ₀₁ has the logical value “0”. F
Like ETP ₂ , FETP ₅ is off, and FETN ₈ · N
_{Since 9} · P ₉ is off, even if FETN ₁₁ · P ₁₀ is turned on, the gate of FET P ₄ is the power supply voltage V _DD , and FETP is
The drain of ₁₀ still has the power supply voltage V _SS , and therefore the addition data signal ₁ also has the logical value "0".

FIG. 5 is a logic circuit diagram showing the input / output relationship of the 1-bit full adder 1.

The correspondence between each FET in FIG. 1 and each logic gate in FIG. 5 will be described.

FETN ₁ · N ₂ is turned between a terminal of the drain of FETn ₂ and the power supply voltage V _SS only when both turned on. Therefore, the FETs N ₁ and N ₂ are expressed as the NAND gate 11 that receives the input data signal A ₁ and the input carry signal C _i1 . In FIG. 5, the reference numerals N ₁ and N ₂ are added to the two input signal lines of the NAND gate 11 so that the input data signal A ₁ and the input carry signal C _i1 are input to the gates of the FETs N ₁ and N _2. It shows that it is doing. Similarly, FETN ₃ · N ₄ and FETN ₅
A · N ₆ NAND gate 12 and NAND gate 13
Express as. When at least one drain of the FETs N ₂ , N _4, and N ₆ and the terminal of the power supply voltage V _SS are turned on, F
The gate of ETP ₂ changes from the power supply voltage V _DD to the power supply voltage V _SS ,
That is, since the logical value "1" changes to the logical "0", FE
The portion of the signal line that connects the drains of TN ₂ , N _4, and N ₆ to the gate of FET P ₂ in parallel is expressed as an AND gate 14. The drain of FETP ₂ If left gate logic value "1" of the FETP ₂ remains logic "0", because the gate is changed to a logic value "0" drain is changed to a logic value "1" , FETP ₂ is represented as a NOT gate 15. FETn ₈ to N _10, since everything is the logical value "0" to the gate of FETP ₄ from the logical value "1" only when turned on, the FETN ₈ ~N ₁₀ NAND gate 16
Express as. FETP ₄ is similar to FETP _{2 in} N
It is represented as an OT gate 17. FETP ₅ and P ₆ are
Only when both are on, the drain of FET P ₆ and the power supply voltage V _DD
It is expressed as a NOR gate 19 because it is turned on between the terminals of and. Similarly, the FETs P _{7 to} P ₉ are expressed as the NOR gate 18. Since between the at least terminal of the source and the power supply voltage V _DD of the turned on when FETP ₁₀ between the terminal of one of the drain and source voltage V _DD of FETP ₆ · P ₉ is on, FETP ₆ · P ₉ The drain of the FETP
The portion of the signal line connected in parallel to the ₁₀ sources is expressed as an OR gate 20. The FET P ₁₀ operates as an enable switch that controls the timing of outputting the addition data signal ₁ , and is not related to the logical operation. Similarly, the FET N ₁₁ operates as an enable switch that controls the timing of reading the on / off state of the FETs N _{8 to} N ₁₀ as the gate state of the FET P ₄ , and is not related to the logical operation. FETP ₁ / P ₃ / that controls the precharge operation
N ₇ · N ₁₂ · N ₁₃ also not related to the logical operation.

Now, when calculating the logical equation expressing the input-output relationship of the logic circuit shown in FIG. _{5, 1 = (A 1 · 1} + 1 · B 1) · C i1 + (A 1 · B 1 + 1 · 1)・_I1・ ・ ・ (3) C ₀₁ = A ₁・ B ₁ + B ₁・ C _i1 + C _i1・ A ₁ ...... (4) Inverted signals S ₁ of the addition data signal ₁ becomes _{S 1 = (A 1 · 1} + 1 · B 1) · i1 + (A 1 · B 1 + 1 · 1) · C i1 ......... (5) . Equations (1), (2) and (5), (4) have the same shape. That is, the logic circuit shown in FIG. 5 logically operates as a 1-bit full adder. From this, the 1-bit full adder shown in FIG. 1 certainly operates as a 1-bit full adder.

The 1-bit full adder 1 is composed of 23 FETs. If a 16-bit full adder circuit is constructed in the same manner as the embodiment shown in FIG. 1, the required number of FETs becomes 368. This number is much smaller than the number of 512 FETs required in the conventional 16-bit full adder circuit.

〔The invention's effect〕

As described in detail above, the full adder circuit of the present invention requires a small number of FETs per bit and simplifies wiring, and since it is a dynamic operation, there is no through current between power supplies when the signal level changes. It is economical, suitable for IC, has a high calculation speed, and has low power consumption. These effects become more remarkable as the number of bits increases.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of a full adder circuit of the present invention, FIG. 2 is a logic circuit diagram showing an example of a conventional 1-bit full adder, and FIG. Is an explanatory diagram showing the input / output relationship of a 1-bit full adder in general, FIG. 4 is a time chart showing the operation of the 1-bit full adder 1 in FIG. 1, and FIG. It is a logic circuit diagram which shows the input-output relationship of the 1-bit full adder 1 in the figure. 1 & 2 ...... 1-bit full _{adders, N 1 ~N 13 · P 1} ~P 10 ...
... FET.

Claims (1)

[Claims] 1. A first, a second, a third, a fourth, a fifth, a sixth and a seventh switch means, and a first conductivity type field effect type first, second, third. Fourth, fifth, sixth and seventh transistors and field effect type eighth, ninth, tenth, eleventh and twelfth which are second conductivity types different from the first conductivity type. A thirteenth, fourteenth, fifteenth, and sixteenth transistor, wherein the sources of the first and second transistors are common to the first terminal of the power supply, and the gate is the first The second terminal is connected to the first terminal of the power source via the second switch means, and the drain is connected to the second terminal of the power source via the third and fourth switch means, respectively. And the fifth, sixth, and seventh transistors are connected in series and parallel, and the sources of the third and fifth transistors are connected in front of the power source. Commonly connected to the first terminal, the drains of the fourth and seventh transistors are commonly connected to the addition data signal terminal through the fifth switch means, and the eighth and ninth transistors and the The tenth and eleventh transistors and the twelfth and thirteenth transistors are connected in series and parallel, and the drains of the eighth, tenth and twelfth transistors are connected to the gate of the first transistor. Commonly connected, the sources of the ninth, eleventh, and thirteenth transistors are commonly connected to the second terminal of the power source, and the fourteenth, fifteenth, and sixteenth transistors are connected. Connected in series, the drain of the fourteenth transistor is connected to the gate of the second transistor through the sixth switch means, and the source of the sixteenth transistor is connected to the second of the power supply. Connect to the terminal, The gate of any one of the fifth, sixth, and seventh transistor groups and the fourteenth, fifteenth, and sixteenth transistor groups is commonly used for the first input data signal terminal. , Each of the remaining two transistors has one gate commonly connected to the second input data signal terminal and the other gate commonly connected to the input carry signal terminal, respectively. Of the three sets of the eleventh, twelfth, and thirteenth transistors, which are divided into two transistors that are not directly connected to each other, one of the two gates is connected to the first input data. Common to the signal terminals, one of the remaining two gates of the two sets is connected to the second input data signal terminal in common, and the other two gates are connected to the input carry signal terminal in common, respectively, Connecting one of the gates of the fourth transistor to the gate of the first transistor and the other to the drain of the second transistor, and connecting the drain of the first transistor to the output carry signal terminal A full adder circuit, wherein the addition data signal terminal is connected to the second terminal of the power source through the seventh switch means.