JPH06201856A - Combined device - Google Patents

Abstract

(57) [Abstract] [Purpose] The time function processing of each clock means can be managed in a uniform time. [Configuration] After setting either one of the clock processing unit TM1 or the clock processing unit TM2 as a reference clock by the setting unit, the time data is transmitted from one clock unit in which the transmission unit is set as the reference clock to the other clock unit. The present invention is characterized in that when the receiving means receives the transmitted time data, the current time of one of the clock means is automatically corrected based on the time data received by the correcting means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a copy processing function,
The present invention relates to a composite device that can execute composite functions such as a facsimile processing function, a print processing function, and a file function processing while managing time.

[0002]

2. Description of the Related Art As OA equipment, a facsimile, a copying machine, a laser beam printer, a file device and the like are independent equipments, and are widely used in offices. Due to improvements in communication processing speed, technological advances in digital copying machines, space saving in offices, etc., a device incorporating a copying machine and a facsimile has appeared in the world.

On the other hand, the function of the combined device is, in the above-mentioned facsimile, copying machine, laser beam printer, and file device, especially the copying device may have a clock function for realizing a function such as automatic power-off. is there. An external device having a facsimile device, a computer interface, or the like has a clock function in order to realize functions such as timer transmission of the facsimile device.

As described above, in a compound device, even if the power of one of the devices is off, the other device is required to realize the above-mentioned function. At the very least two clock means are required.

In this case, of the two clock means, the reference clock means is determined and the clock processing function is executed.

[0006]

As described above, since the time of each clock means is not made to coincide with each other, the display times of the both are slightly deviated during the operation of the compound device and do not coincide with each other. The situation is such that the time is displayed.
For this reason, the operator needs time and effort to adjust the current times of both parties, and the operator's burden is heavy.

Further, when the display times of the both are slightly deviated during the operation of the multi-function apparatus and the times that do not coincide with each other are displayed, for example, when the transmission time is reserved by the time setting, which one is used as a reference. There is also a problem that the system reliability is impaired as a result of confusing whether it should be done.

The present invention has been made in order to solve the above problems, and transmits the reference time data from any one of the compound devices having the clock means to the other device of the compound device having the clock means. By automatically setting the time of the clock means of each device, it is an object of the present invention to provide a composite device capable of managing the time function processing of each clock device in a uniform time.

[0009]

A first image forming system according to the present invention comprises setting means for setting either the first clock means or the second clock means as a reference clock, and the setting means. A transmitting means for transmitting time data from one clock means set as a reference clock to the other clock means, a receiving means for receiving the time data transmitted from this transmitting means, and a time data received by this receiving means. Based on this, a correction means for automatically correcting the current time of one clock means is provided.

A second image forming system according to the present invention is
The transmitting means is configured to transmit the time data at every timing of turning on the power of one of the clock means, changing the time, updating the time, or at a predetermined interval.

[0011]

In the first aspect of the present invention, the first means is set by the setting means.
After either one of the clock means or the second clock means is set as the reference clock, the transmitting means transmits time data from one clock means set as the reference clock to the other clock means and is transmitted. When the receiving means receives the time data, the current time of one of the clock means is automatically corrected based on the time data received by the correcting means, so that the time of each clock means can be matched with each other.

In the second aspect of the invention, the transmitting means transmits the time data at any one of the timing when the power of one of the clock means is turned on, when the time is changed, when the time is updated, and at a predetermined interval. This makes it possible to match the time of each clock means with each other at the optimum timing.

[0013]

FIG. 1 is a block diagram illustrating the configuration of an image forming system showing an embodiment of the present invention.

In the figure, 1 is an image input device for converting an original into image data (hereinafter referred to as a reader unit), 2 is a printer unit (printer), which has a plurality of types of recording paper cassettes, and print commands. The image output device outputs the image data as a visible image on the recording paper. 3 is the lead
The external device is electrically connected to the chassis unit 1 and has various functions. The external device 3 has a facsimile unit 4, a file unit 5, a man-machine interface unit 6 connected to the file unit 5, a computer interface unit 7 for connecting to a computer, and information from the computer as a visible image. Formatter and reader 1 for
An image memory unit 9 for accumulating information from a computer or temporarily accumulating information sent from a computer,
A core unit 10 for controlling each function of the above 1 to 8 is provided. TM1 is a clock processing unit provided in the reader unit 1, and includes a timer IC described later. TM2 is a clock processing unit provided in the core unit 10 and includes a timer IC described later.

In the image forming system configured as described above, either the first clock means (clock processing section TM1 in this embodiment) or the second clock means (clock processing section TM2 in this embodiment) is set by the setting means. After one of them is set as the reference clock, the transmitting means (in this embodiment, the functional processing of the CPU) transmits time data from one clock means set as the reference clock to the other clock means, and the transmitted time is set. When the receiving means (CPU functional processing in this embodiment) receives the data, the correction means (CPU functional processing in this embodiment).
By automatically correcting the current time of one clock means based on the received time data, it becomes possible to make the time of each clock means coincide with each other.

The transmitting means is either one of the clock means (in the present embodiment, the clock processing unit TM1 or the clock processing unit TM).
2) When the power is turned on, the time is changed, the time is updated, and the time data is transmitted at any time of a predetermined interval, the time of each clock means is made to coincide with each other at an optimum timing. Is possible.

The functions of the respective units 1 to 8 will be described in detail below.

FIG. 2 is a sectional view showing the construction of the reader unit 1 and the printer unit 2 shown in FIG. The configuration and operation will be described below.

The originals stacked on the original feeding device 101 are sequentially conveyed one by one onto the original table glass surface 102. When the document is conveyed, the lamp 103 of the scanner unit is turned on and the scanner unit 104 moves to irradiate the document. The reflected light of the document is reflected by the mirrors 105, 106, 1
After passing through the lens 108, the light is input to the CCD image sensor unit 109 (hereinafter referred to as CCD).

FIG. 3 is a circuit block diagram showing a signal processing configuration of the reader unit 1 shown in FIG. The configuration and operation will be described below.

The image information input to the CCD 109 is photoelectrically converted here and converted into an electric signal. CCD109
The color information from the following amplifiers 110R, 110G,
At 110B, the signal is amplified according to the input signal level of the A / D converter 111. The output signal from the A / D converter 111 is
Input to the shading circuit 112, where the lamp 1
The light distribution unevenness of No. 03 and the sensitivity unevenness of the CCD are corrected. The signal from the shading circuit 112 is input to the Y signal generation / color detection circuit 113 and the external I / F switching circuit 119. The Y signal generation / color detection circuit 113 calculates the signal from the shading circuit 112 based on the following equation (1) to obtain the Y signal.

Y = 0.3R + 0.6G + 0.1B (1) Further, it has a color detection circuit for separating the R, G, B signals into seven colors and outputting the signals for the respective colors. The output signal from the Y signal generation / color detection circuit 113 is input to the scaling / repeat circuit 114. The scaling in the sub-scanning direction is performed according to the scanning speed of the scanner unit 104, and the scaling / repeat circuit 114 performs scaling in the main scanning direction. Further, the scaling / repeat circuit 114 can output a plurality of identical images. The contour / edge enhancement circuit 115 obtains edge enhancement and contour information by enhancing high frequency components of the signal from the scaling / repeat circuit. The signal from the contour / edge emphasis circuit 115 is used for patterning / thickening / masking / marker area determination / contour generation circuit 116.
It is input to the trimming circuit 117. The marker area determination / contour generation circuit 116 reads a portion of a document written with a marker pen of a designated color to generate contour information of the marker, and the next patterning / thickening / masking / trimming circuit 117 uses this contour. Thicken, mask and trim from the information. In addition, the Y signal generation / color detection circuit 11
Patterning is performed by the color detection signal from 3. An output signal from the patterning / thickening / masking / trimming circuit 117 is input to the laser driver circuit and variously processed signals are converted into signals for driving a laser. The signal from the laser driver circuit is input to the printer 2 and image formation is performed as a visible image.

Next, the external I / F switching circuit 119 for interfacing with an external device will be described.

The external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 120 when the image information is output from the reader unit 1 to the external device 3. . When the reader unit 1 inputs image information from the external device 3, the external I
The / F switching circuit 119 inputs the image information from the connector 120 to the Y signal generation / color detection circuit 113.

The above-mentioned respective image information is given by the instruction of the CPU 122, and the area generation circuit 121 generates various timing signals necessary for the image processing from the values set by the CPU 122. In addition, communication with the external device 3 is performed using the communication function built in the CPU 122. The sub-CPU 123 controls the operation unit 124 and communicates with the external device 3 by using the communication function built in the sub CPU. 125 is a calendar IC
Is an IC having a clock function, and is connected to the CPU 122. The CPU 122 can refer to or change the time that the calendar IC 125 has.

The configuration and operation of the printer 2 will be described below with reference to FIG.

The signal input to the printer unit 2 is converted into an optical signal by the exposure control unit 201 and converted into an image signal by the photosensitive member 2.
02 is irradiated. The latent image formed on the photoconductor 202 by the irradiation light is developed by the developing device 203. The transfer paper is conveyed from the transfer paper 204 or the transfer paper stacking unit 205 at the same timing as the latent image, and the developed image is transferred to the transfer unit 206. The transferred image is
After being fixed on the transfer paper by the fixing unit 207, the paper discharge unit 208
Is discharged to the outside of the device. The transfer paper output from the paper output unit 208 is discharged to each bin when the sort function is working in the sorter 220 or to the highest bin of the sorter when the sort function is not working. .

Next, a method for outputting sequentially read images on both sides of one output sheet will be described.

The output sheet fixed by the fixing section 207 is once conveyed to the sheet discharge section 208, and then the sheet conveying direction is reversed and the re-feed transfer sheet stacking section 210 is conveyed through the conveying direction switching member 209. Transport to. When the next manuscript is prepared,
The original image is read in the same manner as in the above process, but since the transfer paper is fed from the re-feed transfer paper stacking unit 210, it is possible to output two original images on the front surface and the back surface of the same sheet. .

The system configuration operation of the external device 3 shown in FIG. 1 will be described below.

The external device 3 is connected to the reader unit 1 by a cable, and the core unit in the external device 3 controls signals and controls each function. In the external device 3, there are provided an interface between the computer and a facsimile unit 4 for performing facsimile transmission / reception, a file unit 5 for converting various document information into electric signals and storing the same, and a formatter unit 8 for developing code information from the computer into image information. The information from the computer interface unit 7 and the reader unit 1 is stored,
It comprises an image memory unit 9 for temporarily storing information sent from a computer and a core unit 10 for controlling the above-mentioned functions.

The configuration and operation of the core section 10 of the external device 3 will be described below with reference to the block diagram shown in FIG.

FIG. 4 is a block diagram showing the detailed structure of the core portion 10 shown in FIG.

The connector 1001 of the core portion 10 is connected to the connector 120 of the leader portion 1 by a cable. The connector 1001 contains three types of signals, and the signal 1054 is an 8-bit multivalued video signal and a video control signal. The signal 1051 is the CPU in the reader unit 1.
122. The signal 1052 communicates with the sub CPU 123 in the reader unit 1. Signal 1052 and signal 1
A communication protocol processing 053 is performed by the communication IC 1002 and transmits communication information to the CPU 1003 via the CPU bus 1053.

The signal 1054 is a bidirectional signal line, and it is possible for the core unit 10 to receive information from the reader unit 1 and to output information from the core unit 10 to the reader unit 1. Is. The signal 1054 is the binarization circuit 1004.
It is connected to the connectors 1010 and 1013. The connector 1010 is connected to the file unit 5, and the connector 1013 is connected to the image memory unit 9.

The binarizing circuit 1004 outputs 8 of the signal 1054.
It has a function of converting a bit multilevel signal into a binary signal.
The binarization circuit 1004 has a simple binarization function for binarizing a multi-valued signal 1054 at a fixed slice level, and binarization by a variable slice level in which the slice level fluctuates from the values of pixels around the pixel of interest. It has a function and a binarization function by the error diffusion method. Output signal 105 of binarization circuit 1004
5 is input to the rotating circuit 1005 and the selector 1008.

The rotating circuit 1005 functions together with the memory 1006, and after the information output from the reader unit 1 is converted into a binary signal by the binarizing circuit 1004 via the connector 1001, the rotating circuit 1005 is controlled. Memory below 1006
The information from the reader unit 1 is stored in. Next, the CPU 10
The rotation circuit 1005 causes the memory 10
The information from 06 is rotated and read. Rotating circuit 1005
The output signal 1056 of 1 is input to the expansion circuit 1007.

The expansion circuit 1007 first converts the binary signal of the signal 1056 into a multi-valued signal. When the signal 1056 is "0", the signal 1 is output at "00H (H is a hexadecimal number)".
When 056 is "1", it is converted into "FFH". Enlargement circuit 1
007 is in the X direction and Y according to an instruction from the CPU 1003.
It is possible to set the enlargement ratio independently of the direction. The expansion method is a linear interpolation method of the first order. Enlargement circuit 1007
Output signal 1054 of the connector 1001 or 1010, 10
13 is input.

The output signal 1055 of the binarization circuit 1004 and the output signal 1056 of the rotation circuit 1005 are the selector 100.
8 and is selected by the instruction of the CPU 1003. The output signal 1058 of the selector 1008 is connected to the connector 1009, the connector 1010, and the connector 1012.

The caranda IC 1014 is a CPU 1003.
CPU 1003 is connected to the calendar IC 10
The time of 14 can be referred to or changed.

The CPU bus 1053 is the CPU 1003.
Communication IC 1002, connector 1009, connector 101
0, connector 1011, connector 1012, connector 1
013 is connected. CPU 1003 is a communication IC
Communication with the reader unit 1 is performed via 1002. Also, C
The PU 1003 communicates with the facsimile unit 4 via the connector 1009. Similarly, communication is performed with the file unit 5 via the connector 1010, the computer interface unit 7 via the connector 1011, the formatter unit 8 via the connector 1012, and the image memory unit 9 via the connector 1013.

The signal flow of the core section 10 and each section will be described below. [Processing of Core Unit 10 Based on Information from Facsimile Unit 4] A case of outputting information to the facsimile unit 4 will be described. The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. The reader unit 1 outputs image information to the connector 120 when the scanner unit 104 scans a document according to a document scan command. The reader unit 1 and the external device 3 are connected by a cable, and information from the reader unit 1 is input to the connector 1001 of the core unit 10. Further, the image information input to the connector 1001 is input to the binarization circuit 1004 through the multi-level 8-bit signal line 1054. The binarization circuit 1004 converts the 8-bit multilevel signal 1054 into a binarized signal. The binarized signal 1055 is output to the selector 1008 or the rotation circuit 100.
Input to 5. Output signal 1056 of the rotating circuit 1005
Is also input to the selector 1008, and the selector 1008
Either the signal 1055 or the signal 1056 is selected.
The signal selection is determined by the CPU 1003 communicating with the facsimile section via the data bus 1053. The binarized signal 1058 from the selector 1008 is sent to the facsimile section via the connector 1009.

Next, the case of receiving information from the facsimile section 4 will be described.

The image information from the facsimile section 4 is transmitted through the connector 1009 as a binary signal to the signal line 10.
It is transmitted to 58. The selector 1008 is the CPU 100
Signal 1058 or signal 1055 or signal 1
Output to 056. If signal 1055 is selected,
The binary signal from the facsimile unit 4 is transmitted to the rotating circuit 100.
After being rotated by 5, the data is input to the next enlarging circuit 1007. Signal 1 as an output signal from the selector 1008
When 056 is selected, it is directly input to the enlargement circuit 1007 without undergoing the rotation processing. The enlargement circuit 1007 converts the binary signal into an 8-bit multivalue and then performs an enlargement process by a linear interpolation method of the first order. The 8-bit multilevel signal from the expansion circuit 1007 is sent to the reader unit 1 via the connector 1001. The reader unit 1 inputs this signal to the external interface switching circuit 119 via the connector 120.
The external interface switching circuit 119 inputs the signal from the facsimile section 4 to the Y signal generation / color detection circuit 113. The output signal from the Y signal generation / color detection circuit 113 is processed as described above and then output to the printer unit 2 to form an image on an output sheet. [Processing of Core Unit 10 Based on Information from File Unit 5] A case of outputting information to the file unit 5 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and sends a document scan command. The reader unit 1 outputs image information to the connector 120 when the scanner unit 104 scans a document according to this command. Leader part 1
The external device 3 and the external device 3 are connected by a cable, and the reader unit 1
Information is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 passes through the multilevel 8-bit signal line 1054 and the connector 101.
0 or input to the binarization circuit 1004. When the file section 5 compresses and filing 8-bit multivalued information, the information of the signal line 1054 is sent to the file section 5 via the connector 1010. When the file unit 5 compresses binary information for filing, the binarization circuit 1004 performs binarization. The binarization process and the rotation process are the same as in the case of the facsimile unit 4 described above, and therefore description thereof will be omitted.

Binary signal 105 from selector 1008
8 is sent to the file unit 5 via the connector 1010.

Next, the case of receiving information from the file section 5 will be described. The image information from the file unit 5 is transmitted via the connector 1010 to the signal line 1054 in the case of an 8-bit multilevel signal and to the signal line 1058 in the case of a binary signal. The signal line 1054 is sent to the reader unit 1 via the connector 1001. The signal on the signal line 1058 is input to the selector 1008. The selector 1008 sets the signal line 1058 to the signal 1055 or the signal 1056 according to an instruction from the CPU 1003.
Output to. When the signal 1055 is selected, it is rotated and then input to the next enlarging circuit 1007. When the signal 1056 is selected as the output signal from the selector 1008, it is directly input to the enlarging circuit 1007 without undergoing the rotation processing. The 8-bit multilevel signal from the expansion circuit 1007 is sent to the reader unit 1 via the connector 1001.
The information of the file portion sent to the reader unit 1 is output to the printer unit 2 and image formation is performed on the output paper, as in the above-described facsimile unit 4. [Processing of Core Unit 10 Based on Information from Computer Interface Unit 7] The computer interface unit 7
It interfaces with a computer connected to the external device 3. The computer interface unit 7 is an SCS.
I, RS232C, and a plurality of interfaces for communicating with Centronics system. The computer interface unit 7 has three types of interfaces as described above, and information from each interface is stored in the connector 10
11 to the CPU 1003 via the data bus 1053. The CPU 1003 performs various controls based on the contents sent. [Processing of Core Unit 10 Based on Information from Formatter Unit 8] The formatter unit 8 has a function of expanding command data such as a document file sent from the computer interface unit 7 into image data. C
When the PU 1003 determines that the data sent from the computer interface unit 7 via the data bus 1053 is data regarding the formatter unit 8, the PU 1003 transfers the data to the formatter unit 8 via the connector 1012.
The formatter unit 8 develops the transferred data in the memory as a meaningful image such as characters and figures. Next, a procedure for receiving information from the formatter unit 8 and forming an image on an output sheet will be described.

The image information from the formatter unit 8 is transmitted as a binarized signal to the signal line 1058 via the connector 1012. The signal on the signal line 1085 is input to the selector 1008. The selector 1008 is C
The signal 1058 is converted to the signal 1055 according to the instruction from the PU 1003.
Or output to signal 1056. When the signal 1055 is selected, it is rotated and then input to the next enlarging circuit 1007. When the signal 1056 is selected as the output signal from the selector 1008, it is directly input to the enlarging circuit 1007 without undergoing the rotation processing. The 8-bit multilevel signal from the expansion circuit 1007 is sent to the reader unit 1 via the connector 1001. The information of the formatter unit 8 sent to the reader unit 1 is output to the printer unit 2 and image formation is performed on the output paper as in the above-described facsimile unit 4. [Processing of Core Unit 10 Based on Information from Image Memory Unit 9] A case of outputting information to the image memory unit 9 will be described. The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. The reader unit 1 outputs image information to the connector 120 when the scanner unit 104 scans a document according to this command. The reader unit 1 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 is multivalued 8
It is sent to the image memory unit 9 via the bit signal line 1054 and the connector 1013. The image information stored in the image memory unit 9 is sent to the CPU 1003 via the data bus of the connector 1013. CPU10
03 transfers the data sent from the image memory unit 9 to the computer interface unit 7 described above.
The three types of interfaces mentioned above, namely SCSI,
Transfer to the computer with a desired interface of RS232C and Centronics.

Next, a case of receiving information from the image memory unit 9 will be described.

First, image information is sent from the computer to the core unit 10 via the computer interface unit 7. When the CPU 1003 of the core unit 10 determines that the data sent from the computer interface unit 7 via the data bus 1053 is the data related to the image memory unit 9, the CPU 1003 transfers the data to the image memory unit 9 via the connector 1013. Next, the image memory unit transmits the 8-bit multilevel signal 1054 via the connector 1013. The signal line 1054 is sent to the reader unit 1 via the connector 1001. The information in the image memory unit 9 sent to the reader unit 1 is output to the printer unit 2 and the image is formed on the output paper, similarly to the facsimile unit 4 described above.

The configuration of the facsimile section 4 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 5 is a block diagram for explaining the detailed structure of the facsimile section 4 shown in FIG.

The facsimile section 4 is connected to the core section 10 by the connector 400 and exchanges various signals. The signal 451 is a bidirectional binarized image signal, and is stored in the buffer 4
01 separates the bidirectional signal 451 into an output signal 452 from the facsimile unit 4 and an input signal 453 to the facsimile unit 4. The signal 452 and the signal 453 are input to the selector 402.
Is input to the selector 402, and the selector 402 selects it according to an instruction from the CPU 412. When the binary information from the core unit 10 is stored in any of the memories A405 to D408, the selector 402 selects the signal 453. Also,
When transferring data from one memory (one of the memories A405 to D408) to another memory, the selector 402 selects the signal 452. The output signal 453 of the selector 402 is input to the scaling circuit 403 and undergoes scaling processing. When the reading resolution 400 DPI of the reader unit 1 is transmitted by facsimile, the scaling circuit 403 converts the resolution according to the facsimile on the receiving side.
The output signal 454 of the scaling circuit 403 is stored in any one of the memory A405, the memory B406, the memory C407, and the memory D408 under the control of the memory controller, or in a cascade connection of two sets of memories. The memory controller 404 has a mode for exchanging data with the memory A 405, the memory B 406, the memory C 407, the memory D 408, and the CPU bus 462 according to an instruction from the CPU 412, and a CODEC 41 having an encoding / decoding function.
In the mode for exchanging data with the CODEC bus 463 of No. 1 and the binary video input data 454 under the control of the timing generation circuit 409, the memory A 405, the memory B 40
6. It has four functions: a mode for storing in any one of the memory C407 and the memory D408, and a mode for outputting the memory contents from any of the memory A405, the memory B406, the memory C407, and the memory D408 to the read signal 452. Memory A405, Memory B406, Memory C40
7. The memory D408 has a capacity of 2 Mbytes, respectively, and stores an image corresponding to A4 at a resolution of 400 DPI. The timing generation circuit 409 is connected to the connector 400 via the signal line 459, and is activated by the control signals HSYNC, HEN, VSYNC, VEN from the core unit 10 to generate signals for achieving the following two functions. . First, the image signal from the core unit 10 is stored in the memory A.
405, memory B406, memory C407, memory D4
08, a function of storing in any one memory or two memories, two are memory A405, memory B406,
This is a function of transmitting from one of the memory C407 and the memory D408 to the read signal line 452. The dual port memory 410 is connected to the CPU 1003 of the core unit 10 via the signal line 461 and the CPU 412 of the facsimile unit 4 via the signal line 462. Each CPU exchanges commands via the dual port memory 410. SCSI controller 413
Interface with the hard disk connected to the facsimile section 4 shown in FIG. It stores the data when sending and receiving a facsimile.
The CODEC 411 is a memory A405 and a memory B40.
6, the image information stored in any one of the memory C407 and the memory D408 is read out, and MH, MR, and MM are read.
After encoding by the desired method of the R method, the memory A4
05, memory B406, memory C407, memory D40
8 is stored as encoded information. Further, the encoded information stored in the memory A405, the memory B406, the memory C407, and the memory D408 is read out, and M
After performing the decoding by the desired H, MR, or MMR method, the memory A405, the memory B406, and the memory C40
7. Decryption information, that is, image information is stored in one of the memories D408. MODEM 414 is CO
A function of modulating the coded information from the hard disk connected to the DEC 411 or the SCSI controller 413 in order to transmit it on the telephone line, and demodulating the information sent from the NCU 415 to convert it into coded information, COD
The encoded information is transferred to the hard disk connected to the EC 411 or the SCSI controller 413. NC
The U 415 exchanges information with an exchange installed directly at a telephone station or the like by being directly connected to a telephone line according to a predetermined procedure.

An example of the facsimile transmission process will be described below.

The binarized image signal from the reader unit 1 is input from the connector 400 and the signal line 451 to the buffer 401. The buffer 401 is the CPU 412
The signal 451 is output to the signal line 453 according to the setting. The signal 453 is input to the selector 402 and then reaches the scaling circuit 403. The scaling circuit 403 includes a reader unit 1.
The resolution of 400 DPI is converted to the resolution of facsimile transmission. The output signal 454 from the scaling circuit 403 is stored in the memory A 405 by the memory controller 404. The timing to be stored in the memory A 405 is generated by the timing generation circuit 409 according to the timing signal 459 from the reader unit 1. The CPU 412 uses the memory A 405 and the memory B 40 of the memory controller 404.
6 is connected to the bus line 463 of the CODEC 411.
The CODEC 411 reads the image information from the memory A 405, encodes it by the MR method, and writes the encoded information in the memory B 406. CO image information of A4 size
When the DEC 411 encodes, the CPU 412 transfers the memory B 406 of the memory controller 404 to the CPU bus 46.
Connect to 2. The CPU 412 sequentially reads the encoded information from the memory B406 and transfers it to the MODEM 414. The MODEM 414 modulates the encoded information and transmits it as facsimile information on the telephone line via the NCU 415.

Next, an example of the facsimile receiving process will be described.

The information sent from the telephone line is NCU.
It is input to the facsimile unit 4 in a predetermined procedure by the NCU 415. Information from NCU 415
It enters the MODEMM 414 and is demodulated. CPU412
Stores information from the MODEM 414 in the memory C407 via the CPU bus 462. When the information of one screen is stored in the memory C407, the CPU 412 controls the memory controller 404 to cause the memory C40 to operate.
7 data line 457 to CODEC 411 line 4
Connect to 63. The CODEC 411 is a memory C407.
The coded information is read out sequentially and decoded, that is, stored in the memory D408 as image information. CPU412
Communicates with the CPU 1003 of the core unit 10 via the dual port memory 410 and makes settings for printing out an image from the memory D 408 through the core unit 10 to the printer unit 2. When the setting is completed, the CPU 412
The timing generation circuit 409 is activated, and the signal line 4
A predetermined timing signal from 60 is sent to the memory controller 4
Output to 04. The memory controller 404 synchronizes with the signal from the timing generation circuit 409 and stores the memory D40.
The image information is read from No. 8 and transmitted to the signal line 452. The signal 452 is input to the buffer 401 and output to the connector 400 via the signal line 451. The process up to the output from the connector 400 to the printer unit 2 has been described in the core unit 10 and will be omitted.

The detailed configuration and operation of the file unit 5 will be described below with reference to the block diagram shown in FIG.

FIG. 6 is a block diagram for explaining the detailed structure of the file unit 5 shown in FIG.

The file section 5 is connected to the core section 10 by the connector 500 and exchanges various signals. Signal 55
Reference numeral 1 is a bidirectional 8-bit multivalued image signal, which is input to the buffer 501. The buffer 501 separates the bidirectional signal 551 into a multilevel output signal 556 from the file unit 5 and a multilevel input signal 555 to the file unit 5. The multi-valued input signal 555 is input to the compression circuit 503, where multi-valued image information is converted into binary compression information and output to the selector 505. The signal 552 is a bidirectional binarized image signal and is connected to the buffer 502. The buffer 502 is
The bidirectional binary signal 552 is separated into a binary output signal 558 from the file unit 5 and a binary input signal 557 to the file unit 5. The binary input signal 557 is input to the selector 505. The selector 505 outputs the output signal 561 from the compression circuit 503 and the buffer 50 according to an instruction from the CPU 516.
The signal is selected from three types of signals, that is, the output signal 557 from the buffer 2 and the output signal 562 from the buffer 512, and is input to the memory controller 510. Output signal 563 of selector 505
Is also input to the selector 511. 8 from the core part 10
Compressed information obtained by compressing bit multi-valued information is stored in the memory A5.
06 to the memory D509, the selector 505 selects the signal 561. When the binary information is stored in the memory, the selector 505 outputs the signal 55
Select 7. When storing the information from the man-machine interface unit 6 shown in FIG. 1 in the memory, the selector 505 selects the signal 562. The output signal 563 of the selector 505 is stored under the control of the memory controller 510 in any one of the memories A506, B507, C508, and D509, or in a cascade connection of two sets of memories. The memory controller 510 is the CPU 51
According to the instruction of 6, the memory A506, B507, C50
8, a mode for exchanging data between the D509 and the CPU bus 560, and a CODEC 517 for encoding / decoding
Mode for exchanging data with the CODEC bus 570, and a signal 563 under the control of the timing generation circuit 514.
To store in any of the memories A506, B507, C508, and D509, and memory A506, B507,
It has four functions of a mode of outputting the memory contents from either C508 or D509 to the read signal line 558. Memories A506, B507, C508, D509
Has a memory capacity of 2 Mbytes each and 400D
An image corresponding to A4 is stored with the resolution of PI. The timing generation circuit 514 is connected to the connector 500 by the signal line 553, and the control signal HSYN from the core unit 10 is supplied.
It is activated by C, HEN, VSYNC, VEN and generates signals to achieve the following two functions. One is to store information from the core unit 10 in the memories A506 and B50.
7, C508, D509 any one memory, or the function of storing in two memories, two are the memory A50
6, the function of transmitting from any one of B507, C508, and D509 to the read signal line 558. The connector 513 is the man-machine interface unit 6 shown in FIG.
To exchange signals. The image information is stored in the buffer 512.
In addition, the command is connected to the communication circuit 518. Signal 56
Reference numeral 9 is a bidirectional image signal, and the buffer 512 outputs the signal information to the signal line 562 when receiving the image information from the man-machine interface unit 6. When the image information is output from the file unit 5 to the man-machine interface unit 6, the information on the signal line 568 is stored in the buffer 5.
12, the dual port memory 515 transferred via the connector 513, the core unit 1 via the signal line 554.
The CPU 516 of the file unit 5 is connected via the CPU 1003 of 0 and the signal line 560. Each CPU
1003 and 516 exchange commands via the dual port memory 515. The SCSI controller 519 interfaces with the external storage device 520 connected to the file unit 5 shown in FIG. The external recording device 520 is specifically composed of a magneto-optical disk, and stores data such as image information. CODEC 51
7 is a memory A506, B507, C508, D509
Read the image information stored in one of the
After encoding by a desired method of the MH, MR and MMR methods, the memories A506, B507, C508 and D509 are used.
Is stored as encoded information. In addition, after the encoded information stored in the memories A506, B507, C508, and D509 is read and decoded by a desired method of the MH, MR, and MMR methods, the memories A506 and B5 are read.
07, C508, or D509 is stored as decryption information, that is, image information.

An example of processing for accumulating file information in the external storage device 520 will be described below.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 500 and the signal line 551 to the buffer 501. The buffer 501 is C
The signal 551 is sent to the signal line 555 by setting the PU 516.
Output to. The signal 555 is input to the compression circuit 503, where it is converted into binary compression information 561. The compressed information 561 reaches the memory controller 510 after being input to the selector 505. The signal 563 is input to the memory controller 510 and also the selector 51.
It is also input to the man-machine interface unit 6 via the 1, buffer 512 and the connector 513. The memory controller 510 uses the signal 553 from the core unit 10 to generate the timing signal 559 in the timing generation circuit 514, and according to this signal, outputs the compressed signal 563 to the memory A 506.
Remember. The CPU 516 is the memory controller 51.
0 memory A506 and memory B507 are CODEC
517 to the bus line 570. CODEC 51
7 reads the compressed information from the memory A506,
Encoding is performed by the MR method and encoded information is stored in the memory B507.
Write in. When CODEC 517 finishes encoding,
The CPU 516 is the memory B of the memory controller 510.
507 is connected to the CPU bus 560. The CPU 516 sequentially reads the encoded information from the memory B507,
Transfer to the SCSI controller 519. The SCSI controller 519 stores the encoded information 572 in the external storage device 520.

Next, an example of a print process for extracting information from the external storage device 520 and outputting it from the printer unit 2 will be described.

Upon receiving an information retrieval / printing instruction from the man-machine interface unit 6, the CPU 516 executes S
External storage device 520 via CSI controller 519
And receives the encoded information from and transfers the encoded information to the memory C508. At this time, the memory controller 510 instructs the CPU bus 560 to instruct by the CPU 516.
Is connected to the bus 566 of the memory C508. Memory C5
When the transfer of the encoded information to 08 is completed, the CPU 516
By controlling the memory controller 510,
The memory C508 and the memory D509 are connected to the bus 570 of the CODEC 517. CODEC 517 is a memory C
The encoded information is read from 508 and sequentially decoded, and then transferred to the memory D509. The CPU 516 is the CPU 1003 of the core unit 10 via the dual port memory 515.
And the setting for printing out an image from the memory D509 through the core unit 10 to the printer unit 2 is performed. When the setting is completed, the CPU 516 activates the timing generation circuit 514 and outputs a predetermined timing signal from the signal line 559 to the memory controller 510. The memory controller 510 reads the decoding information from the memory D509 in synchronization with the signal from the timing generation circuit 514 and transmits it to the signal line 558. The signal line 558 is input to the expansion circuit 504, and the decoded information is expanded and converted into image information. Expansion circuit 504
Output signal 556 is input to the buffer 501 and output to the connector 500 via the signal line 551. The process up to the output from the connector 500 to the printer unit 2 has been described in the core unit 10 and will be omitted.

The configuration and display processing operation of the man-machine interface unit 6 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 7 is a block diagram for explaining the detailed structure of the man-machine interface unit 6 shown in FIG. Hereinafter, an example of a process of receiving image information from the file unit 5 and displaying it on the display will be described.

The connector 600 is connected to the connector 513 of the file section 5 by a cable. CPU 615 is C
The communication circuit 610 communicates with the CPU 516 of the file unit via the PU bus 660 to set the image input mode.
The bidirectional image signal 651 from the connector 600 is separated into a unidirectional signal by the buffer 601. File part 5
The signal from is a one-way signal 652 in the buffer 601 and is input to the reduction circuit 602. Reduction circuit 602
Is an FLC display (high dielectric display) 60
The input image signal is reduced according to the display size of 8. The output signal 654 of the reduction circuit 602 is input to the dual port memory 605 through the buffer 603. Writing to the dual port memory 605 is performed by the timing generation circuit 60.
4 signal 658. The timing generation circuit 604 uses the timing signal 65 from the file unit 5.
It is activated by 7. When the image information for one line is written in the dual port memory 605, the CPU 615 receives the signal 666 from the timing generation circuit 604.
A DMA (direct memory access) request to the. C
The PU 615 uses a built-in DMAC (Direct Memory Access Controller) to control the dual port memory 6
The image information is transferred from 05 to the DRAM (dynamic random access memory) 612 via the CPU bus 660. By repeating the above operation, the image information of one screen is stored in the DRAM 612. FLC display 6
08 is connected to the connector 607 by a cable 662 and inputs an image request signal (hereinafter, FHSYNC) 665 to the timing generation circuit 609. Timing generation circuit 609
Upon receiving FHSYNC 665, outputs a DMA request signal 667 to CPU 615. CPU 615 is D
When the MA request signal 667 is received, the DMAC incorporated in the CPU 615 is activated, and the line address displayed on the FLC display 608 from the DRAM 612 and the image information for one line are transferred to the FIFO 60 via the CPU bus 660.
DMA transfer to 6. Next, the timing generation circuit 609
Outputs a timing signal 663 and reads out image information for one line from the FIFO 606 and transfers it to the FLC display 608 via the connector 607. The FLC display 608 determines the image display position from the line address to be displayed and displays one line of image information on the FLC display. By repeating the above operation, the image information of one screen is displayed on the entire FLC.

An example of the transfer process for transferring the image information in the man-machine interface unit 6 to the file unit 5 will be described below.

The CPU 615 communicates with the CPU 516 of the file section 5 via the communication circuit 610 to set the image output mode. The image information of the man-machine interface unit 6 is stored in the DRAM 612, and the CPU 615
Is the DMA request signal 6 from the timing generation circuit 604.
When 66 is received, the image information for one line is transferred from the DRAM 612 to the dual port memory 605. Next, the read timing signal 658 from the timing generation circuit 604 reads the image information 656 from the dual port memory 605. Dual port memory 605
Output signal 656 from buffer 603, buffer 6
The image signal 651 is output to the connector 600 via 01. The operation in the file unit 5 has been described above, and will be omitted.

A keyboard interface 618 and a mouse interface 616 communicate with a keyboard and a pointing device (mouse), and give an operation instruction to the man-machine interface unit 6.

The configuration and operation of the computer interface section 7 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 8 is a block diagram for explaining the detailed structure of the computer interface unit 7 shown in FIG.

The connector A (connector) 700 and the connector B (connector) 701 are SCSI interface connectors. The connector C702 is a Centronics interface connector. Connector D70
Reference numeral 3 is an RS232C interface connector.
The connector E707 is a connector for connecting to the core unit 10. The SCSI interface 704 has two connectors 700 and 701. When connecting a device having a plurality of SCSI interfaces, the connector 7
This is performed by making a cascade connection using 00 and 701. When the external device 3 and the computer are connected one-to-one, the connector 700 and the computer are connected with a cable, and the connector 701 is connected with a terminator, or the connector 701 and the computer are connected with a cable, and the connector 700 is connected. Connect the terminator to. Information input from the connector 700 or the connector 701 is
SCSI interface 70 via signal line 751
4 is input. The SCSI interface 704 is S
After performing the procedure according to the CSI protocol, the data is transferred to the connector E (connector) 70 via the signal line 754.
Output to 7. The connector 707 is the CPU of the core unit 10.
The CPU 1 of the core unit 10 connected to the bus 1053
003 receives the information input to the SCSI interface connectors (connectors 700 and 701) from the CPU bus 1053. Data from the CPU 1003 of the core unit 10 is transferred to the SCSI connector (connectors 700 and 701).
When outputting to, the procedure is the reverse of the above.
Centronics interface 705 is connector C
It is connected to the (connector) 702 and input to the Centronics interface 705 via the signal line 752. The Centronics interface 705 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E (connector) 707 via the signal line 754. The connector 707 is the CPU bus 10 of the core unit 10.
The CPU 1003 of the core unit 10 connected to the CPU 53.
Receives the information input to the Centronics interface connector (connector 702) from the CPU bus 1053.

The RS232C interface is connected to the connector D (connector) 703 and input to the RS232C interface 706 via the signal line 753. The RS232C interface 706 receives the data according to the procedure of the determined protocol and outputs the data to the connector E (connector) 707 via the signal line 754. The connector 707 is the CPU bus 105 of the core unit 10.
3 and the CPU 1003 of the core unit 10
The information input to the RS232C interface connector (connector 703) is received from the CPU bus 1053. The data from the CPU 1003 of the core unit 10 is RS2
When outputting to the 32C interface connector (connector 703), the procedure is reversed.

The configuration and operation of the formatter unit 8 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 9 is a block diagram for explaining the detailed structure of the formatter unit 8 shown in FIG.

Computer interface section 7 described above
Is determined by the core unit 10, and if the data is related to the formatter unit 8, the CP of the core unit 10
The U 1003 transfers data from the computer to the dual port memory 803 via the connector 1012 of the core unit 10 and the connector 800 of the formatter unit 9. The CPU 809 of the formatter unit 8 receives the code data sent from the computer via the dual port memory 803. The CPU 809 sequentially develops this code data into image data, and through the memory controller 808, the memory A 806 or the memory B 80.
Transfer the image data to 7. The memory A806 and the memory B807 each have a memory capacity of 2 Mbytes,
One memory (memory A806 and memory B807)
With the resolution of 400 DPI, it is possible to support up to A4 paper size. In the case of supporting up to A3 size paper at a resolution of 400 DPI, the memory A806 and the memory B807 are connected in cascade to develop image data. The memory control described above is performed by the memory controller 808 according to an instruction from the CPU 809. Also, when you need to rotate characters or figures when expanding image data,
After being rotated by the rotation circuit 804, it is transferred to the memory A 806 or the memory B 807. When the expansion of the image data in the memory A806 or the memory B807 is completed, the CP
U 809 controls the memory controller 808 to control the data bus line 858 of the memory A 806 or the memory B 80.
7 data bus line 859 to memory controller 80
8 output lines 855. Next, the CPU 809
Is the C of the core unit 10 via the dual port memory 803.
It communicates with the PU 1003 and sets a mode in which image information is output from the memory A 806 or the memory B 807.
The CPU 1003 of the core unit 10 sets the print output mode in the CPU 122 using the communication function built in the CPU 122 of the reader unit 1 via the communication circuit 1002 in the core unit 10. The CPU 1003 of the core unit 10 activates the timing generation circuit 802 via the connector 1013 and the connector 800 of the formatter unit 8. The timing generation circuit 802 generates a timing signal for reading image information from the memory A 806 or the memory B 807 to the memory controller 808 according to the signal from the core unit 10. Memory A806 or memory B807
The image information from is input to the scaling circuit 801 through signal lines 858 and 855. The scaling circuit 801
After scaling according to an instruction from the CPU 809, the data is transferred to the core unit 10 via the signal line 851 and the connector 800. Regarding the output of the printer unit 2 from the core unit 10,
Since it has been described with respect to the core portion 10, it will be omitted.

The configuration and operation of the image memory unit 9 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 10 is a block diagram for explaining the detailed structure of the image memory unit 9 shown in FIG.

The image memory unit 9 is connected to the core unit 10 by the connector 900 and exchanges various signals. The signal 951 is a bidirectional 8-bit multivalued image signal and is input to the buffer 901. The buffer 901 outputs the bidirectional signal 951 to the multilevel output signal 95 from the image memory unit 9.
5 and a multi-valued input signal 954 to the image memory unit 9. The multi-valued input signal 954 is supplied to the memory controller 90.
5 is stored in the memory 904 under the control of 5. The memory controller 905 is instructed by the CPU 906 to execute the memory 9 operation.
04 and the CPU bus 957, and a signal 95 under the control of the timing generation circuit 902.
4 is stored in the memory 904, and a mode in which the memory contents are read from the memory 904 and output to the signal line 955 is provided. The memory 904 has a storage capacity of 32 Mbytes, a resolution of 400 DPI and 25
An image corresponding to A3 is stored with 6 gradations. The timing generation circuit 902 is connected to the connector 900 by a signal line 952, and controls signals HSYNC and H from the core unit 10.
It is activated by EN, VSYNC and VEN and generates signals to achieve the following two functions. One is a function of storing the information from the core unit 10 in the memory 904, and the other is a function of transmitting the information to the signal line 955 read from the memory 904. The dual port memory 903 includes a CPU 1003 of the core unit 10 via a signal line 953 and a CPU 9 of the image memory unit 9 via a signal line 957.
06 is connected. Each CPU 1003, 906
Exchange commands via the dual port memory 903. Hereinafter, an example of a transfer process of storing image information in the image memory unit 9 and transferring this information will be described.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 900, passes through the signal line 951, and is input to the buffer 901. The buffer 901 is
The signal 951 is sent to the signal line 95 by the setting of the CPU 906.
Output to 4. The memory controller 905 is the core unit 1
The signal 952 from 0 causes the timing generation circuit 902
The timing signal 956 is generated in accordance with the above, and the signal 954 is stored in the memory 904 in accordance with this signal. CPU 906
The memory 904 of the memory controller 905 is connected to the CPU bus 957. The CPU 906 sequentially reads the image information from the memory 904, and the dual port memory 9
03. The CPU 1003 of the core unit 10 reads the image information of the dual port memory 903 of the image memory unit 9 via the signal line 953 and the connector 900, and transfers this information to the computer interface unit 7. The transfer of information to the computer interface unit 7 has been described above, and thus the description thereof will be omitted. Hereinafter, an example of an image output process for outputting the image information sent from the computer from the printer unit 2 will be described.

The image information sent from the computer is sent to the core unit 10 via the computer interface unit 7. The CPU 1003 of the core unit 10 is C
Image information is transferred to the dual port memory 903 of the image memory unit 9 via the PU bus 1053 and the connector 1013. At this time, the CPU 906 controls the memory controller 905 to transfer the CPU bus 957 to the memory 9.
04 bus. The CPU 906 transfers the image information from the dual port memory 903 to the memory 904 via the memory controller 905. Memory 904
After transferring the image information to the CPU 906, the CPU 906 controls the memory controller 905 to connect the data line of the memory 904 to the signal 955. The CPU 906 is a CPU of the core unit 10 via the dual port memory 903.
Communication with 1003 is performed, and settings for printing out an image from the memory 904 through the core unit 10 to the printer unit 2 are performed. When the setting is completed, the CPU 906 activates the timing generation circuit 902 and outputs a predetermined timing signal from the signal line 956 to the memory controller 905. The memory controller 905 reads the image information from the memory 904 in synchronization with the signal from the timing generation circuit 902 and transmits it to the signal line 955. The signal line 955 is input to the buffer 901 and output to the connector 900 via the signal line 951. Connector 90
Since the process from 0 to the output to the printer unit 2 has been described in the core unit 10, the description thereof will be omitted.

In the above configuration, a computer or workstation connected to the operation unit 124 of the reader unit 1, the keyboard 619 of the file unit 5, the connector A700 to the connector D703 of the computer formatter unit 7 as the operation means for inputting various settings. I have a 790 keyboard,
As described in each item, each operation unit is connected to the CPU 1003 of the core unit 10 by the communication unit.

The CPU 1003 of the core unit 10 constantly communicates with each connected function. When an operation setting is input by any operation means, a corresponding command code is transmitted to the CPU 1003. , The sequence program is executed after command interpretation, and an operation command is issued to the function requested to operate. At this time, if the priority setting and the operation prohibition setting are registered in the sequence program, it is possible to make the user-friendly operation according to the purpose of use of the user.

When the image data is received from the external device by using the third function, the condition set by the external device is set in the communication protocol in advance and is sent out. Training in Modem 4
The CPU 412 interprets various settings via the CPU 14 and the CPU of the core unit 10 through the dual port memory 410.
By sending a command to 1003, it is also possible to remotely operate the function of this system. [First Time Adjustment Processing] The automatic time adjustment processing operation of the CPU 122 and the calendar IC 125 of the reader unit 1 and the CPU 1003 and the calendar IC 1014 of the core unit 10 will be described below with reference to FIGS. 11 and 12. In this embodiment, it is previously determined that the reader unit 1 is a device having a reference clock (hereinafter, referred to as a master device) by using a setting device such as a switch of the master device. That is,
The calendar IC 125 becomes the master calendar IC, and the time held by the IC becomes the reference. Further, the CPU 122 serves as a master CPU and manages time.

On the other hand, the core unit is a slave device in this embodiment, the CPU 1014 is a slave CPU, and the master C
The time held by the calendar IC 1014 which is the slave calendar IC is rewritten at the reference time transmitted from the PU. When the master device is powered on, the master C
The PU activates the flowchart shown in FIG. 11, and the slave CPU has an interrupt and periodically operates according to the flowchart shown in FIG.

FIG. 11 is a flow chart showing an example of a time data transmission processing procedure from the reader unit 1 in the multifunction apparatus according to the present invention. In addition, (1) to (10) indicate each step.

First, it is judged whether or not the power of the slave device is turned on (1), and the slave CPU (CPU 10
Send a predetermined command to (03) (1). When the slave device receives the command when the slave device is powered on, the slave device transmits a command notifying that the power is powered on to the master CPU. Next, it is judged whether the power of the core unit 10 is turned on (2) by the command transmitted from the master CPU,
When it is determined that the power is not turned on (NO), the process proceeds to step (3), the fact that the power of the slave device is not turned on is recorded in the master CPU, and the process is ended.

On the other hand, if the judgment in step (2) is YES, a command for rewriting at the reference time is transmitted to the slave CPU (4). When the slave CPU receives this command, the slave calendar IC (calendar IC101
It is checked whether the time can be written in 4), and a command indicating rewritable or non-rewritable is transmitted to the master CPU.

The master CPU analyzes the command transmitted from the slave calendar IC (calendar IC 1014) indicating rewritable or non-rewritable, and the slave CPU
It is judged whether it is possible to rewrite at the reference time (5),
If NO (not rewritable), the rewritable is recorded in the master CPU (6), and the process ends.

On the other hand, when the rewritable command is received in the judgment of step (5), the time data of the master calendar IC is read into the master CPU (7), and the read time is transmitted to the slave CPU (8). . The slave CPU receives this time data, rewrites the contents of the slave calendar IC with the received contents, and after the rewriting is completed, the slave CPU sends a command notifying the master CPU that the rewriting is completed. Next, the master CPU determines whether or not a command indicating completion of rewriting from the slave CPU has been received (9), and in the case of NO (when the completion of rewriting is not received), it is confirmed that the master CPU has not rewritten. Record (10) and end the process. Meanwhile, step
If the determination in (9) is YES, the time data transmission process ends.

FIG. 12 is a flow chart showing an example of the time data reception processing procedure of the core unit 10 in the multifunction apparatus according to the present invention. In addition, (1) to (10) indicate each step.

First, it is judged whether or not the command for checking the power-on of the slave device is transmitted from the master device (the above command is received) (1). If NO, the process is terminated and YES. Then, the command notifying that the power is turned on (ON state) is sent to the master CPU (2). Next, it is judged whether or not a command to rewrite at the reference time is received from the master CPU.
(3) If NO, terminate the process, and if YES, investigate whether or not the time can be written in the slave calendar IC (calendar IC 1014) (4), and can write (rewritable)
It is determined whether or not (5), and if NO, the calendar IC101
Send 4 to the master CPU that it cannot be rewritten.
(6), the process ends.

On the other hand, if the determination in step (5) is YES, the fact that the calendar IC 1014 is rewritable is transmitted to the master CPU (7), the reference time is received from the master CPU (8), and the slave CPU The contents of the calendar IC are rewritten to the contents of the received time data (9), a command indicating the completion of rewriting is transmitted to the master CPU (10), and the time data reception process ends. [Second time adjustment processing] In the first time adjustment processing,
Although the example in which the power supply of the master device is turned on is the timing for starting the time adjustment process has been described, the time may be set when the user sets the time of the reference clock. The master device and the slave device are shown in FIG.
The description is omitted because it complies with 2. [Third time adjustment process] In the first time adjustment process,
An example in which the timing of starting the time adjustment process is set to be the time when the master device is turned on has been described, but a device having a reference clock may periodically execute the time adjustment process. The master device and the slave device are shown in FIG.
The description is omitted because it is based on FIG. [Fourth time adjustment process] In the first time adjustment process,
The master device is the reader unit 1, and the slave device is the core unit 10.
Although the time adjustment processing in the case of is explained, the master device may be the core unit 10 and the slave device may be the reader unit 1. The core unit 10 is set as the master device by a switch or the like. It shall be configured as possible. In this case, substantially the same processing is executed except that the transmission subject and the reception subject of the time data shown in FIGS. The time when the master device is turned on is the timing for starting the time adjustment process. [Fifth time adjustment process] In the fourth time adjustment process,
Although the example in which the power supply of the master device is turned on is the timing for starting the time adjustment process has been described, the time may be set when the user sets the time of the reference clock. The master device and the slave device are shown in FIG.
The description is omitted because it complies with 2. [Sixth time adjustment process] In the fourth time adjustment process,
An example in which the timing of starting the time adjustment process is set to be the time when the master device is turned on has been described, but a device having a reference clock may periodically execute the time adjustment process. The master device and the slave device are shown in FIG.
The description is omitted because it is based on FIG.

[0095]

As described above, according to the first aspect of the invention, after the setting means sets either the first clock means or the second clock means as the reference timepiece, the transmitting means becomes the reference timepiece. When one clock means set as a clock transmits time data to the other clock means, and the received time data is received by the receiving means, the current time of one clock means is based on the time data received by the correcting means. Is configured to be automatically corrected, it is possible to match each time of each clock means with each other.

According to the second aspect of the invention, the transmitting means transmits the time data at every timing of turning on the power of any one of the clock means, changing the time, updating the time, or at a predetermined interval. With this configuration, the times of the clock means can be matched with each other at the optimum timing.

Therefore, the burden on the time adjusting operation of each timepiece means by the operator is reduced as in the prior art, the time shift state of each timepiece means is eliminated, and the anxiety of the operator due to the inconsistency of the time display and the like can be eliminated. Exerts the excellent effect of.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image forming system according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a configuration of a reader unit and a printer unit shown in FIG.

3 is a circuit block diagram showing a signal processing configuration of a reader unit shown in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a core section shown in FIG.

5 is a block diagram illustrating a detailed configuration of a facsimile unit illustrated in FIG.

6 is a block diagram illustrating a detailed configuration of a file unit illustrated in FIG.

7 is a block diagram illustrating a detailed configuration of a man-machine interface unit illustrated in FIG.

8 is a block diagram illustrating a detailed configuration of a computer interface unit illustrated in FIG.

9 is a block diagram illustrating a detailed configuration of a formatter unit shown in FIG.

FIG. 10 is a block diagram illustrating a detailed configuration of an image memory unit illustrated in FIG.

FIG. 11 is a flowchart showing an example of a time data transmission processing procedure from the reader unit in the multifunction apparatus according to the present invention.

FIG. 12 is a flowchart showing an example of a time data reception processing procedure of the core unit in the multifunction apparatus according to the present invention.

[Explanation of symbols]

 1 reader unit 2 printer unit 3 external device 4 facsimile unit 5 file unit 6 man-machine interface unit 7 computer interface unit 8 formatter unit 9 image memory unit 10 core unit 608 display 619 keyboard 790 workstation TM1 clock processing unit TM2 clock processing Department

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Koichi Unno 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hirohiko Ito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (2)

[Claims] 1. A composite device constructed by connecting a plurality of external devices having second clock means to at least one external device via an interface to a copying machine having a first clock means. Setting means for setting one of the means and the second clock means as a reference clock, and transmitting means for transmitting time data from one clock means set as the reference clock by this setting means to the other clock means, A composite comprising: a receiving means for receiving the time data transmitted from the transmitting means, and a correcting means for automatically correcting the current time of one of the clock means based on the time data received by the receiving means. apparatus. 2. The transmitting means transmits the time data at every timing of turning on the power of any one of the clock means, changing the time, updating the time, and a predetermined interval. Item 1. The compound device according to item 1.