JPH06204664A - Multilayer substrate - Google Patents

Multilayer substrate

Info

Publication number
JPH06204664A
JPH06204664A JP34758192A JP34758192A JPH06204664A JP H06204664 A JPH06204664 A JP H06204664A JP 34758192 A JP34758192 A JP 34758192A JP 34758192 A JP34758192 A JP 34758192A JP H06204664 A JPH06204664 A JP H06204664A
Authority
JP
Japan
Prior art keywords
prepreg
conductive paste
printed wiring
filled
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34758192A
Other languages
Japanese (ja)
Inventor
Masatoshi Suehiro
雅利 末広
Mitsutomi Iwasaka
光富 岩坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dowa Holdings Co Ltd
DKS Co Ltd
Original Assignee
Dai Ichi Kogyo Seiyaku Co Ltd
Dowa Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Ichi Kogyo Seiyaku Co Ltd, Dowa Mining Co Ltd filed Critical Dai Ichi Kogyo Seiyaku Co Ltd
Priority to JP34758192A priority Critical patent/JPH06204664A/en
Publication of JPH06204664A publication Critical patent/JPH06204664A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Non-Insulated Conductors (AREA)

Abstract

PURPOSE:To increase the mounting density of a circuit board by filling the inside of prepreg with conductive paste, by forming a conductive circuit within the prepreg, thereby providing high-density wiring and, at the same time, reducing the number of through-holes. CONSTITUTION:Viaholes 2 are formed by a punching machine at a plurality of positions required through a prepreg 1. Then, the viaholes 2 are filled up with a conductive paste 3 by means of screen printing or dispenser coating. This conductive paste is produced by blending metal powder of gold, silver, copper or nickel with a thermosetting resin such as phenol resin or epoxy resin, and solvent can be also mixed together. The prepreg 1 filled up with the conductive paste is placed between printed wiring boards 4a and 4b, both the surfaces of which had wiring circuits L in advance and is pressed to one united body after correcting the positions so as to secure the continuity between each electrode 5 of the printed wiring boards 4a and 4b and the conductive paste.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子機器等に利用される
多層化基板に関し、さらに詳しくは高密度な実装を可能
とする多層化基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layered substrate used in electronic equipment and the like, and more particularly to a multi-layered substrate which enables high-density mounting.

【0002】[0002]

【従来の技術】プリント配線板の高密度化に関し、層間
接続をとることが高密度化の重要な要件であり、そのた
めに、種々の製造方法および技術が紹介されている。例
えば、両面配線板の両側の導通を図るためには、スルー
ホールを介してメッキにより接続する方法、あるいは導
電ペーストを用いてスルーホールを接続する方法があ
る。
2. Description of the Related Art Regarding the densification of a printed wiring board, interlayer connection is an important requirement for densification, and therefore various manufacturing methods and techniques have been introduced. For example, in order to establish conduction on both sides of the double-sided wiring board, there are a method of connecting by plating through the through holes, and a method of connecting the through holes by using a conductive paste.

【0003】ところで、半導体集積回路を初めとした一
連の部品の小型化に伴い、プリント配線板上での機能を
大きくし、しかも装置の小型化が可能となってきた。し
かし、片面・両面配線板では配線数が不足し、端子接続
が処理しきれないために、複数のプリント配線板を積層
した多層化基板が用いられている。この多層化基板とし
ては、例えば、図2に示すように、両面に配線回路Lの
形成されたプリント配線板11の両側にプリプレグ12
a、12bを介して最外層に銅箔を積層した後、貫通ス
ルーホール13を設け、このスルーホール13に導電性
のメッキを施した後、最外層の銅箔をエッチングして配
線回路Lを形成するものが知られている。
By the way, along with the miniaturization of a series of parts including a semiconductor integrated circuit, it has become possible to increase the function on the printed wiring board and further miniaturize the device. However, a single-sided / double-sided wiring board is insufficient in the number of wires and terminal connection cannot be processed. Therefore, a multilayer board in which a plurality of printed wiring boards are laminated is used. As the multilayer substrate, for example, as shown in FIG. 2, prepregs 12 are provided on both sides of a printed wiring board 11 having wiring circuits L formed on both sides.
After a copper foil is laminated on the outermost layer via a and 12b, a through through hole 13 is provided, conductive plating is applied to the through hole 13, and the outermost copper foil is etched to form the wiring circuit L. What forms is known.

【0004】また、層間接続を増加させて高密度化を図
るために、図3に示すように、予めスルーホール13で
接続されると共に両面に配線回路Lの形成されたプリン
ト配線板14a、14bの間にプリプレグ15を介装
し、プリプレグ15とプリント配線板14a、14bを
それぞれ導通16したものが知られている。
Further, in order to increase the number of interlayer connections and increase the density, as shown in FIG. 3, the printed wiring boards 14a and 14b are preliminarily connected by through holes 13 and wiring circuits L are formed on both surfaces. It is known that a prepreg 15 is interposed between the prepreg 15 and the prepreg 15 and the printed wiring boards 14a and 14b are electrically connected 16 respectively.

【0005】[0005]

【発明が解決しようとする課題】このように、従来の多
層化基板においては、スルーホールを介して上下面の導
通が図られているものの、プリプレグを介在させて多層
化する構造であるため、プリプレグの両側に位置する導
電層を接続する方法としては、多層化基板全体を貫通す
るスルーホールでの接続に頼っていた。そのため、貫通
スルーホールの数が多くなり、表層に実装することがで
きる部品点数が制限され、高密度実装を妨げる要因とな
っていた。
As described above, in the conventional multi-layer substrate, although the upper and lower surfaces are electrically connected through the through holes, the multi-layer structure is formed by interposing the prepreg. The method of connecting the conductive layers located on both sides of the prepreg relies on the connection by through holes penetrating the entire multilayer substrate. Therefore, the number of through-holes increases, and the number of components that can be mounted on the surface layer is limited, which is a factor that hinders high-density mounting.

【0006】本発明はこのような従来の技術の有する問
題点に鑑みてなされたものであって、その目的は、高密
度実装が可能な多層化基板を提供することにある。
The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a multi-layered substrate capable of high-density mounting.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明の要旨は、内層あるいは表層にプリプレグを介
してプリント配線板を積層してなる多層化基板におい
て、上記プリプレグにビアホールを形成し、該ビアホー
ル内に導電性ペーストを充填したことを特徴とする多層
化基板にある。
In order to achieve the above object, the gist of the present invention is to form a via hole in the prepreg in a multi-layered substrate in which a printed wiring board is laminated on an inner layer or a surface layer through a prepreg. The multilayer substrate is characterized in that the via hole is filled with a conductive paste.

【0008】[0008]

【作用】プリプレグの両側に位置する導電層を導電性ペ
ーストを充填したプリプレグを介して接続することによ
り、高密度配線が可能になり、同時に貫通スルーホール
の個数が少なくて済むので部品実装面積が大きくとれ、
プリント配線板の実装密度を向上することができる。
[Function] By connecting the conductive layers located on both sides of the prepreg through the prepreg filled with the conductive paste, high-density wiring becomes possible, and at the same time, the number of through-holes can be reduced, so that the component mounting area can be reduced. Take big,
The mounting density of the printed wiring board can be improved.

【0009】[0009]

【実施例】以下に本発明の多層化基板を製造する方法の
一例を、図1に基づいて説明する。図に示すように、ま
ずプリプレグ1の複数の必要箇所に、パンチングマシー
ンで0.2〜1.0mm径のビアホール2を形成する。次
いで、このビアホール2内に、導電性ぺースト3を、ス
クリーン印刷またはディスペンサー塗布法等によって充
填する。この導電性ペースト3は、粒径1〜100μm
の金、銀、銅あるいはニッケルなどの金属粉末をフェノ
ール樹脂またはエポキシ樹脂等の熱硬化性樹脂とブレン
ドしたものであって、その中に溶剤を含有することもで
きる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a method for manufacturing a multi-layer substrate of the present invention will be described below with reference to FIG. As shown in the figure, first, via holes 2 having a diameter of 0.2 to 1.0 mm are formed by a punching machine at a plurality of required portions of the prepreg 1. Then, the conductive paste 3 is filled in the via hole 2 by screen printing or a dispenser coating method. The conductive paste 3 has a particle size of 1 to 100 μm.
The metal powder of gold, silver, copper, nickel or the like is blended with a thermosetting resin such as a phenol resin or an epoxy resin, and a solvent may be contained therein.

【0010】この導電性ペーストを充填したプリプレグ
1は、あらかじめ両面に配線回路Lが形成されたプリン
ト配線板4aと4bとの間に介装し、プリント配線板4
a、4bの各電極5と導電性ペースト3との導通が確保
されるように位置を修正した後で、一体にプレスする。
以上の例は、4層基板を示すが、同様の方法でより多層
の基板を製造することができるのはもちろんである。
The prepreg 1 filled with the conductive paste is interposed between the printed wiring boards 4a and 4b having wiring circuits L formed on both sides in advance, and the printed wiring board 4 is provided.
After the position is corrected so as to secure the conduction between the electrodes 5 of a and 4b and the conductive paste 3, they are pressed together.
Although the above example shows a four-layer substrate, it goes without saying that more multilayer substrates can be manufactured by the same method.

【0011】[0011]

【発明の効果】本発明は、プリプレグ内に導電性ペース
トを充填してプリプレグ内に導通回路を形成したもので
あるから、高密度配線が可能になり、同時に貫通スルー
ホールの個数を極力少なくすることができる。その結
果、配線板表層に実装できる部品点数が多くなり、いわ
ゆる高密度実装が可能になる。
As described above, according to the present invention, the conductive paste is filled in the prepreg to form the conductive circuit in the prepreg, which enables high-density wiring and at the same time minimizes the number of through-holes. be able to. As a result, the number of components that can be mounted on the surface layer of the wiring board increases, and so-called high-density mounting becomes possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多層化基板の断面図である。FIG. 1 is a cross-sectional view of a multilayer substrate according to the present invention.

【図2】従来の多層化基板の断面図である。FIG. 2 is a cross-sectional view of a conventional multilayer substrate.

【図3】従来の別の多層化基板の断面図である。FIG. 3 is a cross-sectional view of another conventional multilayer substrate.

【符号の説明】[Explanation of symbols]

1、12a、12b、15…プリプレグ 2…ビアホール 3…導電性ペースト 4a、4b、11、14a、14b…プリント配線板 5…電極 13…スルーホール L…配線回路 1, 12a, 12b, 15 ... Prepreg 2 ... Via hole 3 ... Conductive paste 4a, 4b, 11, 14a, 14b ... Printed wiring board 5 ... Electrode 13 ... Through hole L ... Wiring circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内層あるいは表層にプリプレグを介して
プリント配線板を積層してなる多層化基板において、上
記プリプレグにビアホールを形成し、該ビアホール内に
導電性ペーストを充填したことを特徴とする多層化基
板。
1. A multi-layered substrate having a printed wiring board laminated on an inner layer or a surface layer via a prepreg, wherein a via hole is formed in the prepreg and a conductive paste is filled in the via hole. Substrate.
JP34758192A 1992-12-28 1992-12-28 Multilayer substrate Pending JPH06204664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34758192A JPH06204664A (en) 1992-12-28 1992-12-28 Multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34758192A JPH06204664A (en) 1992-12-28 1992-12-28 Multilayer substrate

Publications (1)

Publication Number Publication Date
JPH06204664A true JPH06204664A (en) 1994-07-22

Family

ID=18391189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34758192A Pending JPH06204664A (en) 1992-12-28 1992-12-28 Multilayer substrate

Country Status (1)

Country Link
JP (1) JPH06204664A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999009795A1 (en) * 1997-08-13 1999-02-25 Fry's Metals, Inc. Process for the formation of composite films
JP2011040607A (en) * 2009-08-12 2011-02-24 Tatsuta Electric Wire & Cable Co Ltd Multilayer flexible printed circuit board and method for manufacturing the same
JP2011160005A (en) * 2011-05-25 2011-08-18 Tatsuta Electric Wire & Cable Co Ltd Partially-multilayered flexible printed wiring board
JP2014216552A (en) * 2013-04-26 2014-11-17 富士通株式会社 Laminate structure and process of manufacturing the same
CN113207223A (en) * 2021-04-22 2021-08-03 联合汽车电子有限公司 Conduction structure and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999009795A1 (en) * 1997-08-13 1999-02-25 Fry's Metals, Inc. Process for the formation of composite films
JP2011040607A (en) * 2009-08-12 2011-02-24 Tatsuta Electric Wire & Cable Co Ltd Multilayer flexible printed circuit board and method for manufacturing the same
KR20120071387A (en) * 2009-08-12 2012-07-02 다츠다 덴센 가부시키가이샤 Multilayer flexible printed circuit board, and method for fabricating the same
JP2011160005A (en) * 2011-05-25 2011-08-18 Tatsuta Electric Wire & Cable Co Ltd Partially-multilayered flexible printed wiring board
JP2014216552A (en) * 2013-04-26 2014-11-17 富士通株式会社 Laminate structure and process of manufacturing the same
CN113207223A (en) * 2021-04-22 2021-08-03 联合汽车电子有限公司 Conduction structure and manufacturing method thereof

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