JPH06204820A - Comparator circuit and method for comparing a pair of signals with each other - Google Patents

Abstract

PURPOSE: To provide an improved comparator circuit for generating a resulting digital output by comparing two input signals with each other. CONSTITUTION: This comparator circuit 10 uses a single cascode device and a current mirror circuit 22, which are connected in parallel with two differential amplifier stages 12 and 14. One of the stages 12 and 14 receives differential input signals, and the other receives a variable reference voltage and a feedback voltage from the output of the comparator 10. The reference voltage is changed according to a request from a user. The reference voltage can be changed to any voltage within the range of input signals given to the differential amplifier stage. The hysteresis differential voltage of the input differential amplifier stage can be controlled accurately, by changing a bias current given to the hysteresis differential amplifier stage and the reference voltage.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to electronic circuits, and more particularly to a comparator circuit for comparing two input signals to produce a resulting output signal.

[0002]

BACKGROUND OF THE RELATED ART Comparator circuits used to compare two input signals are well known. In operating in the non-linear range, the comparator provides information on the digital output voltage corresponding to the difference between the input voltages. For example, if the input voltage presented to the non-inverting input is greater than the voltage presented to the inverting input, then a relatively large output signal will be produced. Conversely, if the input voltage to the non-inverting input is lower than the input voltage to the inverting input, then a relatively low output voltage will be produced. Therefore, the comparator functions to compare the two input signals and produce a digital output based on the comparison.

Most comparator circuits include at least two stages of operation. For example, a typical comparator uses differential amplifiers or differential transistor pairs in the input stage of operation and multiple loads / buffers in the output stage. The amplifier and load circuit are biased from a constant current source and a voltage reference that is typically generated in the same monolithic circuit as that of the comparator. By integrating the reference voltage device and the constant current source on the same silicon chip as the comparator, less package leads are needed, ie no power needs to be drawn from outside the chip. Furthermore, the integration ensures that the behavior of each component with fairly uniform processing parameters across the substrate surface is consistent.

A problem often encountered with many conventional comparators is the detrimental effect of noise on the input signal feeding the comparator. For example, if one input slightly exceeds the other due to noise, the output may inadvertently be triggered to the opposite digital value. Inadvertent triggering of the output by rapid and subtle fluctuations in the noise of the input signal will occur in rapid succession. The presence of such fluctuations in the output of the comparator caused by noise on the input is sometimes referred to as "chatter".
Called.

In trying to overcome the chatter problem, many comparators use a hysteresis feedback loop from the output of the comparator to the input amplifier stage.
A comparator circuit using a feedback hysteresis loop is described in US Pat. No. 4,670,671. US Pat. No. 4,670,671 describes a comparator circuit having two separate differential amplifiers, one receiving feedback information from the output of the comparator and the other receiving the input signal. . Patent No. 4,670,671
Device guarantees that the output does not change unless one input signal exceeds the other input signal by a hysteresis value. The output of the comparator will not inadvertently toggle or chatter unless the noise peak on one input exceeds the other input by a hysteresis value.

The comparator of Japanese Patent No. 4,670,671 is
It is primarily designed to provide relatively low power while providing hysteresis feedback during high speed operation. As such, Patent No. 4,670,671
Each differential amplifier (feedback differential amplifier and input differential amplifier) requires a pair of feedback current mirrors or loads. Although these loads provide high speed operation with low power consumption, each load must use three transistors interconnected with positive and negative driver circuits. The inclusion of separate loads and drivers increases the complexity of the device by requiring a large number of transistors and their associated interconnect routing. The addition of transistors and routing only adds to the cost of manufacturing monolithic devices and reduces device reliability.

[0007]

SUMMARY OF THE INVENTION Most of the problems outlined above are solved by the comparator of the present invention. That is, the comparator circuit described herein uses a single load circuit instead of the multiple load circuits commonly found in previous designs. Specifically,
The single load circuit provided in the folded cascode device and the current mirror circuit comprises part of a single suction and discharge output stage for the device of the present invention. The folded cascode device and the current mirror circuit receive parallel inputs from both the feedback (or hysteresis) differential amplifier and the input (or main) differential amplifier. By connecting each differential amplifier pair of transistors in parallel between a constant current device and a cascode device, it is necessary to provide relatively few active devices and their associated interconnections to provide the operation of the present invention. Will be one load circuit. Instead of requiring four separate feedback current mirror loads (each load contains three transistors) and two separate drivers (positive and negative drivers) as shown in US Pat. No. 4,670,671. , The present invention only requires a single shared current mirror load and a pair of cascode devices.

Broadly speaking, the present invention contemplates an improved comparator circuit having a smaller number of active devices and associated interconnections. This comparator therefore takes up less silicon space and is more reliable to operate cheaper to manufacture. The comparator includes a pair of current devices and further includes a first of current from each current device.
Also included is a cascode device and a current mirror that are coupled to receive a portion of the. A pair of differential transistors are coupled to receive the pair of input signals and also receive a second portion of the current from each current source. A pair of hysteresis transistors are coupled in parallel with the differential transistors to receive a third portion of the current from each current device. The output voltage produced by the cascode device and the current mirror circuit may be varied in response to changes in the relative magnitudes of the first, second and third portions of the current.

The present invention also contemplates a comparator circuit for comparing a pair of input signals. The improved comparator circuit described herein includes first and second current devices,
Each current device is adapted to produce a constant current equal to the current produced by the other current device. The cascode device and the current mirror circuit are coupled to the first and second current devices so that the cascode device and the current mirror establish a suction and discharge output stage for delivering the output of the comparator. First and second conductive paths are coupled between the cascode device and the current mirror circuit and the first and second current devices, respectively. The first conductive path is changed by the output of the comparator and the second conductive path is changed by the variable reference voltage. The third and fourth conductive paths are coupled in parallel with the first and second conductive paths, respectively. The third conductive path is modified by one input signal of the pair of input signals and the fourth conductive path is modified by the other input signal of the pair of input signals. Increasing the voltage on one input signal to a higher hysteresis value than the other input signal results in imbalance of sink and discharge currents at the output stage.

The cascode device and current mirror circuit of the present invention do not require many active devices or transistors. Specifically, the cascode device and the current mirror circuit are configured such that one end of the conductive path has a first and second end, respectively.
First and second cascode transistors connected to the current device of FIG. The 4-transistor current mirror is connected between the cascode transistor and the first power supply, and the output node is connected between the second cascode transistor and the two series-connected transistors of the 4-transistor current mirror.

The present invention further contemplates a method for comparing a pair of input signals. The method includes providing a pair of constant current devices and drawing a first portion of the current from each current device through a cascode device and a current mirror circuit. The second portion of the current is adapted to receive a pair of input signals 1
It is drawn from the current device through the main differential transistor of the pair. A third portion of the current is drawn from each current device via a pair of hysteretic differential transistors that are coupled to receive the reference voltage and the output voltage from the output of the comparator. The output voltage is generated by sinking and discharging current through the cascode device and the current mirror circuit, and then the output is fed back to one input of the hysteresis differential transistor pair. The output voltage changes in response to changes in the relative magnitudes of the first, second and third portions of current. The digital change in output voltage is
This occurs when the relative magnitudes of the portions of current change during the time that the voltage of one input signal exceeds the voltage of the other input signal by a certain amount of hysteresis.

Other objects and advantages of the present invention will become apparent upon reading the detailed description below and referring to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail in the following section. However, the drawings and description therefor are not intended to limit the invention to the particular form disclosed, but to the contrary, within the spirit and scope of the invention as defined by the appended claims. It is to be understood that it is the intention to cover all the variations, equivalents and alternatives that come in.

[0014]

DETAILED DESCRIPTION OF THE INVENTION Turning now to the drawings, FIG.
Shows a block diagram of an improved comparator circuit 10 having three stages of operation. First stage, or main differential amplifier stage 12
Is adapted to receive the input signals IP and IN at the non-inverting and inverting input terminals as shown. According to standard comparator function, if the input signal IP exceeds the input signal IN, a digital "1" or a relatively high voltage value will appear at the output of the comparator 10. The second stage or hysteresis differential amplifier stage 14 functions to receive the output voltage VOUT and the reference common mode voltage VCM and produce an output that is coupled in parallel to the output of the main differential amplifier stage 12.

A voltage bias generator 16 of common design and well known type establishes the bias voltage needed to bias the constant current devices 18 and 20, stages 14 and 12, and circuit 22. Shown as capable. Generator 16 may produce several voltage levels, including PBIAS voltage and NBIAS voltage. In addition, each PBIAS and NBIAS may singly have two or more distinct voltage levels, one of which is higher or lower than the level used to bias devices 18 and 20. The circuit 22 may be biased at the voltage level. Further, the generator 16 may generate the reference voltage VCM, or the reference voltage VCM may be generated from a driver external to the comparator circuit 10 if desired. Reference voltage NB
IAS may be present in both stages 12 and 14.
-Suitably used to modify constant current devices such as channel current sinks. In contrast, PBIAS is used to alter a constant current device such as a p-channel current source that may be present in both stages 12 and 14 instead of n-channel current sinking. Furthermore, depending on the application, NB
Either IAS or PBIAS is used to alter the constant current devices 18 and 20 (which may be n-channel current sinks as shown in FIG. 3 or p-channel current sources as shown in FIG. 2). You may As discussed in various preferred embodiments described below, the user desires to configure comparator 10 primarily with p-channel transistor devices or with n-channel transistor devices. Depending on the crab, steps 12 and 1
4 or current sources 18 and 20 may use current sinks or current sources. The term "current device" as used herein to describe devices 18 and 20 refers to either a current source or a current sink.

The third stage or cascode device and current mirror circuit 22 is adapted to receive a portion of the current from current devices 18 and 20. The remaining portion of the current is shunted to the main differential amplifier stage 12 and the hysteresis differential amplifier stage 14 coupled in parallel. Depending on the relative magnitude of the input IP with respect to the magnitude of the input IN, different proportions of current are carried through each of the three stages. For example I
If P exceeds IN, the current I _A will be disproportionately larger than the current I _B. Therefore, more current I is carried from current device 18 as I _{A and} less current I
Remains as I _E and is sent to the circuit 22. Conversely, less current I is sent to the main differential amplifier stage 12 as I _B , so more current I is sent to circuit 22 as I _F. The addition of the hysteresis differential amplifier stage 14 further sinks current from the current devices 18 and 20, which would otherwise pass through the circuit 22.
To ensure that the proper amount of current is delivered through circuit 22 to transition VOUT, the main differential amplifier stage 12 sinks an additional amount of current, through hysteresis stage 14. Have to overcome the additional suction of. The additional amount of current drawn through stage 12 is
It is caused by the additional hysteretic differential voltage introduced into the input signal above the balanced voltage level.

Referring to FIG. 2, a schematic diagram of one embodiment of comparator circuit 10 is shown in accordance with the present invention. The circuit diagram illustrates in more detail the block diagram of FIG. 1 where n-channel transistors predominate rather than p-channel transistors. In particular, stages 12, 14 and 2 of comparator 10
Each of the two is shown as having a limited number of active devices and associated interconnections. Main differential stage 12 is shown as including a pair of differential transistors 24 and 26, each transistor having a conductive path, one end of which is separated by a current sink transistor 28. Coupled to the conductive path of the. The NBIAS voltage that exceeds the first power supply by a threshold amount, such as ground, causes current to be drawn into the first power supply from the conductive path formed by differential transistors 24 and 26.

Coupled in parallel with differential transistors 24 and 26 and current sink transistor 28 is
Hysteresis transistors 30 and 32 and current sink transistor 34. The first and second current devices 18 and 20 are shown in FIG. 2 as using a single current source transistor. Current source transistor 3
6 and 38 are activated to provide a constant current from current devices 18 and 20, respectively. The amounts of current produced by current devices 18 and 20 are equal to each other because the PBIAS currents placed on the gates of transistors 36 and 38, respectively, are equal. The PBIAS voltage is a positive power supply (ie VD
Change the constant current flowing from the second power source as in D).

Cascode device and current mirror circuit 22
Includes two cascode transistors 40 and 42 that are connected in series with transistors 36 and 38 to establish a suction and a discharge configuration. mainly,
Suction and discharge occur at the common drain node of one of the cascode transistors of current mirror load 44 (ie, transistor 42) and one of the transistors (ie, transistor 46). Connected between the first power supply and the cascode transistors 40 and 42 is a four transistor current mirror load 44. Current mirror 44
Includes two transistors 46 and 48 connected in series between the first power supply and the transistor 42. Another pair of transistors 50 and 52 connected in series is connected between the first power supply and the transistor 40. The buffer circuit 54 including the two inverters 56 and 58 is
It may be used to buffer the output voltage VOUT from circuit 22. The buffer 54, however, is not needed in many applications. VOUT is fed back to the gate of transistor 30 of the pair of hysteresis transistors 30 and 32, regardless of whether buffer 54 is used.

Transistors found throughout comparator 10 may be field effect transistors (FETs) or bipolar transistors. Preferably,
Transistors are manufactured by MOSFET technology with both p-channel and n-channel devices. CM
OS design is preferred, but other transistor technologies may be used. A CMOS design was chosen for illustration purposes only and is shown in FIG. 2 as having p-channel and n-channel enhancement field effect transistors. As is generally known to those skilled in the art, enhancement transistors conduct when the applied gate-source voltage exceeds a threshold amount. However, it is important to note that one or more enhancement transistors may be replaced with depletion transistors provided the same purpose and function as described herein according to the present invention is maintained. . P-channel transistors are shown as having a small circle at their gate terminals, and n-channel transistors are shown as having no such circle at their gate. It is well known that the source terminal of the source-drain conductive path is the terminal closest to the power supply. For p-channel devices, the source terminal is a second power supply (eg VDD) than the drain terminal.
Connected closer to. In addition, the source terminal of the n-channel device is placed closer to the first power supply (eg ground) than the drain terminal.

The comparator 10 operates by considering the previous output of the comparator. If IP exceeds IN, then transistor 24 is more than via transistor 26.
More current is sent through. Thus, a resulting higher current will appear through transistor 42 than through transistor 40. Transistor 4
The lesser current through 0 is due to transistors 50 and 5
2 and via transistors 46 and 48. Small current through transistors 46 and 48 (less than current through transistor 42)
Indicates a current imbalance at the drain terminals of transistors 42 and 46. This current imbalance produces a relatively high digital output corresponding to the input IP being greater than the input IN.

If VOUT is at a relatively high voltage level, transistor 30 will saturate, which will result in more current sinking through transistor 30 than through transistor 32. Transistor 30
Provides current sinking in addition to current sinking through transistor 24, ensuring additional current imbalance at the drains of transistors 42 and 46. The additional current drain thus provides a level of hysteresis, which allows the input IP to flow before VOUT toggles from its higher voltage state to its lower voltage state.
Must be reduced below the input IN. VOUT
IN should toggle high enough to a low level, IN must be sufficiently higher than IP so that transistor 26 sinks sufficient current to overcome the sinking of current through transistors 24 and 30. I have to. Therefore, to transition VOUT from its previous high voltage state to a low voltage state, the input signal IP must be IN
It must be at a lower threshold level (hysteresis level) or the input signal IN must be at a higher threshold level (hysteresis level) than IP.

The amount of hysteresis voltage can be adjusted by changing the bias current in the transistors 34 of the hysteresis differential pair. As the bias current in transistor 34 increases, so does the hysteresis voltage. Similarly, as the bias current decreases, so does the hysteresis voltage. This provides a well controlled hysteresis voltage in the comparator 10. "Hysteresis width" is V
Defined as the difference in voltage between IP and IN that transitions OUT, the "hysteresis position" is defined as the voltage point at which the transition occurs in relation to the input voltage applied to the main differential amplifier stage 12. The hysteresis width is set to the suction transistor 34 (see FIG. 2) or the discharge transistor 70.
It can be changed by changing the bias current through (see FIG. 3). In addition, the hysteresis point can be changed by changing the relative magnitude of the VCM within the input differential range of the main differential pair 12.

Referring to FIG. 3, there is shown an alternative embodiment of comparator 10 that can achieve the same results as the comparator shown in FIG. Instead of using n-channel predominant devices as shown in FIG. 2, the embodiment of FIG. 3 primarily uses p-channel devices. Specifically, the main differential amplifier stage 12 is p-
2 coupled in series with channel current source transistor 64
Shown as using one p-channel differential transistor pair 60 and 62. Coupled in parallel with stage 12 is a p-channel hysteresis transistor pair 6
Hysteresis differential stage 14 with 6 and 68.
Transistor pair 66 and 68 are coupled in series with p-channel current source transistor 70.

Shown in FIG. 3 are parallel coupled stages 12 and 14 and a cascode device connected between current devices 18 and 20, similar to the n-channel dominant layout of FIG. And current mirror circuit 22
Is. Current devices 18 and 20 have 72 and 74, respectively.
A single n-channel current sink transistor, designated as Transistors 72 and 74 sink a varying percentage of current from stage 12, stage 14 and circuit 22 according to the relative voltage difference between input signals IP and IN. The circuit 22 produces VOUT, which is VOU unless the differential voltage between IP and IN exceeds the hysteresis value.
Hold the state of T. VOUT is the circuit 22,
It changes or transitions in response to a relative change in the magnitude of the first, second and third portions of the current received through the differential stage 12 and the hysteresis stage 14. As long as one input does not exceed the other input by a hysteresis value, no current imbalance will occur at the drains of transistors 88 and 76, and thus no VOUT transition. The pair of cascode devices 76 and 78 are connected in series between the current devices 18 and 20 and the p-channel current mirror 80, respectively. Current mirror 8
0 is four p-channel transistors 82, 84, 86
And 88. Suction and discharge occur at the drain common to transistors 88 and 76 shown in FIG.

The embodiment illustrated in FIG. 3 operates similarly to that shown in FIG. That is, VOUT is fed back to the hysteresis stage, which provides a subsequent transition in the output when the hysteresis differential input voltage occurs. Instead of sinking current from the current source transistor as in the embodiment of FIG. 2, stages 12 and 14 (as shown in FIG. 3) and circuit 22 are proportional to the input signal difference and the current state of VOUT. It discharges current to the current sink transistors 72 and 74.

Referring to FIG. 4, simulation results are shown for the comparator 10 of the present invention. During the simulation, the voltage reference VCM was fixed at a constant voltage of 2.4 Volts and the first and second power supplies were set to ground and 5.0 Volts respectively. The input signal IN is also 2.
Set to 4 volts, the voltage of the input signal IP was varied with respect to VCM. FIG. 4 shows the width of the hysteresis at the exemplary VCM and input voltage selected for the simulation. IP as seen in curve 100
Is greater than IN by about 25 millivolts (mV), VO
The UT begins a transition from a relatively low voltage value to a relatively high voltage value (ie, 0 volt to 5 volt). Curve 1
00 is shown as a steep line showing the rapid output slew rate that is the result of the preferred design. In addition, curve 1
02 indicates that IP remains at 5 volts even after being reduced slightly below IN. However, once IP is 25 mV less than IN, VOUT
Begins the 5 volt to 0 volt transition as shown.

Referring to FIG. 5, a transient analysis at the moving point of VOUT is shown. When IP rises 25 mV above IN, as shown by curve 104, VOUT is time T
Transition to higher level with ₁ . Following the transient sinusoid, the reverse bias of signal IP below IN, as shown by curve 106, causes VOUT to transition to a low level at time T ₂ . On the contrary, curve 108 shows the opposite result that occurs when the input signal IN initially deviates below the input signal IP and then reverses and deviates to become greater than the input signal IP. Transient analysis shows a rapid response of the output slew rate once the differential input voltage exceeds the hysteresis value or 25 mV. If the differential input signal fluctuates (which can be caused by noise) and goes below the hysteresis level of 25 mV, VOUT will not transition and will not produce an unwanted chatter signal.

The present invention is a bipolar or MOS, p
-It is believed that the application is possible in numerous types of transistors, either channel-dominant or n-channel-dominant, or enhancement-dominant or depletion-dominant. Will be recognized by those of ordinary skill in the art having the benefit of this disclosure. Furthermore, it is to be understood that the form of the invention shown and described is to be taken as the presently preferred embodiment. Various changes and modifications may be made without departing from the spirit and scope of the invention as set forth in the claims. An exemplary variation may be to use a current source as opposed to the current sink of each stage of the comparator. Furthermore, current sinking may be used instead of a current source for each of the constant current devices. Furthermore, buffer circuits may or may not be used, depending on the needs of the user and the particular output application. The claims set forth above are intended to be construed to include all such variations and modifications.

[Brief description of drawings]

FIG. 1 is a block diagram of a comparator circuit according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of a comparator circuit according to the present invention.

FIG. 3 is a circuit diagram of another embodiment of the comparator circuit according to the present invention.

FIG. 4 is a graphical representation of hysteresis width as a function of input voltage versus output voltage in accordance with the present invention.

FIG. 5 is a graphical representation of a transient analysis of the hysteresis shift point as a function of input voltage with respect to a reference voltage (VCM) according to the present invention.

[Explanation of symbols]

 10 Comparator Circuit 12 Main Differential Amplifier Stage 14 Hysteresis Differential Amplifier Stage 16 Voltage Bias Generator 18 Constant Current Device 20 Constant Current Device 22 Cascode Device and Current Mirror Circuit

Claims (21)

[Claims] 1. A pair of current devices, a cascode device and a current mirror circuit coupled to receive a first portion of the current from each of the current devices, and a pair of input signals and a first of the currents. A pair of differential transistors coupled to receive two portions from each of the current devices, and a pair coupled to the differential transistors in parallel to receive a third portion of current from each of the current devices. A hysteresis transistor for changing the output voltage produced by the cascode device and the current mirror circuit in response to changes in the relative magnitudes of the first, second and third portions of current. Comparator circuit including the means of. 2. The comparator circuit of claim 1, wherein the current device produces a current amount equal to the sum of the first, second and third portions of the current. 3. The comparator circuit of claim 1, wherein the pair of differential transistors and the pair of hysteresis transistors are coupled between the current device and the cascode device and current mirror circuit. 4. The output voltage is coupled to one of the inputs of the pair of hysteresis transistors, and the other input of the pair of hysteresis transistors is coupled to receive a reference voltage. Comparator circuit. 5. A comparator circuit for comparing a pair of input signals, comprising first and second current devices, each current device being a constant equal to the current produced by the other current device. A single cascode device and a current mirror circuit adapted to generate an electric current and further having two sink and discharge current paths and an output connected to one of said current paths; And the first
And a first coupled respectively to the second current device
And a second conductive path, wherein the first conductive path is modified by a signal sent from the output, the second conductive path is modified by a variable reference voltage, and the first and second conductive paths are further modified. A third and a fourth conductive path coupled in parallel with the path, the third conductive path being altered by one input signal of the pair of input signals, and the fourth conductive path being the first conductive signal. Changed by the other input signal of the pair of input signals, further increasing the voltage of one input signal of the pair of input signals to a hysteresis value exceeding the other input signal of the pair of input signals, and A comparator circuit including means for producing a current imbalance in the current path. 6. The first and second conductive paths include a pair of hysteresis transistor conductive paths connected between the current device and a current sink coupled to a first power supply. 5. The comparator circuit according to item 5. 7. The first power supply is grounded.
Comparator circuit according to. 8. The first and second conductive paths include a pair of hysteresis transistor conductive paths connected between the current device and a current source coupled to a second power supply. 5. The comparator circuit according to item 5. 9. The comparator circuit of claim 8, wherein the second power supply is a positive voltage. 10. The third and fourth conductive paths include a pair of differential transistor conductive paths connected between the current device and a current sink coupled to the first power supply.
The comparator circuit according to claim 5. 11. The comparator circuit of claim 10, wherein the first power supply is grounded. 12. The third and fourth conductive paths include a pair of differential transistor conductive paths connected between the current device and a current source coupled to a second power supply. Item 5. The comparator circuit according to item 5. 13. The comparator circuit of claim 12, wherein the second power supply is a positive voltage. 14. The comparator circuit of claim 5, wherein each of the first and second current devices includes a transistor that is varied by a constant bias voltage from a bias generator. 15. The cascode device and the current mirror circuit include first and second cascode transistors each having one end of a conductive path thereof connected to the first and second current devices, the load transistor and the second cascode device, respectively. A four-transistor current mirror connected to and from one power supply, the output being connected between the second cascode transistor and two series-connected transistors of the current mirror. Item 5. The comparator circuit according to item 5. 16. The comparison of claim 15, wherein the cascode device and current mirror circuit further include means for varying the first and second cascode transistors with a constant bias voltage sent from a bias generator. Circuit. 17. The comparator circuit of claim 5, further comprising a buffer circuit located between the output and the cascode device and current mirror circuit. 18. A comparator circuit for comparing a pair of input signals, comprising first and second current devices, each current device being a constant equal to the current produced by the other current device. A cascode device and a current mirror circuit, the cascode device and the current mirror circuit being arranged between the first and second current devices and the first power supply, First and second cascode transistors, each cascode transistor having a conductive path and one end of each of the conductive paths being connected to the first and second current devices, respectively, and further including the cascode transistor and the second cascode transistor. A four-transistor current mirror connected between two power sources, and two series connected transistors of the second load transistor and the current mirror. An output connected to the first and second current devices, the comparator circuit further comprising: an output connected to the first and second current devices, respectively. , The first conductive path is modified by the output, the second conductive path is modified by a variable reference voltage, and is further coupled in parallel with the first and second conductive paths. A third and a fourth conductive path, wherein the third conductive path is changed by one input signal of the pair of input signals, and the fourth conductive path is the other of the pair of input signals. Of the input signals of the pair of input signals, the voltage of one input signal of the pair of input signals is increased to a hysteresis value exceeding the other input signal of the pair of input signals, and the first and second Mosquito Comprising means for providing an imbalance current between the code transistor, a comparator circuit. 19. A method for comparing a pair of input signals, the method comprising the steps of: providing a pair of constant value current devices, said first portion of current being provided via a cascode device and a current mirror circuit. Deriving from each of the current devices, a second portion of the current from each of the current devices via a pair of differential transistors coupled to receive the pair of input signals; Drawing a third portion of the current from each of the current devices via a pair of hysteresis transistors coupled to receive a reference voltage and an output voltage, the first, second and third of the currents Generating the output voltage from the cascode device and a current mirror circuit in response to changes in relative size of the portions.
Method. 20. The step of generating includes the step of increasing the voltage of one input signal of the pair of input signals to a hysteresis value that exceeds the other input signal of the pair of input signals. Item 19. The method according to Item 19. 21. The generating step includes the step of lowering the voltage of one input signal of the pair of input signals to a hysteresis value that is lower than the other input signal of the pair of input signals. Item 19. The method according to Item 19.