JPH06205018A - Serial multiplex communication system - Google Patents

Abstract

(57) [Summary] [Purpose] To speed up error re-transmission and not to wait longer than necessary. In a baseband serial multiplex communication system in which a transmission delay time is shorter than a 1-bit cycle, an input shift register D that sequentially inputs serial data and transmission data that is stored in an output data register H are sequentially transmitted to a communication path. An output shift register G that outputs and a monitor circuit C that monitors the state of the communication path and determines whether or not the communication path is empty.
And a waiting time control circuit I that measures a predetermined communication waiting time that is variably set for each node from the change time every time the communication path changes from the use state to an empty state, and prohibits transmission during that time. , When a transmission request occurs, the measurement by the waiting time control circuit indicates the passage of a predetermined communication waiting time,
Further, a control circuit K is provided for sequentially outputting the transmission data of the output shift register to the communication path only when the monitor circuit determines that the communication path is in an empty state after the elapse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial multiplex communication system in which a plurality of nodes can freely communicate with each other in a system having a short communication distance in which a transmission delay time can be ignored compared to a 1-bit cycle of data.

[0002]

2. Description of the Related Art Recently, electronic systems have been widely used in automobiles. Along with this, the number of wire harnesses is remarkably increasing, and serial multiplex communication for transmitting serial data in a baseband is becoming important in order to reduce harnesses.

In this serial multiplex communication system, a CSMA / CD (Carrier Sense Multiple) having a bus-like communication path, constantly monitoring whether or not the communication path is empty, and outputting transmission data to the communication path when the empty status is confirmed Accoss / C
ollision Detection) method is adopted. In addition, in a communication system such as an automobile, which has a short communication distance and in which the transmission delay time can be ignored compared to the bit period, each node can read data on the bus at the same time due to the simultaneity of the buses. We are doing contention.

A method in which, when transmission is started from two or more nodes at the same time and data bits ("1", "0") collide, one data bit ("1" or "0") is always generated. Then, the transmission node compares the transmission data with the data on the bus, and if the transmission data and the data on the bus match, the transmission can be continued. The node that has been able to continue transmission until the time when the data in the bus contention field has been transmitted will have the transmission right, and will continue to transmit data.

[0005]

In the contention of the bus-like communication path, the data with higher priority in the contention field has the transmission right. Therefore, if the data with higher priority continues, the data with lower priority will be I can no longer send. Due to the bit configuration of the contention field, different priorities are all assigned to all nodes, and no two nodes can have the same priority. Therefore, even if the urgency is almost the same, the priority will always be different, and if the communication is congested, the transmission data that has issued a transmission request much earlier will have a priority even if a later transmission request is issued. You have to wait for high send data. For this reason, Latency (the time from the generation of a transmission request to the actual completion of transmission) may become very large, which is a problem.

The present invention has been made to solve the above problems, and an object thereof is a transmission waiting time even for transmission data that happens to be set to a low transmission priority in a CSMA / CD type serial multiplex communication system. Is to prevent it from becoming longer than necessary, and to speed up the retransmission processing for communication errors.

[0007]

The structure of the invention for solving the above-mentioned problems is to connect a plurality of nodes and to provide a bus-like communication path for transmitting data and an output and an input of data to the communication path. The communication delay time is shorter than the 1-bit cycle, and the communication control circuit constantly monitors the communication path and confirms that the communication path is available when it is necessary to transmit, and then performs communication. Start CSMA / CD (Carrier
Sense Multiple Accoss / Collision Detection) serial multiplex communication system, the communication control circuit monitors the status of the communication path and monitors whether the communication path is empty, and serial data on the communication path. Input shift register that inputs sequentially, input data register that stores the received data that is input to the input shift register, output data register that stores the transmission data that is output to the communication path, and transmission data that is stored in the output data register An output shift register for sequentially outputting
Each time the communication path changes from the in-use state to the empty state, a predetermined communication waiting time that is variably set for each node is measured from the change time, and a waiting time control circuit that prohibits transmission during that time, and a transmission When a request occurs, the output shift is measured only when the waiting time control circuit indicates that the predetermined communication waiting time has elapsed, and when the monitor circuit determines that the communication path is empty. And a control circuit for sequentially outputting the transmission data of the register to the communication path.

Further, the invention of claim 2 is characterized in that the communication waiting time is variably set, and the predetermined communication waiting time to be measured is set to a predetermined first time as an initial value. The second time shorter than the first time is set for the retransmission due to the communication error, and the third time longer than the first time is set when the data communication ends normally. The first time, which is an initial value, is reset instead of the third time after the predetermined condition is satisfied.

According to a third aspect of the invention, the communication path is the third channel.
When the empty state is continued for the time of, the initial time of the first time is set instead of the third time.

[0010]

According to the first aspect of the present invention, the monitor circuit determines whether or not the communication path is empty, and the waiting time control circuit detects the time when the communication path changes from the in-use state to the empty state. A predetermined communication waiting time that is variably set for each node is measured, and transmission during that time is prohibited. Therefore, when a transmission request is generated at each node, even if it is confirmed that the communication path is in an empty state, data transmission is not always performed immediately. In addition, transmission is permitted for the first time only when the communication path is still empty after waiting for a predetermined communication waiting time determined according to the priority order, the transmission status, and the like.

The invention according to claim 2 is characterized by a communication waiting time setting method which is variably set for each node. In each node, the first time is set as the initial value of the communication waiting time. Therefore, when transmitting data for the first time after a system reset, etc., it is possible to transmit data if the communication channel is still empty after waiting for a predetermined first time after the communication channel became empty. Becomes Also, if an error occurs in data transmission, the communication waiting time is set to a second time shorter than the first time, and if completed normally, the communication waiting time is set to a second time shorter than the first time. The time of 3 is set. Therefore, it is possible to immediately retransmit the data when a communication error occurs. If a communication error does not occur and the node that has issued the first data transmission request conflicts with the node that has issued a non-first data transmission request, the first time with a short communication waiting time The transmission of the node for which the first data transmission request is set is permitted. In this way, the transmission of the node that has never transmitted data is prioritized.
After that, when the predetermined condition is satisfied, the first time of the initial value is reset instead of the third time. In addition to the condition described in claim 3, when the number of nodes whose communication waiting time is set to the first time is less than a predetermined value, the predetermined condition is the communication waiting time by the third time. This is the case, for example, when the transmission frequency to be transmitted becomes higher than a predetermined value.

According to the third aspect of the invention, when the communication path is continuously in the empty state for the third time, the first time is set as the communication waiting time by that time. Since the transmission request from the node has not occurred, the communication waiting time of the node set for the third time is returned to the initial value of the first time. By repeating this, the highest priority is given to the retransmission when the transmission error occurs, and then the priority is given to the transmission of the node which has not transmitted any data after being reset at the first time.

[0013]

As described above, since the waiting time control circuit and the control circuit are provided, the waiting time from the empty communication path to the transmission can be variably set for each node. When a transmission request is continuously generated in one node, it is prevented that the communication path is occupied only by the transmission of that node and another node cannot transmit.

[0014]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 shows the overall configuration of this system. This system is for data communication between a plurality of nodes, and comprises communication control circuits A _{1 to} A _n forming each node and a bus-like communication path B for performing data communication between each node.

FIG. 2 is a block diagram showing the configuration of the communication control circuit A. Communication control circuit A ₁ ~ A
_n is a monitor circuit C that constantly monitors the communication path B and determines whether or not the communication path B is free, an input shift register D that reads serial data on the communication path B, and a reception that is read by the input shift register D. An input data register E for storing data, a collision detection / communication error detection circuit F for comparing transmission data and data on the communication path B to determine whether there is a collision and detecting a communication error, and a communication path B
An output shift register G for sending serial data to
Between the output data register H for storing the transmission data to be transmitted from the output shift register G, the waiting time control circuit I for controlling the communication waiting time, the input / output processing circuit J for processing the input / output with the outside, and the respective constituent circuits. Of the control circuit K for controlling the data input / output.

The communication path B is pulled up to a positive power source through a resistor (not shown), the output stage transistor of the output shift register G has an open collector structure, and the communication path B is connected to this collector. Therefore, communication path B
If there is no data in the channel, the signal level of communication channel B is H
It is at a level. Therefore, when the communication path B is continuously at the H level after the previous communication is completed, the monitor circuit C determines that the communication path B is empty.

The input shift register D detects the signal level on the communication path B in synchronism with the synchronizing signal output from the control circuit K and sequentially inputs the detected signal level bit by bit. When the data input of one data frame shown in FIG. 3 is completed and there is no communication error, the value of the input shift register D is taken into the input data register E. Then, if necessary, it is output from the input / output processing circuit J to the outside via the control circuit K.

In the communication data frame shown in FIG. 3,
SOM is a field indicating the beginning of the data frame. The contention field is a field that indicates the priority of the data frame and is used to determine the bus exclusive right when bus contention occurs, and also includes data such as the transmitting node address, the receiving node address, and data identification data. Is a field indicating a control signal associated with the. Data is a field of data that contains the substantive information to be transmitted. The error control data field is CR
These are fields for error control such as communication error detection signals such as C (Cyclic Redundancy Check), parity check, and response signals for communication handshake. EOM is a field indicating the end of the data frame.

[0019] When the transmission request at the communication control circuit A ₁ is generated, the communication control circuit A _1, data of the output data register H to be transmitted is outputted to the output shift register G. When the monitor circuit C outputs a signal indicating that the communication path B is empty to the control circuit K and the wait time control circuit I outputs a predetermined communication wait time elapsed signal, the control circuit K synchronizes. The signal is output to the output shift register G, and the data frame is output from the output shift register G bit by bit to the communication path B.

At this time, the input shift register D has a communication path B.
Signal level is input in synchronization with the synchronization signal output from the control circuit K, and the input data and the transmission data are compared bit by bit in the collision detection / communication error detection circuit F. If they do not match, a collision occurs. If it occurs, the collision detection signal for immediately stopping the transmission is output to the control circuit K.

FIG. 4 shows an example of waiting time setting values in the waiting time control circuit I. In the case of resending when a communication error occurs, the communication waiting time is set to a second data bit time which is the second time so that the resending can be performed immediately. Then, the communication waiting time after the reset at each node is set to 2 data bit times which is the first time as an initial value. Further, when the data transmission is normally completed once in each node, the communication waiting time is set to 3 data bit times as the third time. With this setting, data can be transmitted continuously without fail at the time of retransmission due to a communication error. In addition, since the communication waiting time of the node that once transmitted the data is set to the third time, which is longer than the initial value of the first time, the data that has not been transmitted after reset is more likely than the node that continuously transmits the data. The transmission request of the node that has not transmitted is prioritized. Then, when the predetermined condition is satisfied, the third time is reset (reset) to the initial value of the first time, and the system returns to the initial state. In this embodiment, as the predetermined condition, it is adopted that the communication path remains in the empty state for the third time.

FIG. 5 shows an example of the configuration of the waiting time control circuit, which makes it possible to divide the same communication waiting time set value into that of FIG. 4 into three types. The state transition signal s6 indicating that the communication path B output from the monitor circuit C has changed from the busy state to the empty state is input to the counter circuit L, and the signal s6 causes the counter circuit L to start counting. Further, the bus empty state signal s1 output from the monitor circuit C is input to one terminal of the AND gate O via the control circuit K. Further, the other terminal of the AND gate O is supplied with a clock s of one data bit period from the control circuit K.
2 is inputting. The counter circuit L inputs the clock s2 output from the AND gate O and counts this clock to measure the elapsed time after the communication path B changes from the busy state to the empty state.

In the decoder circuit M, when the value of the counter circuit L coincides with the above three set values, that is, the first time, the second time, and the third time, respectively, the coincidence signal s31,
s32, s33 to MUX. It is a circuit for outputting to N. M
UX. N is a mode command signal s output from the control circuit K
6, i.e., a signal indicating the retransmission processing after the communication error, the first data transmission after the reset, or the non-first data transmission after the reset, and the coincidence signals s31, s32, and s33 are input. Then, MUX. N is the three match signals s31, s32, s33 according to the mode command signal s6.
Which match signal is used as the communication waiting time elapsed signal s4 is selected. The waiting time elapsed signal s4 is the OR gate P
The counter circuit L is reset by the output of the OR gate P to stop counting and output to the control circuit K.

When the empty state of the communication path B is continued for the third time as a predetermined condition for resetting the set value of the third time to the first time, the output of the decoder M is output. The coincidence signal s33 indicating that the coincidence with the third time is performed is used as the predetermined condition determination signal s5. The predetermined condition determination signal s5 is input to the control circuit K, and when the control circuit K receives the signal s5, it sets the mode command signal s6 to a signal indicating the first data transmission after the reset. The predetermined condition determination signal s5 is also input to the OR gate P, and the output signal of the OR gate P resets the counter circuit L.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a serial multiplex communication system according to a specific embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a communication control circuit in the system of the above embodiment.

FIG. 3 is a structural diagram showing a structure of a data frame in the system of the above embodiment.

FIG. 4 is an explanatory diagram showing an example of setting a communication waiting time.

FIG. 5 is a circuit diagram showing a configuration of a waiting time control circuit.

[Explanation of symbols]

A _{1 to An} ... Communication control circuit B ... Communication path C ... Monitor circuit D ... Input shift register E ... Input data register G ... Output shift register H ... Output data register I ... Wait time control circuit K ... Control circuit

Claims (3)

[Claims] 1. A bus-like communication path for connecting data between a plurality of nodes and a communication control circuit for outputting and inputting data to and from the communication path, wherein the transmission delay time is 1 bit cycle. The communication control circuit constantly monitors the communication path and starts communication after confirming that the communication path is free when it is necessary to transmit the CSMA / CD.
In the serial multiplex communication system according to the method, the communication control circuit monitors a state of the communication path and determines whether or not the communication path is empty, and an input for sequentially inputting serial data on the communication path. A shift register, an input data register that stores the received data input to the input shift register, an output data register that stores the transmission data that is output to the communication path, and a transmission data that is stored in the output data register. An output shift register that sequentially outputs to the communication path, and each time the communication path changes from an in-use state to an empty state, a predetermined communication waiting time variably set for each node from the change time is measured, A waiting time control circuit that prohibits transmission during that time and a measurement by the waiting time control circuit when a transmission request occurs Of the communication wait time, and only when the monitor circuit determines that the communication path is in an empty state at that time, the control circuit sequentially outputs the transmission data of the output shift register to the communication path. And a serial multiplex communication system having. 2. In the waiting time control circuit, a predetermined first time is set as an initial value for the predetermined communication waiting time measured, and the first waiting time is set for retransmission due to a communication error. A second time shorter than the time is set, and when the data communication ends normally, a third time longer than the first time is set, and the third time is replaced after the predetermined condition is satisfied. The serial multiplex communication system according to claim 1, wherein the first time of an initial value is reset. 3. The serial multiplex communication system according to claim 2, wherein the predetermined condition is that the communication path remains idle for the third time.