JPH0620901A - Method of forming resist pattern - Google Patents

Abstract

PURPOSE:To improve the resolubility of a pattern in the upper and lower sections of the stepped section of a large area section, and to reduce the dimensional change of the pattern in the upper and lower sections of the stepped section to approximately half. CONSTITUTION:The upper section of a semiconductor substrate 1 is coated with a resist and heated, thus forming a resist film 2. The upper section of the resist film 2 formed is irradiated selectively with near ultraviolet rays according to a pattern by using a first mask 3, and a section 4 irradiated with the ultraviolet rays is removed partially through development. The upper section of the resist film 2 is irradiated selectively with near ultraviolet rays according to a pattern by employing a second mask 5, and developed, thus forming a pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist pattern forming method which is a manufacturing technique for LSIs and the like, and suppresses a dimensional change of a resist pattern above and below a step of a base.

[0002]

2. Description of the Related Art Conventionally, a projection exposure method has been widely used for forming a fine pattern used in manufacturing a semiconductor device. The projection exposure method, especially the reduction projection exposure method is useful for forming extremely fine patterns. The resist film thickness is different above and below the unevenness of the substrate surface caused by the underlying pattern. Therefore, it is becoming difficult to control the pattern dimension by the unevenness of the surface of the substrate. The drawbacks due to the step caused by the relatively fine pattern have been dealt with by the development of a well-known multilayer resist method or a planarization technique. However, even with the above method, it is not possible to completely flatten the step caused by the large-area pattern, and it has been difficult to control the resist dimension change at the upper and lower portions of the step.

[0003]

With the recent high integration of semiconductor integrated circuits and the like, the miniaturization of patterns and the unevenness of unevenness on the substrate surface remarkably increase, and it is required to cope with them. In the above-mentioned conventional technique, it is not possible to completely flatten the uneven steps caused by the large-area pattern, and it is difficult to control the resist dimensional change above and below the steps. An object of the present invention is to provide a pattern forming method capable of forming a fine pattern with sufficiently high accuracy even if a step is generated due to a large area pattern.

[0004]

In order to achieve the above object, a method of forming a resist pattern according to the present invention uses a step of applying a resist film on a semiconductor substrate and a first mask on the resist film. A step of selectively performing a first exposure, a step of developing and removing the area subjected to the first exposure, and a step of performing a second exposure on the resist film using a second mask Then, the area subjected to the second exposure is developed.

[0005]

In the present invention, the controllability of the resist pattern can be improved by partially removing the resist under the step of the large-area pattern portion so that the resist film has a film thickness equivalent to the resist film above the step. In the method of removing a part of the resist film under the step described above, the resist film thickness above and below the step is matched by exposing and developing using a mask that shields the pattern above the step. Then, a desired pattern is printed on the resist and developed to form a fine pattern with sufficiently high accuracy.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

First, FIG. 1 shows a process chart of the present invention. A resist film 2 is formed by applying a resist on the semiconductor substrate 1 and heating it (FIG. 1A). On the formed resist film 2, the first mask 3 is used to selectively irradiate near-ultraviolet light according to the pattern of the mask (FIG. 1B). The surface of the portion 4 (lower part of the step) irradiated with the near-ultraviolet light is developed and partly removed (FIG. 1C). As shown in FIG. 2, the first mask pattern 3 is a mask that shields from ultraviolet light by a Cr portion 6 which is a large area above the step. Further, at this time, the irradiation amount of near-ultraviolet light is changed by the difference in height between steps. A second mask 5 is used on the resist film 2 to selectively irradiate near-ultraviolet light according to the mask pattern (see FIG. 1).
(D)). The portion irradiated with the near-ultraviolet light is developed to form a pattern. The second mask 5 is for forming a wiring pattern for a bit or word line. When it is attempted to form this wiring pattern on a substrate having unevenness in a large area on the surface of the substrate, the difference in level is about 1.
If it exceeds 5 μm, pattern defects (bridge) occur above and below the step. Further, a pattern dimension variation of about 10% occurs above and below a step of about 0.2 μm. When the present invention is used, in the case of the above-mentioned step of 1.5 μm, pattern resolution becomes possible by removing the resist film thickness of about 0.5 μm. Further, in the case of the above step of 0.2 μm, by removing the resist film thickness of about 0.2 μm, the pattern dimension variation above and below the step is reduced to about 5% or less, which is halved. The step of 0.2 μm occurs when the gate pattern is formed, and the device characteristics can be improved by applying the present invention to this step.

[0008]

By using the resist pattern forming method of the present invention, it is possible to improve the pattern resolution above and below a step in a large area and reduce the pattern dimension variation above and below the step to about half.

[Brief description of drawings]

FIG. 1 is a process chart of forming a resist pattern of the present invention.

FIG. 2 is a plan view of the pattern of the first mask of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 resist film 3 first mask 4 irradiated portion 5 second mask 6 Cr portion

Claims (1)

[Claims] 1. A step of applying a resist film on a semiconductor substrate, a step of selectively performing a first exposure on the resist film using a first mask, and a step of performing the first exposure. A step of developing and removing a region, a step of performing a second exposure on the resist film using a second mask, and a step of developing the second exposed region Pattern formation method.