JPH06214538A - System and method for display of integrated video and graphic - Google Patents

Abstract

PURPOSE: To provide a computer system for providing an integrated video and graphic display including two individual buffers, i.e., one for video and the other for graphics. CONSTITUTION: Video data stored in the video buffer 40A and graphic data stored in the graphic buffer 40B may be different in the pixel depths. The data are transferred from the video buffer 40A to a video-processing path, and the graphic data are transferred to a graphic-processing path. The data may be transferred from the buffers at different speeds, so that the pixel transfer speeds along the processing paths are equal to each other. Pixels from the respective processing paths may be combined to generate integrated pixels for video and graphic displays.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer capable of displaying integrated video and graphics simultaneously on a single monitor.

An integrated video / graphics display on a monitor may be in the form of a full screen graphic window, having an insert window in which the video is displayed.

Current architectures for integrated video and graphics computers use a single buffer memory to temporarily store the integrated video image prior to display. This single buffer memory is a memory that constitutes a graphic buffer in a graphic dedicated computer.

When a single buffer is used to store the integrated video graphic image, the software complexity increases because the software must draw the video window in the graphic buffer before displaying it. The software is further complicated to make the video window movable and resizable within the graphics window.

A further disadvantage of the single buffer architecture is that the video and graphics signals are processed in a common path. This is only possible if the video and graphics have the same color resolution or depth. This eliminates the possibility of showing full color video at a resolution of 16 bits / pixel while displaying the graphic at 8 bits / pixel or less, for example.

A further disadvantage of the single buffer / common path architecture is that the same color palette or color lookup table is used for both video and graphics. Since the video and graphic signals are produced by different devices, it is entirely coincidental that one color palette provides faithful color rendering for both video and graphics. Adjustments to the color palette, of course, affect both video and graphics as well.

Clearly, an alternative architecture for integrated video and graphics computers is needed before the full potential of such computers is realized.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to a system for a computer that includes an architecture for displaying integrated video and graphics.

The system includes a video processing path for processing video data and a graphics processing path for processing graphic data. The video processing path includes a first buffer for temporarily storing the video data before it is processed and a means for processing the video data. The graphic processing path is a second path for temporarily storing graphic data before being processed.
Buffers and means for processing graphic data.

The system further includes means for combining the processed video and graphic data to form an integrated video and graphic display.

Each of the video data processing means and the graphic data processing means includes a color lookup table.

The video data processing means further includes means for formatting the video data into video pixels and means for formatting the graphic data into graphic pixels.

The system further includes means for transferring data from the first buffer to the video processing means at a first data rate and data for transferring from the second buffer to the graphics processing means at a second data rate. And means. The first and second data rates may be selected such that the formatting means form video pixels and graphic pixels at equal rates.

Choosing the video and graphics data rates to form video and graphics pixels at equal speeds means that on one monitor, even if the video and graphics have different color resolutions, the raw Allows you to view a graphic display along with full motion full color video.

Separate processing paths for video and graphics, each including a color look-up table, allow independent color processing of video and graphic pixels.

When no video is being displayed, the first and second buffers may be configured as a single graphics buffer, with only graphics being displayed on the monitor. The graphics processing path includes circuitry to support convolutional operations in the interleaved monitor when the video is not being displayed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, in which like components are designated by like identification numbers, FIG.
The system allows video windows and graphics windows to be displayed simultaneously on a computer CRT monitor.

The video window may appear overlaid on the graphics window so that the graphics under the video window are obscured. Alternatively, the window may be made to have a predetermined transparency level so that both the video within the video window and the graphics under the video window are visible.

In the preferred embodiment, system 20 is a personal computer (shown by dotted line 23) having a central processing unit (CPU) 25 which includes a microprocessor 27, eg, a 68040 microprocessor.

Referring again to FIG. 1, the system 20 includes two parts. The first portion 20A includes functional elements for processing video signals of different scan formats and color spaces into standard formats and color spaces. Certain of these elements may be found in prior art integrated video and graphics systems.

The second portion 20B contains the functional elements of a dual pass processing and integration system not found in prior art integrated video / graphics systems. Part 20A
Is included to show how the invention can interface with standard hardware.

Portion 20A of system 20 includes three video input ports. Port 22 is NTSC (National Television Standard Committee) or PAL
It receives analog video signals according to SECAM (European TV Standard) standard, port 24 receives video in Y, C (luminance, chroma) format, port 26 receives digitized video data in YUV format, and port 29 is micro. Provides access to the processor data bus 47. NTSC / PAL signal is AD
Digitized by converter 28, preferably a TDA8708 converter, the Y and C signals are A-
It is digitized by a D converter 30, preferably a TDA8709 converter. The outputs of the DA converters 28 and 30 are decoded by the SAA7191 digital multi-standard decoder. Video signal is color space converter and resizer (VD
C) Contact 34. VDC 34 outputs the video in RGB format and reduces the input video picture to a number and length of scan lines that matches a predetermined video window size.

Portion 20B of system 20 includes a VRAM system 40 arranged to facilitate dual pass processing of graphics and video. The VRAM system 40 includes a first buffer 40A and a second buffer 40A, respectively.
Buffer 40B, each buffer having a 32-bit wide input. Each buffer is 512 kilobytes (k
It has a capacity of either B) or 1 megabyte (1 MB).

For processing integrated video and graphics, buffer 40A is used to temporarily store video data and buffer 40B is used to temporarily store graphic data before the video and graphic data are processed. Used for. The bi-directional trans-receiver 46 allows the buffers 40A and 40B to be used together as a single memory dedicated to graphics, if the video integration function is not enabled. The data in each buffer 40A and 40B represents a matrix of picture elements, commonly referred to as pixels, to form a display or display window on monitor 36.

In the following description of the various elements for system 20, the term "pixel" will be used for differently shaped pixel data at different stages of pixel data processing. As used in the description below,
The term “pixel” refers to a sufficient amount of data to form a picture element (pixel) on monitor 36. Obviously, this data includes red, green, and blue components, which are addresses for color look-up tables, binary data representing color values, or analog signals to drive monitor 36. . The shape of the data will be apparent to those skilled in the art from the description.

The Color Palette and Digital Video Stream Mixer (VSM) 50 provides video and graphics integration capabilities including overlays at different levels of transparency. VSM 50 allows independent color control for video and graphics. The output 52 of VSM 50 provides an analog RGB signal to monitor 36 via an NTSC / PAL encoder and switch 54. In addition, outputs 56 and 58 of encoder 54
Provides integrated video and graphics to recorders or other terminals.

The controller 60 provides control commands to the system 20. This command is for buffer 4
Commands for loading and unloading 0A or 40B, commands for controlling integrated parameters in VSM 50, commands for interfacing system 20 with a microprocessor that generates graphic data, and sync signals for monitor 36. Including. Graphic data for input to buffer 40B or 40A is provided by the microprocessor along a 32-bit wide bus 47.

Having shown an overall view of system 20 and the interaction of the functional elements, a more detailed description of the elements that are important in providing the useful functionality of system 20 is provided below.

As mentioned above, system 20 includes buffers 40A and 40B, each of which can be accessed separately. Referring to FIG. 2, one array is shown, with buffers 40A and 40B totaling 102
Configured for 4kB capacity. The memory is arranged in two banks of four, a total of eight 128 kB
It includes an 8-bit VRAM block 42 (128kx8 block). Each block 42 is connected to a serial port (SAM) 43 for unloading data.
When video is enabled, video data is input through the 32-bit wide bus 41 and the serial port 4
Output from the VSM through the 32-bit wide bus 44
Given to fifty. The graphic data is input through the 32-bit width bus 47, output from the serial port 43, and sent through the 32-bit width bus 45 to the VSM 50.

Another arrangement of VRAM with a total capacity of 2048 kB is shown in FIG. Here, the total memory is eight 128kx, each connected to the SAM43.
Provided by two banks of 8 VRAM blocks 42. In this arrangement, the blocks 42 are connected in parallel in pairs, with each set of input connections connected to the bus 41. The output connection of each set is connected to the bus 44 via the SAM 43.

In FIG. 1, buffers 40A and 40A
B is all VRAM blocks 42 (FIG. 2 or 3)
Is a single block 42A (video VRAM) and 42B
(Graphic VRAM) shown collectively grouped. Similarly, all SAMs 43 (FIG. 2 or 3) are grouped as a single video SAM 43A or a single graphic SAM 43B.

The VSM 50 can directly interface with differently configured buffers 40A and 40B via two 32-bit wide buses without intervening circuit hardware. The manner in which VRAM 40 is configured and loaded is controlled by controller 60. The controller 60 effectively causes the different configurations and capacities of the VRAM 40 to be similar to the VSM 50.

The controller 60 has a video load clock input VLD and a graphic load clock input G.
LD, which controls the load rate of video and graphics data from VRAM 40 to VSM 50. The VLD and GLD clock frequencies are adjusted by the controller 60 independently of the graphic and video color resolution (bits or pixels per pixel or pixel depth) so that the pixel transfer rates of buses 44 and 45 are equal. In other words, if the graphics and video have different color resolutions, the video and graphics data rates are selected by controller 60 such that the video and graphics pixel rates through buses 44 and 45 are equal. When the video and graphic pixel frequencies are equalized, they can be integrated and manipulated by the VSM 50 to provide a predetermined display effect on the monitor 36.

It can be seen that the dual buffer architecture described above is an important part of providing color resolution independent signal processing functionality.

Another significant advantage provided by dual buffers 40A and 40B is independent control of the video and graphics windows. For example,
In prior art systems, the video window is written to the graphic VRAM to form an integrated screen display or window. Graphic VRA if the size or position of the video window has changed
M must be rewritten. This is a slow process,
Requires complex software.

In the system of the present invention, the graphic VR
Video windows can be resized or repositioned without affecting the AM. In the present invention, the video window is displayed just before each line is written to the monitor 36.
VSM50 integrates the graphics line by line. The screen coordinates of the four corners of the window specify the size and position of the window and are used for video and graphics integration. From these coordinates, signals are generated (by the controller 60) that tell the VSM 50 at which screen (scan) lines the video integration begins and at which scan lines the video integration ends.
Let us know. A signal is also generated that tells the VSM 50 at which pixel of the scanline to start video integration and at which pixel of the scanline to end.

With reference to FIG. 4, the functional elements of VSM 50 are described in further detail. A key element of VSM 50 is the pixel formatting pixelizer 10.
It is 0. Pixelizer 100 includes buses 44 and 45.
Receives video and graphic data from and formats the data into color look-up table addresses representing graphic or video pixels.

The clock inputs VLD and GLD and the graphic and video inputs to VSM 50 from buses 44 and 45 are input directly to pixelizer 100. The other input to Pixelizer 100 is line 1
02, a blanking signal from the controller 60, six control bits (D5: D0) from the control register 104, and a clock of the monitor clock 71 that determines the writing speed of the pixel (dot) on the monitor 36. Includes the frequency Dotclk. Monitor clock 7
Reference numeral 1 is a frequency synthesizer chip driven by an oscillator 73 and an oscillator 75. Oscillator 73 preferably has a frequency of about 14.318 megahertz (MHz) and oscillator 75 has a frequency of about 17.734 MHz. Clock chip 71 may be programmed to provide the correct Dotclk frequency for a wider range of monitor types.

Dotclk is used to generate the output signal Vidclk which is passed to the controller 60. Depending on the operating mode of the system 20, Vidcl
k has a frequency of the frequency Dotclk / 1 or Dotclk / 2, which will be explained in more detail below.

System 20 includes two separate pixel processing paths, one for video and one for graphics. The video pixel path output of the pixelizer 100 includes three 5-bit data outputs 106, 107 and 108 representing the red, green, and blue components of a 16-bit digitized video pixel, respectively, and 3 bits of grayscale video transparency data. (Least significant bit or L
SB) output 120.

Video pixel data is passed through multiplexers 110 and data latches 112 to form a video color palette, a video color look-up table (CLUT) 114, 116 and 1.
Passed to 18. CLUTs 114, 116 and 11
8 may be collectively referred to simply as a video color lookup table. Since color video in system 20 is always at the 16-bit level, and CLUT1
Since 14, 116, 118 are only used to store video color values, each has 32 5-bit values (3
Only 2x5) need be stored. Therefore, providing a separate video color palette is not recommended by the system 2.
It does not significantly increase the RAM cost of 0.

Continuing with the description of the video pixel (video data) processing path, the color lookup table 11
The RGB color values selected from 4, 116 and 118 are transferred to the transparency calculation logic circuits 124, 126 and 128 through the data latch 130, respectively. If grayscale video is displayed, CLUT 114,
116 and 118 are programmed to give grayscale values.

Transparency calculation logic circuits 124, 126 and 128 form the RGB components of the screen pixels that form the integrated display on monitor 36.
RGB of integrated video and graphic pixels
It is a component circuit. The transparency calculation logic circuit also includes circuitry for setting the transparency level. In addition, each circuit includes a multiplexer for combining the graphic and video pixel components. Transparency calculation logic circuits 124, 126
And 128 are described in more detail below.

Returning to the graphics path, there are four graphics path outputs from the Pixelizer 100, all 8 bits wide. Outputs 140, 142, and 14
4 is a value representing the RGB component of a true color graphic pixel. True color is 16 bits / pixel or 32 bits / pixel. Output 146 is a pseudo color output.

There are three multiplexers 150, 152, and 154 in the graphic path. The true color pixelizer outputs 140, 142, and 144 are connected in series to multiplexers 150, 152, and 154, respectively. Pseudo color pixelizer output 146
Are connected in parallel to multiplexers 150, 152, and 154. Multiplexers 150 and 15
2, and 154 have inputs from the address register counter 120, the purpose of which is described in more detail below. The outputs from multiplexers 150, 152, and 154 are passed through data latch 156 to CLUT 16
0, 162, and 164. CLUT16
0, 162 and 164 may be collectively referred to simply as the graphic color lookup table. Each C
LUTs 160, 162, and 164 can store 256 9-bit values (256 × 9). Of the 9 bits of a value, 8 bits specify a particular color and 1 bit specifies transparency.

In pseudo-color mode, the graphic color resolution is 2, 4, or 8 bits / pixel, ie 4, 16 or 256 different colors can be displayed. The RGB components of each pseudo color are stored at the same address location in each CLUT 160, 162, and 164. Therefore, only one address number is needed to specify the color. This address number is the output 146 of the pixelizer 100.
Is. As mentioned previously, the output 146 of the pixelizer 100 is connected to all three graphics multiplexers, and thus to all three CLUTs 160, 162 and 164.

Red CLUT1 in true color mode
Any one value stored in 60, green CLUT16
Any one value stored in 2, and the blue CLUT
Different address numbers may be provided to CLUTs 160, 162, and 164 so that any one of the values stored in 164 may be combined to produce one color.

Each CLUT outputs 9-bit color pixel data to one of the three data latches 168.
Each latch 168 passes 8-bit pixel data representing the red, green, or blue component of the pixel to one of the convolution calculation circuits 172, 174, and 176. Each latch 168 stores one bit of data representing a transparency value for video overlay into one multiplexer 178.
Hand over. The 3-bit transparency data is then passed to each of the three transparency calculation logic circuits 124, 126 and 128. Each convolutional logic calculator 172, 17
The 8-bit pixel data from 4 and 178 is
Passed directly to the transparency calculation logic circuits 124, 126, and 128, respectively.

Convolutional logic calculators 172, 17
The purpose of 4 and 178 is to prepare the pixel data for display on the television monitor. Television monitors typically have an interlaced display system. In an interlaced display system, two displays are provided sequentially, ie with sequential screen scans. 1
One scan contains only odd scan lines and the next contains only even scan lines. Both sets of scan lines are combined to form a single screen of information.

Convolutional logic calculators 172, 17
4 and 176 adjust the intensity pixels of adjacent odd and even scan lines so that the intensity of pixels in odd scan lines matches the intensity of adjacent pixels in adjacent even scan lines. This is apparent if the neighboring pixel intensities are not adjusted (sparklin
g) Reduce the impact. A further description of the convolution applied to system 20 is as follows.

In transparency calculation logic circuits 124, 126 and 128, video and graphic pixels (data) are integrated in a predetermined mode and passed to digital-to-analog converters (DACs) 180, 182 and 184, respectively. DAC 180, 18
2 and 184, the analog signal from amplifier 18
6, 188, and 190, respectively,
It is output along the connection 52 of the system 20 (see FIG. 1).

The above description is meant to generally illustrate the layout and functionality of the key elements of integrated video and graphics system 20 and how the components are interconnected. In the following, a more detailed description of how the key elements are constructed, how they work and how they interact is given. But before we get into the details
The physical configuration of 50 will be described.

All the elements of the VSM 50 shown in FIG. 4 are located on one chip packaged on a 100-pin PQFP (rectangular plastic quad flat pack with pins on all sides). Connections to pins are specified in terms used in the detailed description below.
A brief explanation of the terms is also given.

Dot Clock and / Dotclk: These are Emitter Coupled Logic (ECL) differential clock inputs used to clock video and graphics data through the VSM 50. Dotclk is a digital RGB, except when convolution is enabled.
Used to clock data to DACs 180, 182, and 184 (see Figure 1). When convolution is enabled, the digital RGB data is clocked into the DAC 180, 182, and 184 with dot clock / 4.

Vidclk: As mentioned above, Vi
dclk has a frequency of Dotclk / 1 or Dotclk / 2 depending on the display mode of the monitor 36.
Clock output equal to. Vidclk is used by controller 60 (see FIG. 1) as a state machine clock to generate display synchronization control signals such as VLD and GLD signals and signals for video window position on monitor 36.

/ Blank: The / Blank input serves two roles. Input data on the video data bus 44 and the graphic data bus 45 is loaded into the load clock V
Used to synchronize LD and GLD. In addition, the RGB output 52 is forced to a blank level. / Blank signal is video data input VDATA
Must be synchronized against. Therefore, R
To drive the GB output to a blank level / Blan
Before k is used, VSM 50 must delay / Blank by an amount equal to the time it takes for video data to travel from VDATA input of pixelizer 100 to DACs 180, 182, and 184 (pipeline delay). The / Blank signal defines the active portion of the display scan line of monitor 30. / Blan
When k goes low, the VSM 50 must blank its RGB outputs, even if there is undisplayed data in the pipeline.

VDATA 31: 0 (digitized video data bus): The video data bus is VDATA 3
Input to shift / select the logic of the pixelizer 100 via the 1: 0 input. Input data is VLD
Latched on the rising edge of (video load clock). These inputs have internal pull-up registers.

GDATA 31: 0 (digitized graphic data bus): The graphic data bus is GD
Input to shift / select logic of pixelizer 100 via ATA 31: 0 input. Input data is latched on the rising edge of GLD (Graphics Load Clock). These inputs have internal pull-up registers.

VLD (Clock): VLD is an input that serves two purposes. If / Blank is high (active video), the rising edge of VLD latches 32 bits from the VDATA input bus. The VLD input toggles only if the input has valid data. If / Blank is high and the VLD input is not toggling, the pixelizer shifts the binary one into the video processing path. This forces only the graphics to be displayed, no matter what transparency data is being transmitted to the graphics data.

If / Blank is low, the VLD input carries control code (logic 1) 1 from control register 104,
This is captured at the first rising edge of Vidclk after detection of horizontal blanking. The control code of the control register 104 will be described in more detail later.

GLD Clock: GLD is an input that serves two purposes. If / Blank is high (indicating active video), the rising edge of GLD latches 32 bits from the GDATA bus.

If / Blank is low, the GLD input is
The control code 0 is carried from the control register 104. This code is caught on the first rising edge of Vidclk after detection of horizontal blanking.

/ CS (Chip Select): The VSM 50 on-chip registers 198, 120, 194, 104, and 196 are accessed by asserting Chip Select.

R / W (read / write): Read / write input is used when accessing an on-chip register. When high, it reads the internal registers; when low, they are written.

RS1: RS0 Register select: / C
These two register select inputs are used to select which on-chip register is accessed when S is asserted.

D7: D0 (Data Bus, Input and Output): Data for on-chip register access is carried by the D7: D0 signal.

R red output (analog output): red D
Analog output from AC180. This output is RS-3
It is preferably possible to drive a 43 compatible level into a double ended 75Ω cable.

B blue output (analog output): blue D
Analog output from AC182. This output is RS-3
It is preferably possible to drive a 43 compatible level into a double ended 75Ω cable.

G green output (analog output): green D
Analog output from AC. This output can preferably drive an R5543 compatible level into a double ended 75Ω cable.

VREF Reference Voltage (Analog Input): An external reference is input to the reference amplifier via this pin.

IREF Reference Current (Analog Output): A precision register (not shown) connected to this pin and grounded sets the output current of the DACs 180, 182, and 184 to a predetermined level.

As mentioned above, system 20 may be an integrated video and graphics computer system. The computer provides integration and color control functions, and the user of computer 23 selects the graphic color resolution, selects the desired color temperature for the graphic, enables or disables integrated video, selects transparency, and transparency. Allows you to choose a level. The digital signal representing the selection is sent directly or indirectly to the CPU2 via the pin connections described above.
5 to the internal registers of VSM 50.

Referring again to FIG. 4, address register counter 120, color and transparency data register 19
4. Control register 104 and signature analysis and test register 196 are accessed via pins D0: D7. Data is input to and read from these pins directly from the microprocessor via the 8-bit wide microprocessor bus 47 (see FIG. 1). In the VSM50, these signals are
It is carried through a bidirectional 8-bit wide bus 192.

Referring again to FIG. 4, the timing and coding register 198 is accessed by pins / CS, R / W, and RS0: RS1. Data is sent from controller 60 to these pins (see FIG. 1). The signals on these pins depend on which data is on the bus 192
, And from which of the registers 120, 194, 104 and 196 the data will be written or read. Table 1 shows the function of these signals in different combinations of binary states.

In Table 1 (and other tables below),
The bit state "X" indicates that the bit is a logical 1 or a logical 0 without affecting the logic circuit decision. These bits are commonly referred to as "don't care" bits.

[0076]

[Table 1]

Next, the color data video CLUT 11
4, 116, and 118 and graphic CL
Reads and writes to UTs 160, 162 and 164 are described. Color data may be written or read from these CLUTs by the programmer. Graphic CLUTs 160, 162, and 16
The contents of 4 may be modified by the software used in the computer for synthesizing color graphics. Such software is commercially available and comes with one or more customized color palettes. Graphic CLUT 160,16
The contents of 2, and 164 may include data for changing the color temperature of the display and data for linearizing the gamma curve of the RGB screen phosphor of monitor 36.

In certain graphic display modes, the transparency data is CLUT 160, 162, and 1
64 may be included. This data is CLUT16
Included in the 9th bit of each register of 0, 162, and 164, the other 8 bits of each register are reserved for RGB color values. The following steps describe writing a data transfer to or reading from a video or graphic CLUT. The transparency control will be described in more detail later.

When writing to the CLUTs 160, 162 and 164, the control register 104 is selected with RS1, RS0 = 10 and R / W = 0 and the data on the D7: D0 pins to the control register on the first rising edge of / CS. Be clocked. Bit D6 must be 0 to select the graphic CLUT. Address register 12
0 is selected by RS1, RS0 = 0 and R / W = 0 and the address on the D7: D0 pin on the rising edge of / CS is clocked into the address register 120.

At the second rising edge of / CS, R
(Red) Data is written from D7: D0 to a temporary register (not shown). On the third rising edge of / CS, write G (green) data from D7: D0 to a temporary register (not shown). On the fourth rising edge of / CS, write B (blue) data from D7: D0 into the temporary register. On the fifth rising edge of / CS, transparency data is written from D7, D6, and D5 to CLUTs 160, 162, and 164, respectively. RGB data stored in the temporary register is CL
Written to UTs 160, 162, and 164, respectively. Next, the address register 120 is incremented.

The transparency data includes 3 bits, and D7: D
Transferred to and from VSM 50 with 5 data bus bits.

When reading from CLUTs 160, 162, and 164, control register 104 reads RS1, RS0 =
10 and R / W = 0, on the rising edge of / CS, the data on the D7: D0 pins is clocked into control register 104 and bit D6 is set in CLUT16.
Must be 0 to select 0, 162, and 164. Address register RS1, RS0 = 0
0, and R / W = 0, clocks the address on the D7: D0 pin into the address register 120 on the first rising edge of / CS. On the second rising edge of / CS, RGB and transparency data is read into a temporary register (not shown) and red data is
Within the access time of about 50 nanoseconds (50 nS),
D7: Appears on the D0 bus 192. On the third falling edge of / CS, drive G data from one temporary register onto the D7: D0 bus 192. The fourth falling edge of / CS drives the B data from another temporary register to D
7: Drive to D0 bus 192. On the fifth falling edge of / CS, the transparency data is driven D7: D0 and the address register is incremented.

When writing to CLUTs 114, 116, and 118, control register 104 uses RS1, RS0 = 1.
0 and R / W = 0, the rising edge of / CS clocks the data on the D7: D0 pins into control register 104. CLUTs 114, 116, and 118
Bit 136 must be a 1 to select the. The address register 120 has RS1, RS0 = 0.
0 and R / W = 0, the rising edge of / CS places the address on the D7: D0 pin at address register 1
Clock to 20. The third rising edge of / CS is
D7: Write R (red) data from D3 to a temporary register (not shown). On the fourth rising edge of / CS, the G (green) data from D7: D3 is written to a temporary register (not shown). On the fifth rising edge of / CS, the B (blue) data from D7: D3 is written to the blue CLUT 118 and the red and green data stored in the temporary register are written to the red CLUT 114 and green CLUT 116, respectively.

When reading the CLUTs 114, 116 and 118, the control register 104 sets RS1, RS0 = 10.
At the rising edge of / CS, the data on the D7: D0 pin is controlled by control register 1
Clocked at 04. Bit D6 must be 1 to select the video CLUT.

The address register 120 has RS1, RS0
= 00, and R / W = 0, on the first rising edge of / CS, the address on the D7: D0 pins is clocked into the address register 120. On the second falling edge of / CS, RGB and transparency data is read into a temporary register and red data is about 50 nS.
Appears on the D7: D3 bus within the access time of. On the third falling edge of / CS, green data is driven onto buses 192 at D7: D3. On the fourth falling edge of / CS, the blue data is on bus 192 at D7:
Driven by D3. Reading the video CLUT is D
2: Returns 0 at D0.

Continuing to refer to FIG. 4, the control register 104
Contains 8-bit data. These bits are provided to the control register 104 by the CPU via pins D7: D0 in response to user selection. The three bits D2: D0 control the graphic pixel depth (graphic resolution), the three bits D3: D5 configure the input mode of the pixelizer 100, and one bit D6.
Is a CLUT 160, 162, and 164 or a CLU
Select either T114, 116, or 118,
One bit D7 selects overlay enablement. The preferred bit state layouts are shown in Tables 2 and 3.

[0087]

[Table 2]

[0088]

[Table 3]

As mentioned above, the pixelizer 100
The frequency of the Vidclk output from is equal to Dotclk / 2 or Dotclk / 1. Figure 5 shows Vidclk
Control bit D of control register 104 that determines the frequency
5: shows the state of D0. FIG. 5 further illustrates VLD and G
How the frequency of the LD input is in the control register 104
Indicates whether it correlates to a bit.

Having described the signals used to control the VSM and the origin of these signals, the function of the pixelizer 100 will be described in more detail with reference to FIGS. 4 and 7.

Pixelizer 100 (see FIG. 4) has buffers 40A and 40A in a predetermined mode controlled by the above signals from control register 104.
Used to format the input data from B. As mentioned above, video and graphics data, and graphics data only
Pixizer 1 with bit wide VRAM buses 44 and 45
Enter 00. When both video and graphics are selected, video is on bus 44 and graphics are on bus 45. If only graphics is selected, then the graphics are on buses 44 and 45. As mentioned above, the pixelizer 100 receives the data bits D5: D0 from the control register 104 to determine how to handle the data on the buses 44 and 45.
The manner in which these control register bits are interpreted by the pixelizer 100 is described in detail below.

Controlling transparency in video and graphic overlay modes is a key function of Pixelizer 100. Pixelizer 100 receives or directs the transparency data contained in the incoming signal. Therefore, before beginning a further description of the Pixelizer 100,
The signals involved in controlling overlay transparency and the sources of such signals are described next.

Transparency control data for controlling the video / graphics overlay display is communicated to the VSM 50 in a number of ways, depending on the operating parameters specified by the computer user.

The transparency data is communicated in the form of upper 3 bits of data as a graphic and 1 bit of video. These are referred to as alpha bits for the following description. There are two sources of alpha bit,
There are graphic pixels and video pixels. If the pixel depth bits of control register 104 are set to pseudocolor (D2 = 0), the sources of graphic alpha bits are CLUTs 160, 162, and 164, and one bit is read from each of the three CLUTs. . If the graphic pixel depth bit is set to true color (D2 = 1) then the alpha bit is at the pixel data input to the VSM 50. For 16 bits / pixel, there is only one alpha bit and the other 15 bits carry RGB color data. If the alpha bit is 0, the alpha value is set to 000, and if the alpha bit is 1, the alpha value is 1.
Set to 11. The VSM 50 does not support 32 bits / pixel for video at the same time.

Video data has two formats, 16
It is input to the VSM 50 in one of the formats: true color of bits or gray scale of 8 bits.
For 16-bit true color, there is one alpha bit. For 8-bit grayscale, there are no alpha bits. In this case, video alpha is assumed to be zero.

Table 4 shows the overlay control bit states and alpha bit states required to provide various transparency levels and video / graphics integration modes.

[0097]

[Table 4]

16-bit graphic pixel with only one alpha bit: if the alpha bit is 0, the graphic alpha is 000; if the alpha bit is 1, the graphic alpha is 111.

The graphic video overlay is
It can be incremented by the VSM 50 in "chroma keying" mode. In chroma keying, the video object is filmed against a simple background of a predetermined color.
ed) may be done. The video may be programmed so that no background color is recorded. The video can be overlaid on the graphic so that only the video object is visible, ie the video does not appear in a rectangular window, only the shape and content of the object is visible. An everyday example of chromakeying is a television meteorologist who is synthesized against the graphics of a weather map.

In system 20, VDC 34 may be programmed with a range of YUV coordinates including the key (background color). If the incoming video signal to VDC 34 is within the key color coordinate range, alpha bit 1 is V
In the data transmitted to the RAM 42A, emphasis (impres
sed). Video alpha bit 1 (see Table 4)
Makes the video completely transparent, so only the graphic is displayed in the background area of the video.

As discussed above, the transparency calculation for determining the value of the integrated video / graphic pixel is performed by the transparency calculation logic circuits 124, 126 and 12.
Performed by 8. The manner in which these circuits perform calculations is described next.

Three transparency logic calculation circuits 124 and 126
And 128 respectively, the graphics pixel is multiplied by a predetermined transparency factor, the video pixel is multiplied by that factor minus one, and the factored video and graphics pixels are added,
The result is an integrated video / graphic pixel. Factoring may be done using conventional multiplication circuits. However, such circuits are complex and expensive, even for relatively simple multiplication operations. Therefore, a set of transparency factors is selected so that the factoring can be accomplished using binary shifts in much the same way that decimal numbers are factored to 10,100, etc. by moving the decimal point. It has been found preferable to do so.

A block diagram of a transparency logic circuit of 1 is shown in FIG. The transparency logic circuit 124 is shown here,
The transparency logic circuits 126 and 128 are essentially the same. Transparency logic circuits 124, 126 and 128 are circuits in which a transparency factor is added to video and graphics pixels to combine the video and graphics processing paths within VSM 50.

The transparency logic circuit has an 8-bit wide input 91.
And a video dual shift path logic circuit 90 having two 9-bit wide outputs 92A and 92B. In the dual circuit shift path logic circuit 90, 8-bit data is shifted once or twice and divided by 2, 4 or 8. The shifted data is output on either or both outputs 92A and 92B.

The transparency logic also has an 8-bit wide input 9
Includes a graphic dual shift path logic circuit 94 having 5 and 2 9-bit wide outputs 96A and 96B.
In this double circuit shift path logic circuit 94, 8-bit data is shifted once or twice and divided by 2, 4 or 8. The shifted data is output to either or both of outputs 96A and 96B. Video and graphic pixel factoring is 9
Bit adders 93A and 93B. The 9-bit adder gives the maximum rounding error of the least significant bit of 1 plus the normal truncation error (for data shifted twice). Censoring error is 0.25 / 0.75 or 0.375
Occurs at a scale ratio of /0.625. 0/1 or 0.
No error occurs at a ratio of 5 / 0.5.

After the graphic and video pixels have been factored, they are added to the 9-bit adders 93A and 93A.
Each of the Bs is distributed to a separate 9-bit adder 97, where they are combined to form a pixel of the integrated video / graphic display.

For example, to provide an integrated video and graphics pixel with 25% video and 75% graphics, the data for the graphics pixel is shifted twice in the dual shift path logic block 91. Divide by 4 and adder 93 from output 92A
Is transmitted to A. Output 92B transfers the logic 0 of adder 93A. The graphic pixel data is shifted once in the double shift path logic block 94 and divided by 2,
The result is transmitted to the adder 93B via the output 96A. The graphic data is then shifted a second time and divided by 4, and the result is transferred to adder 93B via output 96B. The results obtained by shifting once and twice are added by the adder 93B to obtain 0.75 (1/2 + 1 /
4) Give the factored graphic pixel data. The video pixel data factored by 0.25 and the graphic pixel data factored by 0.75 are added in adder 97 to provide integrated pixel data, which is provided to DAC 180 (see FIG. 1). . Next, the Pixelizer 100 will be discussed, focusing on how the addresses of the color lookup table are handled. Address of register in CLUT, ie RAM where color values are stored
The color value is obtained by giving the address to the CLUT. CLUT address is Pixizer 100
By describing how it is oriented by
Start the discussion.

Referring to FIG. 8, pixelizer 100 captures data from VDATA and GDATA input buses 44 and 45, formats the data, and outputs the CLU.
Graphic CLUT for T114, 116 and 118
Drive addresses 160, 162 and 164. Pixelizer configuration bit (D from control register 104
5: D0) determines how pixelizer 100 handles the data coming in from VDATA and GDATA buses 44 and 45 according to the example described below.

If control register bit D4 is 0, the video input is disabled and buses 44 and 45 are configured for 64-bit graphics. As mentioned above,
When the video input is disabled, a logical 1 is shifted into the video pipeline (processing path). This forces the video alpha bit to 1 so that the graphic is always displayed.

If control register D4 is 1, video input is enabled. The address for the video lookup table is 8-bit grayscale (control register D3
= 0) or 16-bit true color (control register D
3 = 1),
VSM on BDATA bus 44 on rising edge of VLD input
Enter 50. If the VLD input does not toggle, only graphics will be displayed.

If the digitized video data coming into the VSM 50 is formatted as 8-bit grayscale, each of the CLUTs 114, 116 and 118 will receive the same 5-bit address. The upper 5 bits of the 8-bit grayscale code are used as the lookup address and the lower 3 bits bypass the lookup table. The 3 least significant bits are the opposite video (white on black) grayscale format,
(Hexadecimal 0) $ 00 is white, and (Hexadecimal 25
5) Since $ FF is black, it is inverted.

If the digitized video data coming into the VSM 50 is formatted in 16-bit color, the address to the video lookup table is 1-5-5-5, as discussed above. It will be in (alpha-R-G-B) format.

Continuing with the description of the graphic color lookup address, CLUTs 160, 162 and 16
4 can operate in true color or pseudo color mode. If operating in pseudo color (control register bit D2 = 0) mode, the same address is used for these 3 CLUTs. If true color mode (D2
= 1), RGBCLUT 160, 16
The addresses for 2 and 164 will be different from each other.

If the control register D4 is 1, video input is enabled and the pixelizer 100 is GDATA.
Configured to receive graphics only on the 31: 0 bus. In this case, the VLD and GLD clock frequencies will be different from each other if the digitized video and graphic pixel depths are different.

As mentioned above, if the control register D4
If 0, the video input is disabled and graphic data enter VSM 50 on both the VDATA 31: 0 and GDATA 31: 0 buses. In this case, D
The LD and GLD clocks have the same frequency, and graphic data are VDATA31: 0 and GDATA3.
Interleaved at longword boundaries between 1: 0 buses (a longword is 32 bits). Even longwords enter the VSM 50 with GDATA 31: 0 and odd longwords enter with the VDATA 31: 0 bus.

Referring to FIG. 9, if the graphic operates at 8 bits / pixel, the load clock VL
The rising edges of D and GLD will capture 64 bits or 8 pixels. Leftmost 4 pixels LP
N and LP (N + 1) enter on the GDATA 31: 0 bus and the right four pixels RPN and RP (N
+1) enter with VDATA 31: 0 bus.

Returning to the Pixelizer 100 description, once the data is captured from the VDATA or GDATA buses 44 and 45, it must be formatted for presentation to a video or graphic color lookup table. 32 formatting
Achieved by bit-width first rank latches,
This is discussed in detail below in connection with the convolution method. Briefly, the data captured in the 32-bit wide first rank latches of the Pixelizer 100 is sequentially extracted from the latches in groups of 1, 2, 4, 8, 16 bits until the latch is empty. Will The extraction sequence is controlled by the code mentioned above.

As discussed above, there are two basic color modes: pseudocolor (1, 2, 4, or 8).
There are bit / pixel and true color (16 or 32 bit / pixel) modes. Formatting of 1-bit / pixel pseudo-color pixels is illustrated in tabular form in FIG. Here, the band of the data DN1 including 32 bits D31: D0 is captured by the pixelizer 100. From this data, 31 8-bit CLUT addresses (A7: A0) are formed. Bits are sequentially extracted from the data starting with D31, CLU
It is located in the most significant bit position A7 of the T address.
The remaining 7 bits of the address are filled with logic ones.
For example, bit D31 appears at address OB1, bit D30 appears at address OB2, and so on.
Two CLUT addresses are formed. The next line of data D (N + 1) 1 is captured by the pixelizer 100 and the sequence described above is repeated.

Referring to FIG. 11, 2-bit / pixel pseudo-color formatting is illustrated. Here, the band of the data BDN1 including the bits D31: D0 is captured by the pixelizer 100 and the bits are extracted two at a time and positioned at the CLUT address. For example, bits D31 and D30 are located at A7 and A6 of CLUT address TV1, respectively, and bits D29 and D28 are at A7 and A of CLUT address TV2.
16 and C, and so on.
LUT addresses are formed, each of which is in band VDN1.
2 bits from, and 6 logic ones.

Referring to FIG. 12, pixel formatting of 4-bit / pixel pseudo color data is illustrated. Here, the bits are extracted four at a time from the captured data band VD1 to form a total of eight CLUT addresses, each of which is four bits from VDN1 and four.
Contains 1 logic one. In FIG. 13, the formatting of 8 bits / pixel pseudo color data is shown. Here, each CLUT address contains 8-bit data from VDN, for example address EB1 is bit D3.
1: D34 included, address EB2 contains bits D23: D
Including 16 and so on.

Continuing the discussion of pixel formatting of true color pixels, 16 bit / pixel formatting is shown in FIG. From the band of data D31: D0 (not shown), bits D31: D16 are used to form the data for the first (left) pixel and bits D15: D0 are used for the second (right adjacent). Used to form a pixel).

From the incoming data band, the bit D31 containing the alpha data for the left pixel is first extracted, bits D30: D26, D25: 21, and D.
20: D16 are extracted to form RGB CLUT addresses A7: A0, respectively. In each CLUT address, bits A7: A5 are logic 0, and bit A
4: A0 is 5 bits from D30: D0, for example the red CLUT address of the left pixel is D30: D2
Including 6.

After the left pixel is formed, the bit D15 containing the alpha data for the right pixel is extracted. Bits D14: D10, D9: D5 and D
4: RGB C for D0 then the pixel to the right
It is used to form each LUT address.

Referring to FIG. 15, pixel formatting for 32-bit true color pixels is shown. In the band of data D31: D0 (not shown) including pixel data, bits D31: D29 are held as alpha data, and the red CLUT address is bit D2.
3: D16, the green CLUT address is formed from bits D15: D8, and the blue CLUT address is formed from bits D7: D0.

If control register bits D4: D3 = 10
Then, the video data to enter into VSM50 by VDATA bus is 8-bit reverse video (white on black) grayscale format, where $ 00 is white and $ FF
The bits are flipped so that is black. In this grayscale video format, the three LSBs of pixel data contain alpha data. The three bits are extracted and inverted by inverter 113 (see FIG. 8) and then the video CLU shown in FIG.
Bypassing T is provided to transparency logic circuits 124, 126 and 128. The remaining 5 bits of data form a single CLUT address, which contains 3 video CLUs.
Given to all of T114, 116 and 118.

FIG. 6B illustrates how monochrome video 5-bit color data is connected from the latch 130 to the transparency logic block. Bits 7, 6,
5, 4 and 3 are connected to the corresponding inputs of the transparency block 124, while the transparency LS from the pixelizer 100.
B is connected to transparency block 124 at inputs 1, 2 and 3.

Referring to FIG. 6A, the connection of color video color components is shown. Here, bits 7, 6 and 5 from latch 130 are connected to both inputs 7, 6 and 5 and inputs 0, 1 and 2 of transparency block 124. This is done to evenly spread the 5-bit color component over the 8-bit color component range.

Next, it will be described how the pixelizer 100 is configured for graphic convolution. As briefly mentioned above, convolution is a filtering operation performed by each of the convolutional logic circuits 172, 174 and 176 of VSM 50 (see FIG. 4). The purpose of convolution is to minimize flicker between lines resulting from high contrast images on adjacent lines of an interlaced display.

The convolution operation requires both buffers 40A and 40B (see FIGS. 2 and 3). VS
M50 connects the two buffers via GDATA and VDATA buses 44 and 45. Since both buffers 40A and 40B are required, convolution is achieved only when 32-bit buses 44 and 45 are configured as a single 64-bit bus and graphic data is transferred over both buses. Therefore, no convolution will be realized when displaying the video.

When convolution is enabled, the convolution calculation logic 172, 174 for each of the RGB pixel components.
And 176 perform the calculation. The calculation is as shown in equation (1) below:

[0131]

[Equation 1]

Here, Pr, g, and b are RGB primary values, and Nr, g, and b are RGB values of pixels on the displayed line. [Nr, g, b-1] is a line immediately above the line N. This is the RGB value of the pixel directly above the pixel being displayed.

[Nr, g, b + 1] is a line immediately below the line N. This is the RGB value of the pixel immediately below the pixel being displayed.

The integer 2 in the numerator of equation (1) gives the result of rounding. Convolution requires that vertically and horizontally adjacent pixels be presented to the VSM 50 at the same time. The number of horizontal pixels that can be calculated by the load sequence ranges from 4 to 32 depending on the pixel depth. The number of vertical pixels captured by the load sequence is always three. In reality, four are presented to VSM50, but one of them is ignored.

The convolutional realization involves VSM50 by the time data from 3 vertically adjacent pixels and 4 or more horizontally adjacent pixels are provided to the video pipeline for processing. Needs to be captured in.

In VSM 50, convolution is limited to operate in pseudo color mode only. In the examples described below, it is assumed that the graphics occur at 8 bits / pixel, but convolution can be used in 1, 2, 4 or 8 bits / pixel pseudo-color modes. If the graphics are generated at 8 bits / pixel or less, the amount of data captured by the pixelizer on each load does not change, but more horizontal pixels can be calculated for each load.

When convolution is enabled, scan line pairs are mapped into buffers 40A and 40B, as shown in Table 5. Rolling VRM is controller 60
(See FIG. 1).

[0138]

[Table 5] Each line pair is a longword interleaved as shown in FIG. The frequencies of VLD and GLD are equal.

Referring to FIG. 17, an array of data latches of pixelizer 100 is shown. The latch operates as follows. On the first rising edge of VLD and GLD, the first longword containing the first 4 pixels of line 0 is latched from the GDATA45 bus into the first rank latch 70, and the first 4 pixels containing the first 4 pixels for line 2 are latched. Two
Longwords are latched from the VDATA bus into the first rank latch 72. On the second rising edge of VLD and GLD, the third longword containing the first four pixels for line 1 is latched 70 from the GDATA bus.
And the fourth longword containing the first four pixels for line 3 is latched from the VDATA bus to latch 72.

At this point, there is enough data in the pixelizer 100 to calculate four adjacent pixels. V
SM50 now has data for pixels 0, 1, 2 and 3 on lines 0, 1, 2 and 3. Since the convolution calculation includes only three vertically adjacent pixels (see equation (1)), the pixelizer 100 has four longwords latched in the first rank latches 70 and 72. One of them is discarded and the remaining three are latched into the second rank latch 76 (A-F) via multiplexer 69 according to the procedure detailed below.
Multiplexer 69 and latches 70, 72 and 76 are controlled by signals from control logic block 67. Two sets of latches are needed. This is because the second rank latch 76 is needed to supply the video pipeline while the data is captured in the first rank latches 70 and 72. For convenience of this description, an arrangement including six second rank longword latches (A-F) is described. However, it will be apparent to those skilled in the art that other second rank latch arrangements are possible to maintain the functionality required for the convolution operation.

The order of the data on the GDATA and VDATA buses 44 and 45 varies from video field to video field and from line to line within the field. VS
M50 is shown as control code 1: 0 in FIG.
The bit code gives information about this order.
These control code bits are VLD during blanking.
And to the GLD signal. / Blan
The k (high or low) input is used as a demultiplex control signal. This is possible because the control code is updated only once per scan line. If / Bla
If nk is high, the VLD and GLD inputs are used to latch the video data into first rank latches 70 and 72. If / Blank is low, control codes 1: 0 are encoded on the VLD and GLD inputs as shown in FIG.

Control Code 1: 0 inputs are from line N which of the four longwords captured in the first rank latches 70 and 72 and which are N-1 or N.
It is from +1 and determines which should be discarded. The correlation between pixels N-1, N and N + 1 and control code 1: 0 is shown in the tables of FIGS. 9, 20 and 21, which are the first few lines of the even and odd fields of the interlaced display. It is a summary of how the convolution is performed with reference to. In the table,
LEA, LEB ... LEF refer to the latch enable signals shown in FIG.

Returning to the discussion of video and graphics integration in VSM 50, the timing relationship between the 32-bit input for VDATA and the 32-bit input for GDATA is illustrated (first rank latch 70 and FIG. 17). 72). As discussed above, the input operates in two modes. That is, an independent load clock signal VL
D and GLD have the same or different frequencies,
As dual 32 bit inputs or GLD and VL
D has the same frequency and operates as a single 64-bit input. The input behavior will be specified by the following rules.

/ Blank, VLD and GLD timings are for Vidclk. Vidc
The frequency of lk depends on the operating mode of the system 20 and D
equal to otclk / 1 or Dotclk / 2,
This means that the / Blank resolution is 1 or 2 pixels.

Referring to FIG. 22, an example of an integrated video graphic display on monitor 36 and / Bla
A timing diagram of the nk, GLD and VLD signals is shown. This display shows a black (blank) background 81, a graphic window 83 and a graphic window 83.
Including a video window 85 overlaid on. A stream 87 of pixels from the GLD defines scanlines for the graphics window 83 and a pixel stream 89 defines scanlines for the video window 85.

It should be noted that the window layout of FIG. 22 was chosen as an example of how an integrated video graphics system would typically be used. Of course, other window arrangements are possible. For example, the video window may be sized for the VDC 34 to fill the entire space of the screen, or it may be displayed along with the graphics window.

The time / Blank is high defines the active line time. If / Blank is high, valid pixels from / Vla for a time interval equal to VSM50's internal processing delay (pipeline delay).
It is delayed and output from nk.

The VLD and GLD signals are / Blank
Data can be loaded into the VSM 50 only while is high. Furthermore, with the first rising edge of GLD,
/ Blank rising edge must occur within the same Vidclk cycle. In all of the above examples and the examples discussed below, the first rising edge of GLD and the rising edge of / Blank occur at the same time.

The / Blank signal indicates that all of the data loaded by either VLD or GLD is VSM.
It will transition from high to low before being processed and displayed via 50. In this case, the data present in VSM 50 when / Blank goes low is discarded and not displayed. Therefore, the falling edge of / Blank defines the end of the scan line, not the amount of data loaded into the VSM. For example, in FIG.
Data for each graphics pixel is / Blan
loaded into VSM50 at times when k is high, but /
Only 10 pixels are displayed because Blank is high for 10 Vidclk cycles.

A / Blank falling edge defines the end of a scan line, while a scan line may contain both graphic and video pixels. Therefore, additional rules are needed to define the boundaries of the video window.

The left edge of the video window is defined by the first rising edge of the VLD, the first rising edge after the VLD toggles to allow graphic data into the VSM 50. The right edge of the video window is defined by the last rising edge of VLD or the falling edge of / Blank, whichever occurs first.

The reason why the VSM 50 needs to detect a video window with a graphics dependent signal is that within the video window alpha bits will be used to mix video and graphics. Outside the window, the graphic information is displayed regardless of the alpha value.

Referring to FIGS. 23, 24 and 25, three examples of timing relationships that occur when video and graphics are loaded simultaneously are shown.

In FIG. 23, control register bit D
5: D0 is set to 16-bit video, 16-bit graphics, non-convolutional, graphic alpha is logic 111, video alpha is logic 0. These values cause the video to be displayed if it is there. The video window is at the left end of the scan line.

In FIG. 24, control register bit D
5: D0 is set to 16-bit video, 16-bit graphics, non-convolutional, graphic alpha is logic 111, video alpha is logic 0. These values cause the video to be displayed if it is there. The video window is offset from the left edge by one Vidclk cycle.

In FIG. 25, control register bit D
5: D0 is set to 16-bit video, 16-bit graphics, non-convolutional, graphic alpha is logic 111, video alpha is logic 0. These values cause the video to be displayed if it is there. The video window is at the right end of the scan line.

In all of the above examples, the "transparency block" or "transparency logic" is the transparency logic circuit 17 of FIG.
It is a collective term referring to 2, 174 and 176.

Referring again to FIG. 1, a very important element of integrated video graphics system 20 is controller 60. Controller 60 is a hardware controller for a computer, including system 20, which supports video input and output integrated with computer graphics. Controller 60 is a VRAM for one or two microprocessors in the computer
It provides an interface with 40 and configures the VRAM in two forms. That is, either as a single buffer for high resolution graphics, or one for video and the other as double buffers for graphics. The controller 60 simultaneously includes VRAM address generation,
Color space converter resizer to VRAM (V
DC) 34 to control the flow of incoming video, control the transfer of data from the video VRAM and graphics VRAM for display, control all display timing parameters for the monitor, refresh VRAM. Arbitrates the use of VRAM. The controller 60 provides hardware window control of the scaleable video window, which includes independent color depth support for video and graphics and video window positioning.

The functional elements or circuit blocks of the preferred embodiment of controller 60 and their connections are illustrated in block diagram form in FIG. 26 and are described below. FIG. 26
All functional elements shown in the block diagram are integrated on a single chip. Inputs and outputs to the controller are directed to various elements via connection pins, generally indicated by the name they represent the signals they carry.

The bus interface block 300 is V
RAM 42A or VRAM 42B (see FIG. 1)
Or the control register block 302 (see FIG. 26).
Receive all the microprocessor signals needed to detect a request for access to. The bus interface 300 decodes these address ranges,
Either give a VRAM access request to the address multiplexer block 304 or complete the access to the control register 302. Preferably, VRAMs 40A and 40B (see FIG. 1) are $ 5010 000 and $ 5010 000.
502F FFFF is mapped. Control register block 302 is preferably $ 5003 600
Mapped between 0 and $ 5003 7FFF.

The incoming signals to the bus interface 300 include the signals TS, TT1 and SIZ, which respectively indicate the start of the transfer of the VRAM data block from the CPU and what type of data should be transferred. And the size of the R / W data block to be transferred. A31: A26 and A21: A0
Is a register address received from the CPU 25 via the processor address bus 47. The bus interface 300 decodes these addresses, and the CPU
25 determines whether it is requesting communication with the register block 302 or direct communication with the VRAMs 40A and 40B. Bit D0 allows transfers to and from the processor address bus and TA confirms that data has been transferred. MAS
TER indicates which of the two processors in the CPU should be accessed.

The clock signal input from the clock on the board in the CPU transfers data to the VRAM banks 40A and 4A.
Pclk for clocking 0B and Bclk which is a CPU bus clock for communicating data between the controller 60 and the CPU are included. Clock signal Vi
dclk is an input from VSM 50. As mentioned above, Vidclk will have a frequency of Dotclk / 1 or Dotclk / 2, depending on the mode of operation of system 20 (see FIG. 21).

The clock block 301 is the controller 6
Includes a buffer for distributing clock signals Bcclk, Pclk and Vidclk to the logic circuit within 0. Each buffer has a tree of clocks to minimize insertion delay and clock distortion.

The Vidclk signal is used to drive the monitor timing block 308. Monitor timing block 308 is a block of logic circuitry for generating the blanking and sync outputs required to control monitor 36 (see FIG. 1). Monitor timing block 308 may be programmed to suit a wide range of different monitor characteristics, including NTSC, PAL SEACAM and VGA.

Controller 60 includes two similar logic blocks located within monitor timing block 308. These are the horizontal timing (HT) and vertical timing (VT) blocks. These blocks operate by comparing the programmed interval stored in register 302 to a free running counter (clocked by Vidiclk). A predetermined interval is monitored in each state of each block. If the interval matches the counter, the state changes.

The output of monitor timing block 308 includes VSYNC and HSYNC, which are monitor 36.
Vertical and horizontal sync signals for
Includes NC1 and CSYNC2, which are encoders 54 for controlling composite video outputs 56 and 58.
(See FIG. 1) is a synchronization signal. Monitor timing block 308 also generates a signal / Blank, which is the signal provided to VSM 50 (see Figure 4).

Monitor timing block 308 also provides the following outputs to control the transfer of data from serial ports SAMs 43A and 43B.

GDT / OE, which is a graphic VRA
Enables data transfer from M42B to SAM43B. VDD / OE, which enables data transfer from the video SAM 43B. VDSF and GDSF, which are video or graphic SAMs 43A or 43
B operates in SPLID or NON-SPILT (full SAM width used) mode to determine whether to transfer data. VSE1: VSE0, this is video S
Enables data output from AM43A. GSE1:
GSE0, which enables data output from the graphic SAM 43B. GLD and VLD are for loading graphic and video data into VSM 50, respectively. GSC and VSC, which are graphic SAM 43B and video SAM 43A, respectively.
Is a data shift clock signal for. Further XO
E is provided which controls the transmit and receive buffers between the video VRAM 42A and the microprocessor data bus 47.

The video input interface 310 sends a control signal to the video state machine 314 for VDC3
4 to VRAM 42A is requested. The addresses for these transfers are controlled by the video address generator 312.

Data is transferred from the VDC 34 to the VRAM 42A via a first-in first-out buffer (not shown) generally called "fifo". Data transfer is fifo
May start when the data is half full.

The signal HF received by the video input interface 310 from VDC 34 is from VDC to V
It indicates that fifo to RAM is half full and that at least 8 longwords of data are available to be transferred to VRAM 42A. This HF signal transitions during receipt of video in data.

The interface 310 is also the VDC 34
From the INC / ADDR (increment address / address reset) signal. The INC / ADDR signal has two uses. The first use indicates that a new line of video in the data is about to begin. INC /
The ADDR signal is provided to the video-in address generator 312, from which VR a new line is written.
An address indicating the location within AM 42A is generated and provided to address multiplexer block 304. This is due to the low / high transition of INC / ADDR, as shown in the timing diagram of FIG.
Occurs when HF is a logic one.

The second use of the INC / ADDR signal indicates that a new screen or field of video-in data is about to begin. This signal is video
It is provided to an in-address generator 312, which generates an address indicating the location in VRAM 42A at which the beginning of the video screen should be written. This operation is shown in the timing diagram of FIG.

With reference to FIGS. 30A, 30B, 31 and 32, the structure and function of the video-in or video write address generator 312 will be described in more detail.

Since the position, resolution, size and input format of the video window can be changed by the user, the total memory space required to store a single screen or field of video pixels will vary by an order of magnitude or more. obtain.

In the conventional address generation technique, the pixel data of each line is written in the adjacent memory space. To this end, the hardware and software had to keep track of the amount of data in each field and the address had to be recalculated each time the amount of data in one field changed. In addition to the complexity of implementing such a system, the system had to be very fast to change the size and position of the video window in real time.

In the present invention, a simpler video-in address generator is used. As shown in FIG. 32,
The video-in address generator 312 includes a bus address register 350, a first multiplexer 352, a line start register 354, an adder 356, a second multiplexer 358 and a write address register / incrementer 360.
including. All of these components are interconnected as shown in FIG.

Base address register 350 contains the address within VRAM 42A where the beginning of the block of data representing the field is stored. This VRAM
The address is called the base address and is programmable by software.

When the INC / ADDR and HF signals indicate that a new field of video-in data is about to begin (see FIG. 28), the line start register 354 is routed from the base address register 350 through the multiplexer 352. To receive the base address (see FIG. 31, block 362). Line start register 354 stores the address within VRAM 42A where the beginning of the block of data indicating the current scan line is stored.

Next, the write address register / incrementer 36
0 gets the address stored in the line start register 354 (see FIG. 1, block 364). The write address register / incrementer 360 is always the VRAM 42A
Contains the current address of each byte written to.

When signal HF is received from VDC 34 as described above, the data is written to the address of VRAM 42A stored in write address register / incrementer 360. Write address register / incrementer 360 is VR
It is then incremented each time AM 42A is written (see FIG. 31, block 368).

The video-in address generator 3 indicates that the INCR / ADDR and HF signals have reached the end of the scan line, as described above and shown in FIG.
12 generates the address in VRAM 42A at which the beginning of the block of data representing the next scan line should be written.

This new address is generated by adding either 1024 ("small mode") or 1536 ("big mode") bytes to the address of the line start register 354 (see Figure 31, block 370). ). The adder 356 is 1024 or 1
Add 536 bytes to the contents of the line start register 354. The value added to the line start register 354 is determined by the multiplexer 358, which is software programmable. This sum is then located via multiplexer 352 in line start register 354. The write address register / incrementer 360 then obtains the address in the line start register 354, as described above.

The line start register 354 is incremented by the same amount (1024 or 1536) each time the end of a scan line is reached until the end of the field is reached.

As stated above, and as shown in FIG. 28, when the INC / ADDR and HF signals indicate that a new field of video-in data is about to begin, the line start register 354 is set to the base address. Receives the base address stored in register 350,
This entire cycle repeats (see Figure 31, block 362).

The advantage of this method of video-in write address generation is that the address generation is independent of both the amount of data in the video field and the position of the video field on the monitor screen. Figure 30
(A) The data corresponding to the scanned line is VRAM
42A shows a memory configuration starting every 1024 bytes. In this configuration, which is called small mode, each scanned line contains up to 1024 bytes of data. In the memory configuration called big mode shown in FIG. 30B, each scanned line has 15 lines.
Used when including data up to 36 bytes. Either arrangement greatly reduces the hardware and software complexity required to perform address generation for variable size video fields.

Graphic / video data mover 320
Controls the data transfer between the SAM 43A register port and the VSM 50. This is the monitor timing generator 3
Monitor control from 08 and receive configuration bits from register block 302. These configuration bits are output enable signals VSE1: VSE0 and GSE1: GSE0.
And the shift clock signals GSC and VSC for VRAMs 42A and 42B, respectively. The configuration bit is also VSM5
Used to generate VLD and GLD signals for zero.

Refresh block 322 generates requests for VRAM refresh cycles, which are sent to access arbiter block 304 and one of the two access arbiters in the address multiplexer.

One of the two arbiters is a graphic arbiter, which controls both VRAM 42A and VRAM 42B when video-in is disabled and VRAM4 when video-in is enabled.
Control only 2B. The other arbiter is a video arbiter, which controls VRAM 42A when video-in is enabled.

This 2 arbiter is a VR between requesters.
Arbitrated ownership of AM control and address bus. The requester is a refresh block 322, a CPU interface block 300, a video-in interface 310.
And a SAM address generator 324. The arbiter has a fixed priority mechanism. For the graphic arbiter, the priority is SAM transfer, refresh and CPU. For the video arbiter, the priorities are video-in, SAM transfer, refresh, and CPU.

When a refresh request wins arbitration for an access to VRAM 42A, the arbiter signals either the video state machine 314 or the graphics state machine 326 to generate a refresh cycle. State machines 314 and 326 are S
Generate the sequence of VRAM controls for all VRAM accesses except the control for shifting data out of the RAM register. The state machine also
Address multiplexer block 304 needed to switch the row-to-column or column-to-row memory address bus
Generate control to.

Refresh requests are generated by the refresh block 322 at predetermined intervals. These intervals are registered in the register block 302.
2 of the refresh mode bits. The two refresh mode bits determine how many Bclk clocks are counted during a refresh request. An example showing the function of the mode bits is shown in table form in FIG.
9 is shown. One refresh request results in VR
It results in both AMs 42A and 42B being refreshed, regardless of how they are configured.

The SAM address generator block 324 has 2
Perform one function. First, they are NON-SPLI.
Generates the addresses needed for VRAM access in T and SPLIT modes. These accesses make the data V
Move from RAM 42A and 42B to SAM 43A and 43B, respectively. The data in the output register is SA
It is shifted out from the M register and transferred to the VSM 50.

The second function of SAM address generator block 324 is to request state machine 314 or 326 to perform the data transfer.

There are two SAM address generators in block 324, one for graphics and the other for SAM.
One is for video. When video-in is disabled, only the graphic address generator is used. These generators interface with monitor timing block 306 and state machines 314 and 312 to determine the next address for the next data transfer.

When is the requester NON-SPLIT and S
Determine if a PLIT transfer is needed. NON-SPLIT
Transfer is required before the start of the line of graphics begins. These are also required before the beginning of the start of a line of video. For SPLIT transfer, SAM register 4
Required after a shift count of 128 is received by 3A or 43B. The requester receives a signal from one of the state machines 314 and 324 confirming that the transfer from the SAM 43A or 43B is complete.

The detailed description of the controller 60 set forth above is a summary of the detailed description of the key functional elements of the present invention.

The present invention has been described for an integrated video graphics system having two buffers and two processing paths, one commonly used for video and the other for graphics. However, it will be apparent from the above description that a system having more than one buffer may be constructed by applying the principles described above.

In another embodiment, for example, at least one
It may be desirable to provide at least three buffers, one for graphics and two for video. Each buffer feeds a separate processing path as described above. This would allow 2 video displays on the graphic.

In another embodiment, it may be desirable to include, for example, two graphics buffers and at least one video buffer. This would be advantageous for a dedicated multitasking capable computer, where two different graphics programs run at different pixel depths.

Clearly, such a system would involve additional memory hardware costs and software complexity.

The following is a brief summary of the important elements and useful features of this invention. The invention described above includes an integrated video / graphics system for a computer. This system includes two separate buffers, one for video and one for graphics. This separate buffer feeds a color palette and video stream mixer located on a single chip. The chip may be connected to the buffer without intervening hardware. The video and graphics buffers may both be used as a single graphics buffer when the video is not displayed.

The color palette and video data stream mixer includes a pixelizer for formatting incoming video and graphic data. A controller on a separate chip supplies the video and graphics from the video and graphics buffers to the color palette and digital stream mixer. Data is,
It may be supplied at one rate from the video buffer and at another rate from the graphics so that the video and graphic pixels are formed at the same rate at the pixelizer. This allows live, full-motion, full-color video and graphics display within the computer monitor window, even when the video and graphics have different color resolutions. Separate controllers are also used to control the loading of video and graphics buffers. The loading mode may be adjusted depending on the configuration and amount of VRAM in the buffer, or may be adjusted to prepare the graphic data for the convolution operation.

The color palette and video stream mixer have two separate processing paths, one for video and one for graphics. Each processing path includes an RGB color look-up table. Because of this, graphic colors can be modified independently of the video. The graphics processing path contains circuitry to support the convolution when an interlaced monitor is used to display the graphics.

Pixels on the video and graphics processing paths in the Pixelizer are combined in a transparent logic circuit according to predetermined conditions to produce an integrated video /
Form the pixels of a graphic display. Before they are combined by the transparent logic, the video and graphic pixels may be factored so that they appear transparent when the video is overlaid on the graphic. Factoring may be implemented in shift logic to reduce the cost of the circuit.

The invention has been described in the form of preferred embodiments. However, the invention is not limited to the embodiments described and illustrated above. The invention is defined only by the claims which follow.

[Brief description of drawings]

FIG. 1 is a block diagram that schematically illustrates functional blocks of an integrated video and graphics system according to the present invention.

2 1024 kilobytes V for the system of FIG.
It is a block diagram of a RAM configuration.

FIG. 3 2048 kilobytes V for the system of FIG.
It is a block diagram of a RAM configuration.

FIG. 4 is a block diagram that schematically illustrates a pixelizer and other functional elements of a color palette and digital video stream mixer chip according to the present invention.

5 is a tabular representation of the correlation of timing clock frequencies and control bit states for the color palette and video stream mixer of FIG.

6 (A) is a diagram for transferring red, green, and blue (RGB) video transparency data to the transparency calculation circuit of FIG.
FIG. 5 is a diagram schematically showing an array, and FIG. 6B is a diagram schematically showing one array for transferring monochrome video transparency data to the transparency calculation circuit of FIG. 4.

7 is a diagram schematically showing functional elements in the transparency calculation logic circuit of FIG. 4;

FIG. 8 is a block diagram schematically showing connections to a pixelizer in the integrated video graphics system of FIG.

9 is a diagram schematically showing transfer of graphic data on a 60-bit path to the pixelizer of FIG.

FIG. 10 is a table showing a method of formatting a 1-bit pseudo color pixel from 32-bit width data.

FIG. 11 is a tabular representation of a method for formatting 2-bit pseudocolor pixels from 32-bit wide data.

FIG. 12 is a tabular representation of a method for formatting 4-bit pseudocolor pixels from 32-bit wide data.

FIG. 13 is a tabular representation of a method of formatting 8-bit pseudocolor pixels from 32-bit wide data.

FIG. 14 is a tabular representation of a method for formatting 16-bit pseudo color pixels from 32-bit wide data.

FIG. 15 is a tabular representation of a method for formatting 32-bit true color pixels from 32-bit wide data.

FIG. 16 is a schematic diagram of VRAM scan line pair mapping for a display on an interleaved monitor.

17 is a first and second view of the pixelizer of FIG.
FIG. 5 is a diagram schematically showing an arrangement of rank-ranked latches.

FIG. 18 is a timing diagram illustrating transmission of control codes for operating the first rank latches of FIG.

19 is a tabular representation of the correlation between control code settings and capture of interlaced display pixels in the first rank latch of FIG.

20 is a tabular representation of the pixel output of the second rank latch of FIG. 17 for an even field of an interlaced display.

FIG. 21 is a tabular representation of the pixel output of the second rank latch of FIG. 17 for odd fields of an interlaced display.

FIG. 22 schematically illustrates enabling integrated video and graphics windows in a monitor display.

FIG. 23 is a timing diagram showing the integration of video and graphics pixels with the video aligned with the left edge of the graphics window.

FIG. 24 is a timing diagram showing the integration of video and graphics pixels with the video offset from the left edge of the graphics window.

FIG. 25 is a timing diagram illustrating the integration of video and graphic pixels for a display having video aligned with the right edge of the graphics window.

26 is a block diagram that schematically illustrates the functional elements of a frame, buffer, and window controller for the system of FIG.

FIG. 27 is a timing diagram showing control signals for loading a new row of display data into the VRAM of FIG. 2 or 3.

FIG. 28 is a timing diagram showing control signals for loading a new screen of display data into the VRAM of FIG. 2 or 3.

FIG. 29 is a VRAM for the VRAM of FIG. 2 or FIG.
It is a diagram of a table showing the timing of the refresh cycle of.

FIG. 30A shows VRA in “small mode”.
FIG. 7B is a schematic diagram of M video write address generation, FIG.
FIG. 4 is a schematic diagram of VRAM video write address generation in “big mode”.

FIG. 31 is a flow chart diagram of control logic according to a video write address generator.

FIG. 32 is a block diagram of a video write address write generator.

[Explanation of symbols]

 20 video graphic system 25 central processing unit 27 microprocessor 28 converter 30 converter 36 monitor 40A first buffer 40B second buffer 47 data bus 50 video stream mixer 60 controller

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Eric A. Baden Argonaut Drive, Saratoga, CA 95070, USA

Claims (35)

[Claims] 1. At least two processing paths for processing video data and graphics data, one of said processing paths for temporarily storing said video data before it is processed. A buffer and means for processing the video data; another of the processing paths is another buffer for temporarily storing the graphic data before it is processed; Displaying integrated video and graphics, including means for processing the graphic data, and further including means for combining the processed video and graphic data to form an integrated video and graphic display. System for. 2. The system of claim 1, wherein the video processing means includes means for formatting the video data into video pixels and means for formatting the graphic data into graphic pixels. . 3. Means for transferring data from said buffer to said video processing means at a first data rate and means for transferring data from said another buffer to said graphics processing means at a second data rate. 3. The system of claim 2, further comprising means, wherein the first and second data rates are selected such that the formatting means form video pixels and graphic pixels at equal rates. 4. A predetermined coefficient before the video pixels and the graphic pixels are summed such that a video window in the integrated video and graphic display looks like a blend of the video pixels and the graphic pixels. The system of claim 3, further comprising means for scaling by multiplying the video pixels and the graphics pixels. 5. Controlling transfer of said video data representing a matrix of first pixels having a depth of first pixels to one of said processing paths at a first data rate,
Controlling the transfer of the graphic data representing a matrix of second pixels having a depth of the second pixels to another one of the processing paths at a second data rate, wherein the formatting means controls the video pixels and The system of claim 2, further comprising a controller for adjusting the first and second data rates to form the graphic pixels at the same rate. 6. A system for displaying integrated video and graphics, comprising: a video processing path for processing video data; and a graphics processing path for processing graphic data. The path includes a first buffer for temporarily storing the video data before it is processed, and means for processing the video data, and the graphic processing path is the graphic data. A second buffer for temporarily storing the image data before it is processed, and means for processing the graphic data, and further processed to form an integrated video and graphic display. A system including means for combining video and graphic data. 7. The system of claim 6, wherein each of the video data processing means and the graphic data processing means comprises a color look-up table. 8. The system of claim 7, wherein the video processing means includes means for formatting the video data into video pixels and means for formatting the graphic data into graphic pixels. . 9. Means for transferring data from said first buffer to said video processing means at a first data rate; and data from said second buffer to said graphics processing means at a second data rate. Means for transferring, the first and second data rates being selected such that the formatting means form the video pixels and the graphic pixels at an equal rate. system. 10. A video data stream mixer including a video pixel processing path, a graphic pixel processing path, and a pixel formatting means, the pixel formatting means providing a first pixel depth at a first data rate. Means for receiving video data, means for forming video pixels from the video data, and means for sending the video pixels to the video pixel processing path, the pixel formatting means comprising: Means for receiving graphic data having a depth of a second pixel at a data rate of, a means for forming a graphic pixel from the video data, and a means for sending the graphic pixel to the graphic pixel processing path. And including the first and And a second data rate are selected such that the video pixel and the graphic pixel are formed at the same rate independently of the depth of the first and second pixels, and further from the video processing path. Video pixels of the graphics processing path from the graphics processing path in a predetermined manner,
A video data stream mixer including means for forming pixels of an integrated video and graphic display. 11. The video stream mixer of claim 10, wherein each of the video pixel processing path and the graphic pixel processing path comprises a color look-up table. 12. The combining means comprises the video pixels at a predetermined coefficient before video windows in the integrated video and graphic display are summed to appear as a blend of the video pixels and the graphic pixels. 11. The video stream mixer of claim 10, including means for scaling by multiplying the graphics pixels with. 13. The video stream mixer of claim 12, wherein the graphics processing path includes convolution calculation means for preparing graphic pixels for display on an interlaced monitor. 14. The video data receiving means and the graphic data receiving means each have a 32-bit width, and a single 64 for receiving only graphic data.
Video stream mixer according to claim 12, which may be arranged to form a bit width means. 15. A video stream mixer according to claim 10, wherein said combining means is only operable when said video pixel is in said video processing path. 16. A controller for an integrated video and graphic display system, the transfer of data representing a matrix of first pixels from a first buffer to a first processing path at a first data rate. Means for controlling the depth of the first pixel, the first processing path including first means for forming a pixel from the first pixel data. Means for controlling the transfer of data representing a matrix of second pixels from the second buffer to the second processing path at a second data rate, the second processing path comprising: Second means for forming a pixel from second pixel data, the second pixel having a depth of a second pixel, and further comprising the first pixel Preliminary the second pixel is the first
Controller for adjusting the first and second data rates to be formed at equal rates by each of the forming means and the second forming means. 17. The controller of claim 16, wherein the first pixel is a video pixel and the second pixel is a graphics pixel. 18. The controller of claim 16, wherein the first pixel and the second pixel are graphic pixels. 19. The controller of claim 18, wherein the first and second pixels are from a common source. 20. Loading the first pixel into the first buffer and the second pixel into the second buffer in a predetermined order for display on an interlaced monitor. 20. The controller of claim 19, further comprising means for controlling. 21. The first of the first processing paths
Further pixels, and means for controlling the processing of said second pixel in said second processing path,
The controller according to claim 16. 22. A controller for an integrated video and graphic display system, comprising means for controlling the transfer of data representing a matrix of pixels from a source to a buffer at a predetermined data rate, The pixel has a depth of a pixel, the data rate is determined by the depth of the pixel, and the means for further controlling is a VRAM.
A write address generator is included, said address generator to be written with first register means for storing the base VRAM address and second register means for storing the VRAM address of the start of the line. Third register means for storing a byte VRAM address, and further means for transferring the base VRAM address stored in the first register means to the line register means; Means for transferring said VRAM address of the start of the line stored in said register means to said third register means and means for incrementing said third register means by one byte, whereby The VRAM address of the subsequent byte is stored there and further increments the second register means by a fixed number. Includes means of order, thereby VRAM address of the start of the new line is stored there, controller. 23. The controller of claim 22, wherein the constant is 1024 bytes. 24. The controller of claim 22, wherein the constant is 1536 bytes. 25. A controller for an integrated video and graphics display system compatible with monitors having different scan rates, the first data rate to the first buffer at a first data rate. Means for controlling the transfer of data representative of the matrix of first pixels of the first pixel of the first matrix of pixels, the first matrix of pixels having a depth of the first pixels, and at a second data rate of the second matrix of pixels. Means for controlling the transfer of data representing a matrix of second pixels from the source of the second buffer to the second buffer, the second matrix of pixels having a depth of the second pixels, and Three
Means for controlling the transfer of the first matrix of pixels from the first buffer to the first processing path at a data rate of, and a second buffer from the second buffer at a fourth data rate. Means for controlling the transfer of said second matrix of pixels to said processing path, said first matrix of pixels and said second matrix of pixels at a rate proportional to the scan rate of the monitor, Means for adjusting said first, said second, said third, and said fourth data rates for transfer to one processing path and said second processing path. 26. The controller of claim 25, wherein the first source is VDC and the second source is a central processing unit. 27. The controller of claim 26, wherein the first matrix of pixels is video pixels and the second matrix of pixels is graphics pixels. 28. The first and second matrices of pixels are from a common source.
Controller described in. 29. The controller of claim 28, wherein the first matrix of pixels and the second matrix of pixels are graphic pixels. 30. The means for controlling the transfer of data from the first source to the first buffer comprises V
A RAM write address generator, said generator being written with first register means for storing a base VRAM address, and second register means for storing a VRAM address at the start of a line. Third register means for storing the VRAM address of the power byte, and the base VR stored in the first register means
Means for transferring an AM address to the second register means; means for transferring the VRAM address of the start of a line stored in the second register means to the third register means; Means for incrementing the third register means by one byte, whereby the VRAM address of the subsequent byte is stored therein, and means for incrementing the second register means by a fixed number;
26. The controller of claim 25, wherein the VRAM address of the start of a new line is stored there. 31. The controller of claim 30, wherein the constant is 1024 bytes. 32. The controller of claim 30, wherein the constant is 1536 bytes. 33. A method for controlling transfer of video data from a source to a VRAM buffer, comprising storing a base VRAM address in a first register, the VRAM address representing the start of a line in the register. Storing, a VRAM address of the byte to be written in a third register, the base VRAM stored in the first register
Transferring an address to the second register, transferring the VRAM address of the start of a line stored in the second register to the third register, and incrementing the third register by one byte And therefore the VRAM address of the subsequent byte is stored therein, and further incrementing said second register by a constant, so that the VRAM address of the start of a new line is stored therein. . 34. The method of claim 33, wherein the constant is 1024 bytes. 35. The method of claim 33, wherein the constant is 1536 bytes.