JPH06214890A - calculator - Google Patents

Abstract

(57) [Summary] [Purpose] When erroneous data occurs in the main memory,
To obtain a computer that has the function of reading correct data and repairing erroneous data. Moreover, even if an error occurs simultaneously in the dual memory, a computer capable of avoiding the use of erroneous data is obtained. [Structure] CPU unit 1, main memory 2a and slave memory 2
b, a main memory 2a and a slave memory 2
address decode circuit 3a for accessing b, address decode circuit 3b for correcting data in the main memory 2a when a parity error occurs, main memory 2
A parity checker 4 for performing a parity check on the data a and a selector 5 for switching whether to connect the main memory 2a or the slave memory 2b. [Effect] When data has an error, it has a function of reading correct data and repairing erroneous data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a dual system memory composed of a main system memory and a slave system memory and capable of avoiding the use of erroneous data and performing error data recovery by a parity check.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional computer. In the figure, 1 is a CPU unit, 2a and 2b store the data output from the CPU unit 1 at the same time.
The main system memory and the sub system memory 3 for outputting to the memory 3 are address decode circuits for generating the memory chip select signals SAW, SAR, SBW and SBR. here,
SAW is a signal that gives write permission to the main memory, SAR
Is a signal that gives read permission to the master memory, SBW is a signal that gives write permission to the slave memory, and SBR is a signal that gives read permission to the slave memory. 4 is the main memory 2a
Is a parity checker for performing a parity check on the data of 5 above, 5 is a selector for switching whether to connect the main memory 2a and the slave memory 2b, 6 is an address bus, and 7 is a data bus.

The conventional computer is configured as described above, and at the time of writing, the address decoding circuit 3 generates the write permission signals SAW and SBW, and the writing is performed in both the main memory 2a and the slave memory 2b. A parity bit is added to the system memory 2a. At the time of reading, the address decoding circuit 3 generates the read permission signals SAR and SBR, and the data in the main memory 2a is read by the parity checker 4
Check with. If there is no parity error as a result of the check, the data in the main memory 2a is output. When a parity error is detected, the selector 5 is switched and the data of the slave memory 2b is output.

[0004]

In the conventional computer as described above, when the parity error occurs in the main system memory, the data is read unconditionally by switching to the subordinate memory and the main system memory is read. The data in the slave memory was read without knowing that erroneous data had occurred. Also, if there is an error in the slave memory, wrong data was read.

The present invention has been made to solve the above problems, and when an error data occurs in the main memory, a computer having a function of reading correct data and repairing the error data. It is also an object of the present invention to provide a configuration of a computer and a configuration of a computer that avoids the use of the restored data if there is an error.

[0006]

In the computer according to the present invention, an address decoding circuit is added to restore the data in the main memory with the data in the sub memory when a parity error occurs in the main memory. It was done.

Further, the slave memory has a parity checker so that it is possible to detect that the master memory and the slave memory simultaneously generate a parity error.

Further, by adding a comparison circuit and specifying an erroneous bit, error data in the main system memory can be repaired on a bit-by-bit basis.

Further, the slave memory is provided with a parity checker so that the error data in the master memory is restored bit by bit so that when the master memory and the slave memory simultaneously generate a parity error, it can be detected. It was done.

[0010]

According to the present invention, it is possible to provide the function of restoring the data of the master memory by using the data of the slave memory.

Also, a parity checker can be added to the slave memory to avoid the use of erroneous data.

Further, it is possible to provide a function of repairing the error bit of the main memory data by using the comparison circuit.

Further, a parity checker can be added to the slave memory of a computer having a comparison circuit for repairing the error bit to repair the error bit of the main memory data and avoid the use of erroneous data. .

[0014]

【Example】

Example 1. FIG. 1 is a block diagram of a computer showing an embodiment of the present invention. In the figure, 1, 2a, 2b, 4, 5, 6
And 7 are the same as the conventional example. Reference numeral 3a is an address decode circuit for accessing the master memory 2a and slave memory 2b during normal operation, 3b is an address decode circuit for permitting writing only to the master memory 2a when a parity error occurs, and SAWb is an address decode circuit. This is a write enable signal for the main memory 2a generated by 3b.
Note that FIG. 1 shows a state in which data is written in the main system memory 2a and the sub system memory 2b and the contents of the main system memory 2a are read.

In the above-mentioned computer, in the write operation, the write permission signals SAW and SBW generated by the address decode circuit 3a are used to write data in the main memory 2a and the slave memory 2b as in the conventional example. At the time of reading, the main system memory 2 generated by the address decoding circuit 3a
The master memory 2a and the slave memory 2b are accessed by the read permission signal SAR of "a" and the read permission signal SBR of the slave memory 2b. The output data is determined by the parity checker 4 based on the result of the parity check of the data in the main memory 2a. If no parity error is detected, the selector 5 operates as shown in FIG.
The data of is output.

When the parity checker 4 detects a parity error in the data of the master memory 2a, the selector 5 switches as shown in FIG. 2 and outputs the data of the slave memory 2b. At the same time, the main-system write enable signal SAWb is generated by the address decoding circuit 3b, and the data in the sub-system memory 2b is written. FIG. 2 shows this state.

Example 2. FIG. 3 is a block diagram of a computer showing an embodiment of the present invention. In the figure, 1, 2, 3,
5, 6, and 7 are the same as the conventional example. 4a is a data parity checker of the master memory 2a, 4b is a data parity checker of the slave memory 2b, and ER is the master memory 2
It is an error signal for notifying that a parity error has occurred in a and the slave memory 2b.

Write operation and parity checker 4a
The operation when no parity error is detected is similar to that of the conventional computer. When the parity checker 4a detects a parity error, the selector 5 switches to the output of the slave memory 2b. Further, in the computer of this embodiment, the parity checker 4b checks the parity of the slave memory 2b. When no parity error is detected from the parity checker 4b, the slave memory 2b
Data is output. When a parity error is detected from the parity checker 4b, the data of the slave memory 3b is output and at the same time, the parity error signal ER is output. This parity error signal ER is sent to the CPU unit 1
You can inform that there is an error in the data by entering in.

Example 3. FIG. 4 is a block diagram of a computer showing an embodiment of the present invention. In the figure, 1, 2a, 2
b, 3a, 3b, 4, 5, 6 and 7 are the same as in the first embodiment. 12 is the data of the master memory 2a and the slave memory 2
It is a comparison circuit for comparing the data of b and determining different bits.

FIG. 5 is a diagram showing bit manipulation of data in the master memory 2a and the slave memory 2b in the third embodiment. In the figure, 13 is the main memory data, 14 is the slave memory data, 15 is the comparison result by the comparison circuit 12, 1
6 indicates an erroneous bit. As an example, the figure shows a case where bit 5 of word size data has an error. Next, the operation will be described with reference to FIGS.

In the third embodiment, when a parity error is detected in the main memory 2a, the data read from the sub memory 2b is all overwritten in the main memory 2a through the decoding circuit 3b. In the embodiment, when the parity checker 4 detects a parity error, the comparison circuit 12 compares the master memory data 13 and the slave memory data 14, and the obtained comparison circuit result 15
Identify more erroneous bits of data. Next, Example 1
Similarly, the main memory 2a is accessed through the address decoding circuit 3b, and the erroneous bit inversion is performed.

Example 4. FIG. 6 is a configuration diagram of a computer showing an embodiment of the present invention. In the figure, 1, 2, 3,
5, 6 and 7 are the same as the conventional example. 4a is a parity checker for the data in the main memory, 4b is a parity checker for the data in the slave memory, and 12 is a comparison between the data in the main memory 2a and the data in the slave memory 2b when the parity checker 4a detects a parity error. However, it is a comparison circuit for determining different bits. ER is the main memory 2a
Alternatively, it is an error signal notifying that a parity error has occurred in the slave memory 2b.

Write operation and parity checker 4a
The operation when no parity error is detected is similar to that of the conventional computer. When a parity error is detected by the parity checker 4a, the parity check of the slave memory 2b is performed by the parity checker 4b. When no error is detected by the parity checker 4b, the selector 5 switches to the output of the slave memory 2b, and the comparator circuit 12 compares the data in the master memory 2a with the data in the slave memory 2b. Specify. Next, the erroneous bit of the main memory 2a is inverted through the address decoding circuit 3b. Also,
If an error is detected by the parity checker 4b,
The parity error signal ER is output to notify the CPU unit 1 that the data has an error.

[0024]

As described above, by implementing the present invention, when erroneous data occurs in the main memory,
It is possible to obtain a computer having a function of reading correct data and repairing erroneous data.

Further, it is possible to obtain a computer capable of avoiding the use of erroneous data even when an error occurs simultaneously in the main memory and the slave memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer according to a first embodiment of the present invention when there is no parity error.

FIG. 2 is a configuration diagram of a computer according to the first embodiment of the present invention when a parity error occurs.

FIG. 3 is a configuration diagram of a computer according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a computer according to a third embodiment of the present invention.

FIG. 5 is a conceptual diagram of data manipulation of a computer according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a computer according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional computer.

[Explanation of symbols]

 1 CPU part 2a Master memory 2b Slave memory 3 Address decode circuit 4 Parity checker 5 Selector 6 Address bus 7 Data bus 12 Comparison circuit 13 Master memory data 14 Slave memory data 15 Comparison circuit result 16 Error bit

Claims (4)

[Claims] 1. A main memory and a slave memory, a main memory and a slave memory which simultaneously store data output from the CPU and a CPU, and output data from either one to the CPU when a read request is made. Address decode circuit for accessing the memory, address decode circuit for restoring data in the main memory when a parity error occurs, parity checker for checking the parity of the data in the main memory, main memory or sub memory It is composed of a selector that switches whether to connect or not, and when there is an error in the data in the master memory, the data in the slave memory is read and the data in the master memory with the error is transferred to the slave memory. A computer having a function of restoring data. 2. An error signal is output when a parity checker for checking the parity of each of the data of the main memory and the data of the slave memory is added, and an error signal is output when an error occurs simultaneously in the dual memory. The computer according to claim 1, which is characterized in that. 3. A comparison circuit for comparing the data of the master memory and the data of the slave memory and determining different bits, wherein the erroneous data of the master memory is the data of the slave memory for each bit. The method according to claim 1, wherein the restoration is performed.
The calculator shown. 4. A parity checker for checking the parity of each of the data of the main memory and the data of the slave memory is added, and an error signal is output when an error occurs simultaneously in the dual memory. The computer according to claim 3, which is characterized.