JPH0622277B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0622277B2 JPH0622277B2 JP59106388A JP10638884A JPH0622277B2 JP H0622277 B2 JPH0622277 B2 JP H0622277B2 JP 59106388 A JP59106388 A JP 59106388A JP 10638884 A JP10638884 A JP 10638884A JP H0622277 B2 JPH0622277 B2 JP H0622277B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- electrode
- circuit
- region
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体集積回路に係り、特にI2 L回路型の論理
回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an I 2 L circuit type logic circuit.
従来のＩ2Ｌ回路を用いた論理回路では、例えば「A One-
chip I2 L Controller for Appliances」IE3 .SC-14.No.
3、1979にも記載されているように、Ｉ2Ｌ回路における
ベース領域の抵抗による電圧降下のため、ベース電極か
ら遠いゲートの電流利得が低下し、このためにフアン・
アウト数が制限され入出力数の多い論理回路を形成でき
ないという欠点があつた。すなわち、第１図に示したＩ
２Ｌ回路で形成した論理回路ＰＬＡ(Programable Logic
Array)を例にあげて説明すると、ＡＮＤプレーンへの
入力信号Ｉ，１…Ｉ，Ｎが入るベース電極ＢＡ，１…Ｂ
Ａ，Ｎを各ベース領域４ＢＡ−１…４ＢＡ−Ｎの端部に
一つだけ形成されている。第１図から明らかなように、
例えばベース領域４ＢＡ−１は、複数のトランジスタＴ
Ａ１−１，……ＴＡ１−Ｎ’に共通しているため、ベー
ス電極ＢＡ，１に近い位置のトランジスタと遠い位置の
トランジスタでは、ベース領域４ＢＡ−１の有する抵抗
によって、電流利得の差が生ずる。すなわち、第２図に
示した第１図のＡ−Ａ′断面図およびその等価回路を示
した第３図からわかるように、ベース電極ＢＡ，１から
遠いトランジスタＴＡ１−Ｎ′にはＮ′−１個のベース
抵抗ＲＢが付加され、電極ＢＡ，１に近いトランジスタ
ＴA1−１のベース・エミッタ間電圧ＶBEに比べて、抵抗
による電圧降下分だけＶBEが低下し、電流利得が小さく
なる。そのためフアン・アウト数を多くできず論理回路
の入出力数に制限を受ける欠点があつた。In the conventional logic circuit using the I 2 L circuit, for example, “A One-
chip I 2 L Controller for Appliances '' IE 3 .SC-14.No.
3, 1979, the current drop in the gate far from the base electrode is reduced due to the voltage drop due to the resistance of the base region in the I 2 L circuit, which results in
There is a drawback in that the number of outputs is limited and a logic circuit with a large number of inputs and outputs cannot be formed. That is, I shown in FIG.
A logic circuit PLA (Programmable Logic) formed by 2 L circuits
Array) as an example, the base electrodes BA, 1 ... B into which the input signals I, 1 ... I, N to the AND plane are input.
Only one A, N is formed at the end of each base region 4BA-1 ... 4BA-N. As is clear from Fig. 1,
For example, the base region 4BA-1 includes a plurality of transistors T
Since it is common to A1-1, ..., TA1-N ', a difference in current gain occurs between the transistor located near the base electrode BA, 1 and the transistor located far from the base electrode BA, 1 due to the resistance of the base region 4BA-1. . That is, as can be seen from the sectional view taken along the line AA 'in FIG. 1 shown in FIG. 2 and the equivalent circuit shown in FIG. 3, the transistors TA1-N' far from the base electrodes BA, 1 have N'- One base resistor R B is added, and V BE is reduced by a voltage drop due to the resistance and current gain is reduced as compared with the base-emitter voltage V BE of the transistor TA1-1 near the electrode BA, 1. . Therefore, the number of fan-outs cannot be increased and the number of inputs and outputs of the logic circuit is limited.
本発明の目的は、上記従来の問題を解決し、入出力数の
制限を受けることのない、Ｉ2Ｌ回路を用いた論理回路
を提供することである。An object of the present invention is to solve the above conventional problems and to provide a logic circuit using an I 2 L circuit which is not limited by the number of input / output.
上記目的を達成するため、本発明は論理回路を構成する
Ｉ２Ｌ回路のベース領域に少なくとも２つ以上の複数個
のベース電極を設け、それらベース電極を上層の導体で
接続することにより、ベース領域の抵抗による電圧降下
のゲート間格差を緩和し、入出力数に制限のない論理回
路を実現するものである。In order to achieve the above object, the present invention provides a base region of an I 2 L circuit forming a logic circuit with at least two or more base electrodes and connects the base electrodes with conductors in an upper layer. The difference between the gates of the voltage drop due to the resistance of the region is relaxed, and a logic circuit with an unlimited number of inputs and outputs is realized.
以下、本発明の実施例を説明する。第４図は本発明を用
いてＩ２Ｌ回路で構成したＰＬＡの平面図である。また
第５図は第４図のＢ−Ｂ’断面図、第６図は第５図の等
価回路である。第４図に示すようにＰＬＡのＡＮＤプレ
ーンへの入力信号Ｉ，１…Ｉ，Ｎの入るベース電極Ｂ
Ａ，１−１…ＢＡ，Ｎ−１を、各ベース領域４ＢＡ−１
…４ＢＡ−Ｎ内にそれぞれ複数個形成し、それらベース
電極を各ベース領域と平行な上層の導体Ｂ２−１，…Ｂ
２−Ｎで接続した構造にすることによつて、ベース領域
の抵抗による電圧降下の各ゲート間における差を緩和す
る。ここで入力信号Ｉ，１について述べると、第５図に
示すように、任意の複数個のベース電極ＢＡ，１−１…
ＢＡ，１−Ｉ…ＢＡ，１−Ｌをベース領域４ＢＡ−１に
設け、それらを上層の導体Ｂ２−１で接続する。この構
造によれば第６図の等価回路に示したように、トランジ
スタＴＡ１−１とＴＡ１−Ｎ′は入力信号から見てベー
ス抵抗による電圧降下は同じであり、各トランジスタ間
における電流利得の差は、著しく緩和される。このよう
に、ＡＮＤプレーンのトランジスタを接続する配線に対
して直交する（つまりベース領域に平行の）上層の導体
で複数個のベース電極を接続することにより各ゲートの
ベース・エミッタ電圧ＶBEの差を緩和でき、ベース電極
の数を適当に選ぶことにより入出力数に制限のない論理
回路の構成が可能となる。なお、ここでベース電極の数
は各トランジスタの電流利得、ベース領域のシート抵抗
値等により選択されるものである。本実施例ではＰＬＡ
のＡＮＤプレーンに複数個のベース電極を設け上層の導
体で接続したが、同様のことをＯＲプレーンに用いても
有効である。また第４図に示したレイアウト図のごとく
ゲートを接続する配線に直交して上層のベース電極配線
を形成するため、回路の高集積化が容易で大規模の論理
回路に適している。なお、本実施例ではＩ２Ｌ回路で構
成したＰＬＡについてのみ示したが、ベース抵抗による
電圧降下によつて回路構成を制御を受けるようなデコー
ダ等のＩ２Ｌ回路を用いた論理回路においても本発明は
有効である。Examples of the present invention will be described below. FIG. 4 is a plan view of a PLA composed of an I 2 L circuit using the present invention. 5 is a sectional view taken along the line BB ′ of FIG. 4, and FIG. 6 is an equivalent circuit of FIG. As shown in FIG. 4, the base electrode B into which the input signals I, 1 ... I, N to the AND plane of the PLA enter
A, 1-1 ... BA, N-1 are replaced by respective base areas 4BA-1
4A-N, a plurality of base electrodes are formed in each of 4BA-N and upper base conductors B2-1, ... B parallel to the base regions are formed.
The structure connected by 2-N reduces the difference in voltage drop between the gates due to the resistance of the base region. The input signals I, 1 will now be described. As shown in FIG. 5, an arbitrary plurality of base electrodes BA, 1-1 ...
BA, 1-I ... BA, 1-L are provided in the base region 4BA-1, and they are connected by the conductor B2-1 in the upper layer. According to this structure, as shown in the equivalent circuit of FIG. 6, the transistors TA1-1 and TA1-N 'have the same voltage drop due to the base resistance as seen from the input signal, and the difference in the current gain between the transistors. Is significantly mitigated. In this way, by connecting a plurality of base electrodes with conductors in an upper layer that are orthogonal to the wirings that connect the transistors of the AND plane (that is, parallel to the base region), the difference between the base-emitter voltage V BE of each gate. Can be relaxed, and by appropriately selecting the number of base electrodes, it becomes possible to construct a logic circuit with an unlimited number of inputs and outputs. Here, the number of base electrodes is selected according to the current gain of each transistor, the sheet resistance value of the base region, and the like. In this embodiment, PLA
Although a plurality of base electrodes are provided on the AND plane and connected by the conductor of the upper layer, the same thing can be effectively applied to the OR plane. Further, as shown in the layout diagram of FIG. 4, since the base electrode wiring of the upper layer is formed orthogonal to the wiring connecting the gates, it is easy to highly integrate the circuit and is suitable for a large-scale logic circuit. Although only the PLA configured by the I 2 L circuit is shown in the present embodiment, a logic circuit using an I 2 L circuit such as a decoder which receives control of the circuit configuration by a voltage drop due to a base resistance can be used. The present invention is effective.
本発明によれば、Ｉ２Ｌ回路を用いて構成する論理回路
において入出力数に制限を受けず、高集積なデイジタル
回路をアナロク回路を共存できる効果がある。またＰＬ
Ａに本発明を用いれば、ゲートを接続する配線と上層の
ベース電極の接続配線を直交できるため回路の高集積化
に極めて効果がある。According to the present invention, there is an effect that a highly integrated digital circuit and an analog circuit can coexist without being limited by the number of inputs and outputs in a logic circuit configured by using an I 2 L circuit. Also PL
If the present invention is used for A, the wiring for connecting the gate and the connecting wiring for the base electrode in the upper layer can be orthogonal to each other, which is extremely effective for high integration of the circuit.
第１図は従来技術によるＩ２Ｌ回路で構成したＰＬＡの
レイアウトを示す平面図、第２図は第１図のＡ−Ａ′線
断面図、第３図は第２図の等価回路、第４図は本発明に
よるＩ２Ｌ回路で構成したＰＬＡのレイアウトを示す平
面図、第５図は第４図のＢ−Ｂ′線断面図、第６図は第
５図の等価回路図である。 １……第１導電型半導体基板、２……第１導電型半導体
拡散層、３……第１導電型半導体層、４ＩＮＪ１，４Ｉ
ＮＪ２，４ＢＡ−１…４ＢＡ−Ｎ……第２導電型半導体
拡散層、５……第１導電型半導体拡散層、６，６０……
絶縁膜、ＢＡ，１…ＢＡ，Ｎ……ベース電極、ＴＡ１−
１…ＴＡ１−Ｊ，ＴＡ１−ＪＨ…ＴＡ１−Ｎ′−１，Ｔ
Ａ１−Ｎ′……コレクタ電極、ＩＮＪ１，ＩＮＪ２……
インジエクタ電極、Ｉ，１…Ｉ，Ｎ……入力信号、Ｏ，
１…Ｏ，Ｍ……出力信号、ＲＢ……ベース抵抗、ＢＡ，
１−１…ＢＡ，１−Ｉ…ＢＡ，１−Ｌ，ＢＡ，Ｎ−１…
ＢＡ，Ｎ−Ｉ…ＢＡ，Ｎ−Ｌ……ベース電極、Ｂ２−１
…Ｂ２−Ｎ……上層の導体。FIG. 1 is a plan view showing a layout of a PLA composed of an I 2 L circuit according to the prior art, FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1, FIG. 3 is an equivalent circuit of FIG. FIG. 4 is a plan view showing a layout of a PLA composed of I 2 L circuits according to the present invention, FIG. 5 is a sectional view taken along the line BB ′ of FIG. 4, and FIG. 6 is an equivalent circuit diagram of FIG. . 1 ... 1st conductivity type semiconductor substrate, 2 ... 1st conductivity type semiconductor diffusion layer, 3 ... 1st conductivity type semiconductor layer, 4INJ1, 4I
NJ2, 4BA-1 ... 4BA-N ... Second conductivity type semiconductor diffusion layer, 5 ... First conductivity type semiconductor diffusion layer, 6, 60.
Insulating film, BA, 1 ... BA, N ... Base electrode, TA1-
1 ... TA1-J, TA1-JH ... TA1-N'-1, T
A1-N '... collector electrode, INJ1, INJ2 ...
Indicator electrodes, I, 1 ... I, N ... Input signal, O,
1 ... O, M ...... output signal, R B ...... base resistance, BA,
1-1 ... BA, 1-I ... BA, 1-L, BA, N-1 ...
BA, NI ... BA, NL ... Base electrode, B2-1
... B2-N ... upper layer conductor.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡部 隆博 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 林 誠 東京都小平市上水本町1479番地 日立マイ クロコンピユータエンジニアリング株式会 社内 (72)発明者 則末 勝博 東京都小平市上水本町1479番地 日立マイ クロコンピユータエンジニアリング株式会 社内 (56)参考文献 特開 昭54−66784（ＪＰ，Ａ) 特開 昭58−206171（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takahiro Okabe 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Makoto Hayashi, 1479, Kamimizuhonmachi, Kodaira, Tokyo, Hitachi My Clos Computer Computer Engineering Stock Company In-house (72) Inventor Katsuhiro Norisue 1479 Kamisuihoncho, Kodaira-shi, Tokyo Hitachi Mycro Computer Engineering Stock Company In-house (56) Reference JP 54-66784 (JP, A) JP 58- 206171 (JP, A)
Claims (1)
形成された平面形状が帯状である複数の第１のベース領
域および当該第１のベース領域とほぼ直交する方向に配
置された平面形状が帯状で互いに平行な複数の第２ベー
ス領域と、上記第１のベース領域の複数の所定部分にそ
れぞれ接続された第１のベース電極と、上記第１のベー
ス領域の表面領域内に形成された上記ベース領域とは逆
の導電型を有する複数の第１のコレクタ領域と、当該第
１のコレクタ領域に接続された第１のコレクタ電極と、
上記第１のベース領域の上方に上記第１のベース領域と
平行に形成され、上記第１のベース電極にそれぞれ接続
された導電性膜を具備し、上記第２ベース領域にはそれ
ぞれ第２のベース電極が形成され、所定の当該第２のベ
ース電極が上記第１のコレクタ電極と接続されており、
かつ、上記第２のベース電極と上記第１のコレクタ電極
は、１対１では対応しないことを特徴とする半導体集積
回路。1. A plurality of first base regions formed in parallel with each other in a planar shape in a surface region of a semiconductor substrate and having planar shapes arranged in a direction substantially orthogonal to the first base regions. Are formed in the surface region of the first base region, a plurality of second base regions that are strip-shaped and parallel to each other, a first base electrode that is connected to a plurality of predetermined portions of the first base region, respectively. A plurality of first collector regions having a conductivity type opposite to that of the base region, and a first collector electrode connected to the first collector regions,
A conductive film is formed above the first base region in parallel with the first base region and connected to the first base electrode, and the second base region is provided with a second conductive film. A base electrode is formed, and the predetermined second base electrode is connected to the first collector electrode,
In addition, the semiconductor integrated circuit is characterized in that the second base electrode and the first collector electrode do not correspond one-to-one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59106388A JPH0622277B2 (en) | 1984-05-28 | 1984-05-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59106388A JPH0622277B2 (en) | 1984-05-28 | 1984-05-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60250646A JPS60250646A (en) | 1985-12-11 |
| JPH0622277B2 true JPH0622277B2 (en) | 1994-03-23 |
Family
ID=14432313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59106388A Expired - Lifetime JPH0622277B2 (en) | 1984-05-28 | 1984-05-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622277B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466784A (en) * | 1977-11-08 | 1979-05-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS58206171A (en) * | 1982-05-26 | 1983-12-01 | Nec Corp | Semiconductor integrated circuit device |
-
1984
- 1984-05-28 JP JP59106388A patent/JPH0622277B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60250646A (en) | 1985-12-11 |
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